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| Intel(R) I/O Controller Hub 7 (ICH7) Family Datasheet -- For the Intel(R) 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O Controller Hubs April 2007 Document Number: 307013-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) I/O Controller Hub 7 (ICH7) Family chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005-2007, Intel Corporation 2 Intel (R) ICH7 Family Datasheet Contents 1 Introduction ............................................................................................................ 39 1.1 Overview ......................................................................................................... 42 1.2 Intel(R) ICH7 Family High-Level Component Differences ........................................... 50 Signal Description ................................................................................................... 51 2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 55 2.2 PCI Express* (Desktop and Mobile Only) .............................................................. 55 2.3 Platform LAN Connect Interface (Desktop and Mobile Only)..................................... 56 2.4 EEPROM Interface (Desktop and Mobile Only)........................................................ 56 2.5 Firmware Hub Interface (Desktop and Mobile Only)................................................ 56 2.6 PCI Interface .................................................................................................... 57 2.7 Serial ATA Interface (Desktop and Mobile Only) ..................................................... 59 2.8 IDE Interface .................................................................................................... 60 2.9 LPC Interface.................................................................................................... 62 2.10 Interrupt Interface ............................................................................................ 62 2.11 USB Interface ................................................................................................... 63 2.12 Power Management Interface.............................................................................. 64 2.13 Processor Interface............................................................................................ 66 2.14 SMBus Interface................................................................................................ 68 2.15 System Management Interface............................................................................ 68 2.16 Real Time Clock Interface ................................................................................... 69 2.17 Other Clocks..................................................................................................... 69 2.18 Miscellaneous Signals ........................................................................................ 70 2.19 AC '97/Intel(R) High Definition Audio Link ............................................................... 71 2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72 2.21 Intel(R) Quick Resume Technology (Intel(R) ICH7DH Only) ......................................... 72 2.22 General Purpose I/O Signals ............................................................................... 72 2.23 Power and Ground ............................................................................................. 74 2.24 Pin Straps ........................................................................................................ 76 2.24.1 Functional Straps ................................................................................... 76 2.24.2 External RTC Circuitry ............................................................................. 78 Intel(R) ICH7 Pin States............................................................................................. 79 3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 79 3.2 IDE Integrated Series Termination Resistors.......................................................... 80 3.3 Output and I/O Signals Planes and States............................................................. 81 3.4 Power Planes for Input Signals ............................................................................ 90 Intel(R) ICH7 and System Clock Domains................................................................... 95 Functional Description ............................................................................................. 99 5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 99 5.1.1 PCI Bus Interface ................................................................................... 99 5.1.2 PCI Bridge As an Initiator ........................................................................ 99 5.1.2.1 Memory Reads and Writes.......................................................... 99 5.1.2.2 I/O Reads and Writes .............................................................. 100 5.1.2.3 Configuration Reads and Writes ................................................ 100 5.1.2.4 Locked Cycles......................................................................... 100 5.1.2.5 Target / Master Aborts ............................................................. 100 5.1.2.6 Secondary Master Latency Timer............................................... 100 5.1.2.7 Dual Address Cycle (DAC) ........................................................ 100 5.1.2.8 Memory and I/O Decode to PCI................................................. 101 5.1.3 Parity Error Detection and Generation ..................................................... 101 5.1.4 PCIRST# ............................................................................................. 101 2 3 4 5 Intel (R) ICH7 Family Datasheet 3 5.2 5.3 5.4 5.5 5.1.5 Peer Cycles .......................................................................................... 102 5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102 5.1.7 IDSEL to Device Number Mapping ........................................................... 103 5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103 5.2.1 Interrupt Generation ............................................................................. 103 5.2.2 Power Management............................................................................... 104 5.2.2.1 S3/S4/S5 Support ................................................................... 104 5.2.2.2 Resuming from Suspended State ............................................... 104 5.2.2.3 Device Initiated PM_PME Message ............................................. 104 5.2.2.4 SMI/SCI Generation................................................................. 105 5.2.3 SERR# Generation ................................................................................ 105 5.2.4 Hot-Plug .............................................................................................. 106 5.2.4.1 Presence Detection .................................................................. 106 5.2.4.2 Message Generation ................................................................ 106 5.2.4.3 Attention Button Detection ....................................................... 107 5.2.4.4 SMI/SCI Generation................................................................. 107 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) .......................................... 108 5.3.1 LAN Controller PCI Bus Interface............................................................. 108 5.3.1.1 Bus Slave Operation ................................................................ 109 5.3.1.2 CLKRUN# Signal (Mobile Only).................................................. 110 5.3.1.3 PCI Power Management ........................................................... 110 5.3.1.4 PCI Reset Signal...................................................................... 110 5.3.1.5 Wake-Up Events...................................................................... 111 5.3.1.6 Wake on LAN* (Preboot Wake-Up) ............................................. 112 5.3.2 Serial EEPROM Interface ........................................................................ 112 5.3.3 CSMA/CD Unit ...................................................................................... 113 5.3.3.1 Full Duplex ............................................................................. 113 5.3.3.2 Flow Control ........................................................................... 113 5.3.3.3 VLAN Support ......................................................................... 113 5.3.4 Media Management Interface ................................................................. 113 5.3.5 TCO Functionality ................................................................................. 114 5.3.5.1 Advanced TCO Mode ................................................................ 114 Alert Standard Format (ASF) (Desktop and Mobile Only) ....................................... 115 5.4.1 ASF Management Solution Features/Capabilities ....................................... 116 5.4.2 ASF Hardware Support .......................................................................... 117 5.4.2.1 Intel(R) 82562EM/EX ................................................................. 117 5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................ 117 5.4.2.3 Legacy Sensor SMBus Devices .................................................. 117 5.4.2.4 Remote Control SMBus Devices ................................................. 117 5.4.2.5 ASF Sensor SMBus Devices....................................................... 117 5.4.3 ASF Software Support ........................................................................... 118 LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 118 5.5.1 LPC Interface ....................................................................................... 118 5.5.1.1 LPC Cycle Types ...................................................................... 119 5.5.1.2 Start Field Definition ................................................................ 119 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ..................................... 120 5.5.1.4 SIZE...................................................................................... 120 5.5.1.5 SYNC..................................................................................... 121 5.5.1.6 SYNC Time-Out ....................................................................... 121 5.5.1.7 SYNC Error Indication .............................................................. 121 5.5.1.8 LFRAME# Usage...................................................................... 122 5.5.1.9 I/O Cycles .............................................................................. 122 5.5.1.10 Bus Master Cycles ................................................................... 122 5.5.1.11 LPC Power Management ........................................................... 122 5.5.1.12 Configuration and Intel(R) ICH7 Implications................................. 123 5.5.2 SERR# Generation ................................................................................ 123 4 Intel (R) ICH7 Family Datasheet 5.6 5.7 5.8 5.9 5.10 DMA Operation (D31:F0) .................................................................................. 124 5.6.1 Channel Priority ................................................................................... 124 5.6.1.1 Fixed Priority.......................................................................... 125 5.6.1.2 Rotating Priority ..................................................................... 125 5.6.2 Address Compatibility Mode ................................................................... 125 5.6.3 Summary of DMA Transfer Sizes ............................................................. 125 5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words ................................................................................... 126 5.6.4 Autoinitialize........................................................................................ 126 5.6.5 Software Commands............................................................................. 126 LPC DMA (Desktop and Mobile Only) .................................................................. 127 5.7.1 Asserting DMA Requests........................................................................ 127 5.7.2 Abandoning DMA Requests .................................................................... 127 5.7.3 General Flow of DMA Transfers ............................................................... 128 5.7.4 Terminal Count .................................................................................... 128 5.7.5 Verify Mode ......................................................................................... 128 5.7.6 DMA Request Deassertion...................................................................... 129 5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 129 8254 Timers (D31:F0) ..................................................................................... 130 5.8.1 Timer Programming .............................................................................. 131 5.8.2 Reading from the Interval Timer............................................................. 132 5.8.2.1 Simple Read........................................................................... 132 5.8.2.2 Counter Latch Command.......................................................... 132 5.8.2.3 Read Back Command .............................................................. 132 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133 5.9.1 Interrupt Handling................................................................................ 134 5.9.1.1 Generating Interrupts.............................................................. 134 5.9.1.2 Acknowledging Interrupts ........................................................ 134 5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135 5.9.2 Initialization Command Words (ICWx) ..................................................... 135 5.9.2.1 ICW1 .................................................................................... 135 5.9.2.2 ICW2 .................................................................................... 136 5.9.2.3 ICW3 .................................................................................... 136 5.9.2.4 ICW4 .................................................................................... 136 5.9.3 Operation Command Words (OCW) ......................................................... 136 5.9.4 Modes of Operation .............................................................................. 136 5.9.4.1 Fully Nested Mode................................................................... 136 5.9.4.2 Special Fully-Nested Mode........................................................ 137 5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137 5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137 5.9.4.5 Poll Mode ............................................................................... 137 5.9.4.6 Cascade Mode ........................................................................ 138 5.9.4.7 Edge and Level Triggered Mode................................................. 138 5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138 5.9.4.9 Normal End of Interrupt........................................................... 138 5.9.4.10 Automatic End of Interrupt Mode .............................................. 138 5.9.5 Masking Interrupts ............................................................................... 139 5.9.5.1 Masking on an Individual Interrupt Request ................................ 139 5.9.5.2 Special Mask Mode.................................................................. 139 5.9.6 Steering PCI Interrupts ......................................................................... 139 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140 5.10.1 Interrupt Handling................................................................................ 140 5.10.2 Interrupt Mapping ................................................................................ 140 5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141 5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141 5.10.4.1 Edge-Triggered Operation......................................................... 142 Intel (R) ICH7 Family Datasheet 5 5.11 5.12 5.13 5.14 5.10.4.2 Level-Triggered Operation......................................................... 142 5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142 5.10.4.4 Interrupt Message Format ........................................................ 142 Serial Interrupt (D31:F0) .................................................................................. 143 5.11.1 Start Frame ......................................................................................... 143 5.11.2 Data Frames ........................................................................................ 144 5.11.3 Stop Frame .......................................................................................... 144 5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 144 5.11.5 Data Frame Format ............................................................................... 145 Real Time Clock (D31:F0) ................................................................................. 146 5.12.1 Update Cycles ...................................................................................... 146 5.12.2 Interrupts ............................................................................................ 147 5.12.3 Lockable RAM Ranges............................................................................ 147 5.12.4 Century Rollover ................................................................................... 147 5.12.5 Clearing Battery-Backed RTC RAM ........................................................... 147 Processor Interface (D31:F0) ............................................................................ 149 5.13.1 Processor Interface Signals .................................................................... 149 5.13.1.1 A20M# (Mask A20).................................................................. 149 5.13.1.2 INIT# (Initialization)................................................................ 150 5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error) .................................................................................... 150 5.13.1.4 NMI (Non-Maskable Interrupt) .................................................. 151 5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........ 151 5.13.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 151 5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ...................... 151 5.13.2 Dual-Processor Issues (Desktop Only) ..................................................... 152 5.13.2.1 Signal Differences ................................................................... 152 5.13.2.2 Power Management ................................................................. 152 Power Management (D31:F0) ............................................................................ 153 5.14.1 Features .............................................................................................. 153 5.14.2 Intel(R) ICH7 and System Power States ..................................................... 153 5.14.3 System Power Planes ............................................................................ 156 5.14.4 SMI#/SCI Generation ............................................................................ 156 5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159 5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159 5.14.5 Dynamic Processor Clock Control ............................................................ 159 5.14.5.1 Transition Rules among S0/Cx and Throttling States..................... 160 5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) ................................. 161 5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) .................. 161 5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) ............. 161 5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................ 161 5.14.6.1 Conditions for Checking the PCI Clock ........................................ 162 5.14.6.2 Conditions for Maintaining the PCI Clock..................................... 162 5.14.6.3 Conditions for Stopping the PCI Clock ........................................ 162 5.14.6.4 Conditions for Re-Starting the PCI Clock ..................................... 162 5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............ 162 5.14.7 Sleep States ........................................................................................ 163 5.14.7.1 Sleep State Overview............................................................... 163 5.14.7.2 Initiating Sleep State ............................................................... 163 5.14.7.3 Exiting Sleep States................................................................. 163 5.14.7.4 PCI Express* WAKE# Signal and PME Event Message ( Desktop and Mobile only) ......................................................... 165 5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 165 5.14.8 Thermal Management............................................................................ 166 5.14.8.1 THRM# Signal......................................................................... 166 5.14.8.2 Processor Initiated Passive Cooling ............................................ 166 5.14.8.3 THRM# Override Software Bit ................................................... 167 6 Intel (R) ICH7 Family Datasheet 5.15 5.16 5.17 5.14.8.4 Active Cooling ........................................................................ 167 5.14.9 Event Input Signals and Their Usage ....................................................... 167 5.14.9.1 PWRBTN# (Power Button) ........................................................ 167 5.14.9.2 RI# (Ring Indicator)................................................................ 168 5.14.9.3 PME# (PCI Power Management Event) ....................................... 169 5.14.9.4 SYS_RESET# Signal ................................................................ 169 5.14.9.5 THRMTRIP# Signal.................................................................. 169 5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170 5.14.10ALT Access Mode .................................................................................. 170 5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 171 5.14.10.2PIC Reserved Bits ................................................................... 173 5.14.10.3Read Only Registers with Write Paths in ALT Access Mode............. 173 5.14.11System Power Supplies, Planes, and Signals ............................................ 173 5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173 5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 174 5.14.11.3PWROK Signal ........................................................................ 174 5.14.11.4CPUPWRGD Signal .................................................................. 175 5.14.11.5VRMPWRGD Signal.................................................................. 175 5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175 5.14.11.7Controlling Leakage and Power Consumption during Low-Power States ................................................................................... 175 5.14.12Clock Generators.................................................................................. 176 5.14.12.1Clock Control Signals from Intel(R) ICH7 to Clock Synthesizer (Mobile/Ultra Mobile Only)....................................... 176 5.14.13Legacy Power Management Theory of Operation ....................................... 177 5.14.13.1APM Power Management (Desktop Only) .................................... 177 5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only) ........... 177 System Management (D31:F0).......................................................................... 178 5.15.1 Theory of Operation.............................................................................. 178 5.15.1.1 Detecting a System Lockup ...................................................... 178 5.15.1.2 Handling an Intruder ............................................................... 178 5.15.1.3 Detecting Improper Firmware Hub Programming ......................... 179 5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179 IDE Controller (D31:F1) ................................................................................... 183 5.16.1 PIO Transfers ....................................................................................... 183 5.16.1.1 PIO IDE Timing Modes ............................................................. 184 5.16.1.2 IORDY Masking....................................................................... 184 5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184 5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185 5.16.2 Bus Master Function ............................................................................. 185 5.16.2.1 Physical Region Descriptor Format............................................. 185 5.16.2.2 Bus Master IDE Timings ........................................................... 186 5.16.2.3 Interrupts .............................................................................. 186 5.16.2.4 Bus Master IDE Operation ........................................................ 187 5.16.2.5 Error Conditions...................................................................... 188 5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188 5.16.3.1 Operation .............................................................................. 189 5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190 5.16.5 ATA Swap Bay...................................................................................... 190 5.16.6 SMI Trapping ....................................................................................... 190 SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191 5.17.1 Theory of Operation.............................................................................. 192 5.17.1.1 Standard ATA Emulation .......................................................... 192 5.17.1.2 48-Bit LBA Operation............................................................... 192 5.17.2 SATA Swap Bay Support ........................................................................ 193 5.17.3 Intel(R) Matrix Storage Technology Configuration (Intel(R) ICH7R, ICH7DH, and ICH7-M DH Only) ........................................................................... 193 Intel (R) ICH7 Family Datasheet 7 5.18 5.19 5.20 5.17.3.1 Intel(R) Matrix Storage Manager RAID Option ROM ........................ 194 5.17.4 Power Management Operation ................................................................ 194 5.17.4.1 Power State Mappings.............................................................. 194 5.17.4.2 Power State Transitions ............................................................ 195 5.17.4.3 SMI Trapping (APM) ................................................................. 196 5.17.5 SATA LED ............................................................................................ 196 5.17.6 AHCI Operation (Intel(R) ICH7R, ICH7DH, and Mobile Only) ......................... 196 5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................. 197 High Precision Event Timers .............................................................................. 197 5.18.1 Timer Accuracy..................................................................................... 197 5.18.2 Interrupt Mapping................................................................................. 198 5.18.3 Periodic vs. Non-Periodic Modes .............................................................. 198 5.18.4 Enabling the Timers .............................................................................. 199 5.18.5 Interrupt Levels.................................................................................... 199 5.18.6 Handling Interrupts............................................................................... 199 5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 200 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ............................................ 200 5.19.1 Data Structures in Main Memory ............................................................. 200 5.19.2 Data Transfers to/from Main Memory ....................................................... 200 5.19.3 Data Encoding and Bit Stuffing ............................................................... 200 5.19.4 Bus Protocol......................................................................................... 200 5.19.4.1 Bit Ordering............................................................................ 200 5.19.4.2 SYNC Field ............................................................................. 201 5.19.4.3 Packet Field Formats................................................................ 201 5.19.4.4 Address Fields......................................................................... 201 5.19.4.5 Frame Number Field ................................................................ 201 5.19.4.6 Data Field .............................................................................. 201 5.19.4.7 Cyclic Redundancy Check (CRC) ................................................ 201 5.19.5 Packet Formats..................................................................................... 201 5.19.6 USB Interrupts ..................................................................................... 201 5.19.6.1 Transaction-Based Interrupts .................................................... 202 5.19.6.2 Non-Transaction Based Interrupts .............................................. 203 5.19.7 USB Power Management ........................................................................ 204 5.19.8 USB Legacy Keyboard Operation ............................................................. 204 USB EHCI Host Controller (D29:F7).................................................................... 207 5.20.1 EHC Initialization .................................................................................. 207 5.20.1.1 BIOS Initialization ................................................................... 207 5.20.1.2 Driver Initialization .................................................................. 207 5.20.1.3 EHC Resets............................................................................. 208 5.20.2 Data Structures in Main Memory ............................................................. 208 5.20.3 USB 2.0 Enhanced Host Controller DMA ................................................... 208 5.20.4 Data Encoding and Bit Stuffing ............................................................... 208 5.20.5 Packet Formats..................................................................................... 208 5.20.6 USB 2.0 Interrupts and Error Conditions .................................................. 209 5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 209 5.20.7 USB 2.0 Power Management .................................................................. 210 5.20.7.1 Pause Feature ......................................................................... 210 5.20.7.2 Suspend Feature ..................................................................... 210 5.20.7.3 ACPI Device States .................................................................. 210 5.20.7.4 ACPI System States................................................................. 211 5.20.7.5 Mobile/Ultra Mobile Only Considerations ..................................... 211 5.20.8 Interaction with UHCI Host Controllers..................................................... 211 5.20.8.1 Port-Routing Logic ................................................................... 211 5.20.8.2 Device Connects ..................................................................... 213 5.20.8.3 Device Disconnects.................................................................. 213 5.20.8.4 Effect of Resets on Port-Routing Logic ........................................ 214 8 Intel (R) ICH7 Family Datasheet 5.21 5.22 5.23 5.24 5.25 5.26 5.20.9 USB 2.0 Legacy Keyboard Operation ....................................................... 214 5.20.10USB 2.0 Based Debug Port .................................................................... 214 5.20.10.1 Theory of Operation ............................................................... 215 SMBus Controller (D31:F3) ............................................................................... 219 5.21.1 Host Controller..................................................................................... 220 5.21.1.1 Command Protocols ................................................................ 220 5.21.2 Bus Arbitration..................................................................................... 224 5.21.3 Bus Timing .......................................................................................... 224 5.21.3.1 Clock Stretching ..................................................................... 224 5.21.3.2 Bus Time Out (Intel(R) ICH7 as SMBus Master)............................. 224 5.21.4 Interrupts / SMI#................................................................................. 225 5.21.5 SMBALERT# ........................................................................................ 226 5.21.6 SMBus CRC Generation and Checking...................................................... 226 5.21.7 SMBus Slave Interface .......................................................................... 226 5.21.7.1 Format of Slave Write Cycle ..................................................... 227 5.21.7.2 Format of Read Command........................................................ 229 5.21.7.3 Format of Host Notify Command ............................................... 231 AC '97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232 5.22.1 PCI Power Management ........................................................................ 234 5.22.2 AC-Link Overview ................................................................................. 234 5.22.2.1 Register Access ...................................................................... 236 5.22.3 AC-Link Low Power Mode....................................................................... 237 5.22.3.1 External Wake Event ............................................................... 238 5.22.4 AC '97 Cold Reset................................................................................. 239 5.22.5 AC '97 Warm Reset............................................................................... 239 5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec .......................... 239 Intel(R) High Definition Audio Overview ................................................................ 240 5.23.1 Intel(R) High Definition Audio Docking (Mobile Only) ................................... 240 5.23.1.1 Dock Sequence....................................................................... 240 5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241 5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242 5.23.1.4 Undock Sequence ................................................................... 242 5.23.1.5 Interaction Between Dock/Undock and Power Management States ................................................................................... 243 5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# .................. 243 Intel(R) Active Management Technology (Intel(R) AMT) (Desktop and Mobile Only)....... 244 5.24.1 Intel(R) AMT Features ............................................................................. 244 5.24.2 Intel(R) AMT Requirements ...................................................................... 244 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245 5.25.1 SPI Arbitration between Intel(R) ICH7 and Intel PRO 82573E ....................... 245 5.25.2 Flash Device Configurations ................................................................... 245 5.25.3 SPI Device Compatibility Requirements ................................................... 246 5.25.3.1 Intel(R) ICH7 SPI Based BIOS Only Configuration Requirements (Non-Shared Flash Configuration) ............................................. 246 5.25.3.2 Intel(R) ICH7 with Intel(R) PRO 82573E with Intel AMT Firmware Configuration Requirements (Shared Flash Configuration) ............ 246 5.25.4 Intel(R) ICH7 Compatible Command Set .................................................... 247 5.25.4.1 Required Command Set for Inter Operability............................... 247 5.25.4.2 Recommended Standard Commands.......................................... 247 5.25.4.3 Multiple Page Write Usage Model ............................................... 248 5.25.5 Flash Protection ................................................................................... 248 5.25.5.1 BIOS Range Write Protection .................................................... 248 5.25.5.2 SMI# Based Global Write Protection .......................................... 249 5.25.5.3 Shared Flash Address Range Protection...................................... 249 Intel(R) Quick Resume Technology (Digital Home Only) .......................................... 249 5.26.1 Visual Off ............................................................................................ 249 Intel (R) ICH7 Family Datasheet 9 5.27 6 5.26.2 CE-like On/Off ...................................................................................... 249 5.26.3 Intel(R) Quick Resume Technology Signals (ICH7DH Only)............................ 250 5.26.4 Power Button Sequence (ICH7DH Only) ................................................... 250 Feature Capability Mechanism ........................................................................... 251 Register and Memory Mapping ............................................................................... 253 6.1 PCI Devices and Functions ................................................................................ 254 6.2 PCI Configuration Map ...................................................................................... 255 6.3 I/O Map.......................................................................................................... 255 6.3.1 Fixed I/O Address Ranges ...................................................................... 255 6.3.2 Variable I/O Decode Ranges ................................................................... 258 6.4 Memory Map ................................................................................................... 259 6.4.1 Boot-Block Update Scheme .................................................................... 261 Chipset Configuration Registers ............................................................................. 263 7.1 Chipset Configuration Registers (Memory Space).................................................. 263 7.1.1 VCH--Virtual Channel Capability Header Register ...................................... 265 7.1.2 VCAP1--Virtual Channel Capability #1 Register ......................................... 265 7.1.3 VCAP2--Virtual Channel Capability #2 Register ......................................... 266 7.1.4 PVC--Port Virtual Channel Control Register............................................... 266 7.1.5 PVS--Port Virtual Channel Status Register ................................................ 266 7.1.6 V0CAP--Virtual Channel 0 Resource Capability Register .............................. 267 7.1.7 V0CTL--Virtual Channel 0 Resource Control Register .................................. 267 7.1.8 V0STS--Virtual Channel 0 Resource Status Register................................... 268 7.1.9 V1CAP--Virtual Channel 1 Resource Capability Register .............................. 268 7.1.10 V1CTL--Virtual Channel 1 Resource Control Register .................................. 269 7.1.11 V1STS--Virtual Channel 1 Resource Status Register................................... 269 7.1.12 RCTCL--Root Complex Topology Capabilities List Register ........................... 270 7.1.13 ESD--Element Self Description Register ................................................... 270 7.1.14 ULD--Upstream Link Descriptor Register .................................................. 270 7.1.15 ULBA--Upstream Link Base Address Register ............................................ 271 7.1.16 RP1D--Root Port 1 Descriptor Register..................................................... 271 7.1.17 RP1BA--Root Port 1 Base Address Register ............................................... 271 7.1.18 RP2D--Root Port 2 Descriptor Register..................................................... 272 7.1.19 RP2BA--Root Port 2 Base Address Register ............................................... 272 7.1.20 RP3D--Root Port 3 Descriptor Register..................................................... 272 7.1.21 RP3BA--Root Port 3 Base Address Register ............................................... 273 7.1.22 RP4D--Root Port 4 Descriptor Register..................................................... 273 7.1.23 RP4BA--Root Port 4 Base Address Register ............................................... 273 7.1.24 HDD--Intel(R) High Definition Audio Descriptor Register............................... 274 7.1.25 HDBA--Intel(R) High Definition Audio Base Address Register......................... 274 7.1.26 RP5D--Root Port 5 Descriptor Register..................................................... 274 7.1.27 RP5BA--Root Port 5 Base Address Register ............................................... 275 7.1.28 RP6D--Root Port 6 Descriptor Register..................................................... 275 7.1.29 RP6BA--Root Port 6 Base Address Register ............................................... 275 7.1.30 ILCL--Internal Link Capabilities List Register ............................................. 276 7.1.31 LCAP--Link Capabilities Register ............................................................. 276 7.1.32 LCTL--Link Control Register.................................................................... 277 7.1.33 LSTS--Link Status Register .................................................................... 277 7.1.34 RPC--Root Port Configuration Register ..................................................... 278 7.1.35 RPFN--Root Port Function Number for PCI Express Root Ports (Desktop and Mobile only) ..................................................................... 279 7.1.36 TRSR--Trap Status Register .................................................................... 280 7.1.37 TRCR--Trapped Cycle Register ................................................................ 280 7.1.38 TWDR--Trapped Write Data Register ........................................................ 280 7.1.39 IOTRn -- I/O Trap Register (0-3)............................................................. 281 7 10 Intel (R) ICH7 Family Datasheet 7.1.40 7.1.41 7.1.42 7.1.43 7.1.44 7.1.45 7.1.46 7.1.47 7.1.48 7.1.49 7.1.50 7.1.51 7.1.52 7.1.53 7.1.54 7.1.55 7.1.56 7.1.57 8 TCTL--TCO Configuration Register........................................................... 282 D31IP--Device 31 Interrupt Pin Register.................................................. 283 D30IP--Device 30 Interrupt Pin Register.................................................. 284 D29IP--Device 29 Interrupt Pin Register.................................................. 285 D28IP--Device 28 Interrupt Pin Register (Desktop and Mobile Only) ............ 286 D27IP--Device 27 Interrupt Pin Register.................................................. 287 D31IR--Device 31 Interrupt Route Register.............................................. 287 D30IR--Device 30 Interrupt Route Register.............................................. 289 D29IR--Device 29 Interrupt Route Register.............................................. 290 D28IR--Device 28 Interrupt Route Register.............................................. 292 D27IR--Device 27 Interrupt Route Register.............................................. 293 OIC--Other Interrupt Control Register ..................................................... 294 RC--RTC Configuration Register.............................................................. 295 HPTC--High Precision Timer Configuration Register ................................... 295 GCS--General Control and Status Register ............................................... 296 BUC--Backed Up Control Register ........................................................... 298 FD--Function Disable Register ................................................................ 299 CG--Clock Gating (Mobile/Ultra Mobile Only) ............................................ 301 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) ........................... 303 8.1 PCI Configuration Registers (LAN Controller--B1:D8:F0) ....................................... 303 8.1.1 VID--Vendor Identification Register (LAN Controller--B1:D8:F0) ................. 304 8.1.2 DID--Device Identification Register (LAN Controller--B1:D8:F0) ................. 304 8.1.3 PCICMD--PCI Command Register (LAN Controller--B1:D8:F0) .................... 305 8.1.4 PCISTS--PCI Status Register (LAN Controller--B1:D8:F0) .......................... 306 8.1.5 RID--Revision Identification Register (LAN Controller--B1:D8:F0) ............... 307 8.1.6 SCC--Sub Class Code Register (LAN Controller--B1:D8:F0) ........................ 307 8.1.7 BCC--Base-Class Code Register (LAN Controller--B1:D8:F0) ...................... 307 8.1.8 CLS--Cache Line Size Register (LAN Controller--B1:D8:F0) ........................ 308 8.1.9 PMLT--Primary Master Latency Timer Register (LAN Controller--B1:D8:F0)... 308 8.1.10 HEADTYP--Header Type Register (LAN Controller--B1:D8:F0) ..................... 308 8.1.11 CSR_MEM_BASE -- CSR Memory-Mapped Base Address Register (LAN Controller--B1:D8:F0)........................................... 309 8.1.12 CSR_IO_BASE -- CSR I/O-Mapped Base Address Register (LAN Controller--B1:D8:F0)................................................................... 309 8.1.13 SVID -- Subsystem Vendor Identification (LAN Controller--B1:D8:F0) ......... 309 8.1.14 SID -- Subsystem Identification (LAN Controller--B1:D8:F0)...................... 310 8.1.15 CAP_PTR -- Capabilities Pointer (LAN Controller--B1:D8:F0) ...................... 310 8.1.16 INT_LN -- Interrupt Line Register (LAN Controller--B1:D8:F0).................... 310 8.1.17 INT_PN -- Interrupt Pin Register (LAN Controller--B1:D8:F0) ..................... 311 8.1.18 MIN_GNT -- Minimum Grant Register (LAN Controller--B1:D8:F0) .............. 311 8.1.19 MAX_LAT -- Maximum Latency Register (LAN Controller--B1:D8:F0) ........... 311 8.1.20 CAP_ID -- Capability Identification Register (LAN Controller--B1:D8:F0)...... 311 8.1.21 NXT_PTR -- Next Item Pointer (LAN Controller--B1:D8:F0) ........................ 312 8.1.22 PM_CAP -- Power Management Capabilities (LAN Controller--B1:D8:F0) ...... 312 8.1.23 PMCSR -- Power Management Control/ Status Register (LAN Controller--B1:D8:F0)............................................. 313 8.1.24 PCIDATA -- PCI Power Management Data Register (LAN Controller--B1:D8:F0)................................................................... 314 8.2 LAN Control / Status Registers (CSR) (LAN Controller--B1:D8:F0).......................... 315 8.2.1 SCB_STA--System Control Block Status Word Register (LAN Controller--B1:D8:F0)................................................................... 316 8.2.2 SCB_CMD--System Control Block Command Word Register (LAN Controller--B1:D8:F0)....................................................... 317 8.2.3 SCB_GENPNT--System Control Block General Pointer Register (LAN Controller--B1:D8:F0)....................................................... 319 Intel (R) ICH7 Family Datasheet 11 8.3 PORT--PORT Interface Register (LAN Controller--B1:D8:F0) ....................... 319 EEPROM_CNTL--EEPROM Control Register (LAN Controller--B1:D8:F0)......... 321 MDI_CNTL--Management Data Interface (MDI) Control Register (LAN Controller--B1:D8:F0) ....................................................... 322 8.2.7 REC_DMA_BC--Receive DMA Byte Count Register (LAN Controller--B1:D8:F0) ................................................................... 322 8.2.8 EREC_INTR--Early Receive Interrupt Register (LAN Controller--B1:D8:F0) ................................................................... 323 8.2.9 FLOW_CNTL--Flow Control Register (LAN Controller--B1:D8:F0) ................. 323 8.2.10 PMDR--Power Management Driver Register (LAN Controller--B1:D8:F0) ....... 324 8.2.11 GENCNTL--General Control Register (LAN Controller--B1:D8:F0)................. 325 8.2.12 GENSTA--General Status Register (LAN Controller--B1:D8:F0).................... 326 8.2.13 SMB_PCI--SMB via PCI Register (LAN Controller--B1:D8:F0) ...................... 326 8.2.14 Statistical Counters (LAN Controller--B1:D8:F0) ....................................... 327 ASF Configuration Registers (LAN Controller--B1:D8:F0) ....................................... 329 8.3.1 ASF_RID--ASF Revision Identification Register (LAN Controller--B1:D8:F0) .. 330 8.3.2 SMB_CNTL--SMBus Control Register (LAN Controller--B1:D8:F0) ................ 330 8.3.3 ASF_CNTL--ASF Control Register (LAN Controller--B1:D8:F0) ..................... 331 8.3.4 ASF_CNTL_EN--ASF Control Enable Register (ASF Controller--B1:D8:F0) ..... 332 8.3.5 ENABLE--Enable Register (ASF Controller--B1:D8:F0) ............................... 333 8.3.6 APM--APM Register (ASF Controller--B1:D8:F0)........................................ 334 8.3.7 WTIM_CONF--Watchdog Timer Configuration Register (ASF Controller--B1:D8:F0) ................................................................... 334 8.3.8 HEART_TIM--Heartbeat Timer Register (ASF Controller--B1:D8:F0)............. 335 8.3.9 RETRAN_INT--Retransmission Interval Register (ASF Controller--B1:D8:F0) ................................................................... 335 8.3.10 RETRAN_PCL--Retransmission Packet Count Limit Register (ASF Controller--B1:D8:F0) ....................................................... 336 8.3.11 ASF_WTIM1--ASF Watchdog Timer 1 Register (ASF Controller--B1:D8:F0) ................................................................... 336 8.3.12 ASF_WTIM2--ASF Watchdog Timer 2 Register (ASF Controller--B1:D8:F0) ................................................................... 336 8.3.13 PET_SEQ1--PET Sequence 1 Register (ASF Controller--B1:D8:F0) ............... 337 8.3.14 PET_SEQ2--PET Sequence 2 Register (ASF Controller--B1:D8:F0) ............... 337 8.3.15 STA--Status Register (ASF Controller--B1:D8:F0) ..................................... 338 8.3.16 FOR_ACT--Forced Actions Register (ASF Controller--B1:D8:F0)................... 339 8.3.17 RMCP_SNUM--RMCP Sequence Number Register (ASF Controller--B1:D8:F0) ................................................................... 340 8.3.18 SP_MODE--Special Modes Register (ASF Controller--B1:D8:F0) .................. 340 8.3.19 INPOLL_TCONF--Inter-Poll Timer Configuration Register (ASF Controller--B1:D8:F0) ................................................................... 340 8.3.20 PHIST_CLR--Poll History Clear Register (ASF Controller--B1:D8:F0) ............ 341 8.3.21 PMSK1--Polling Mask 1 Register (ASF Controller--B1:D8:F0) ...................... 341 8.3.22 PMSK2--Polling Mask 2 Register (ASF Controller--B1:D8:F0) ...................... 342 8.3.23 PMSK3--Polling Mask 3 Register (ASF Controller--B1:D8:F0) ...................... 342 8.3.24 PMSK4--Polling Mask 4 Register (ASF Controller--B1:D8:F0) ...................... 342 8.3.25 PMSK5--Polling Mask 5 Register (ASF Controller--B1:D8:F0) ...................... 343 8.3.26 PMSK6--Polling Mask 6 Register (ASF Controller--B1:D8:F0) ...................... 343 8.3.27 PMSK7--Polling Mask 7 Register (ASF Controller--B1:D8:F0) ...................... 343 8.3.28 PMSK8--Polling Mask 8 Register (ASF Controller--B1:D8:F0) ...................... 344 8.2.4 8.2.5 8.2.6 9 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 345 9.1 PCI Configuration Registers (D30:F0) ................................................................. 345 9.1.1 VID-- Vendor Identification Register (PCI-PCI--D30:F0) ............................. 346 9.1.2 DID-- Device Identification Register (PCI-PCI--D30:F0) ............................. 346 9.1.3 PCICMD--PCI Command (PCI-PCI--D30:F0) ............................................. 346 12 Intel (R) ICH7 Family Datasheet 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.1.10 9.1.11 9.1.12 9.1.13 9.1.14 9.1.15 9.1.16 9.1.17 9.1.18 9.1.19 9.1.20 9.1.21 9.1.22 9.1.23 9.1.24 9.1.25 10 PSTS--PCI Status Register (PCI-PCI--D30:F0).......................................... 347 RID--Revision Identification Register (PCI-PCI--D30:F0)............................ 349 CC--Class Code Register (PCI-PCI--D30:F0) ............................................ 349 PMLT--Primary Master Latency Timer Register (PCI-PCI--D30:F0) ............... 350 HEADTYP--Header Type Register (PCI-PCI--D30:F0) ................................. 350 BNUM--Bus Number Register (PCI-PCI--D30:F0) ...................................... 350 SMLT--Secondary Master Latency Timer Register (PCI-PCI--D30:F0) ........... 351 IOBASE_LIMIT--I/O Base and Limit Register (PCI-PCI--D30:F0) ................. 351 SECSTS--Secondary Status Register (PCI-PCI--D30:F0) ............................ 352 MEMBASE_LIMIT--Memory Base and Limit Register (PCI-PCI--D30:F0)........ 353 PREF_MEM_BASE_LIMIT--Prefetchable Memory Base and Limit Register (PCI-PCI--D30:F0) ..................................................... 353 PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI--D30:F0) ................................................................... 354 PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI--D30:F0) ................................................................... 354 CAPP--Capability List Pointer Register (PCI-PCI--D30:F0) .......................... 354 INTR--Interrupt Information Register (PCI-PCI--D30:F0) ........................... 354 BCTRL--Bridge Control Register (PCI-PCI--D30:F0)................................... 355 SPDH--Secondary PCI Device Hiding Register (PCI-PCI--D30:F0)................ 356 DTC--Delayed Transaction Control Register (PCI-PCI--D30:F0) ................... 357 BPS--Bridge Proprietary Status Register (PCI-PCI--D30:F0) ....................... 359 BPC--Bridge Policy Configuration Register (PCI-PCI--D30:F0)..................... 360 SVCAP--Subsystem Vendor Capability Register (PCI-PCI--D30:F0).............. 361 SVID--Subsystem Vendor IDs Register (PCI-PCI--D30:F0)......................... 361 LPC Interface Bridge Registers (D31:F0) ............................................................... 363 10.1 PCI Configuration Registers (LPC I/F--D31:F0) .................................................... 363 10.1.1 VID--Vendor Identification Register (LPC I/F--D31:F0) .............................. 364 10.1.2 DID--Device Identification Register (LPC I/F--D31:F0) .............................. 364 10.1.3 PCICMD--PCI COMMAND Register (LPC I/F--D31:F0) ................................ 365 10.1.4 PCISTS--PCI Status Register (LPC I/F--D31:F0) ....................................... 365 10.1.5 RID--Revision Identification Register (LPC I/F--D31:F0) ............................ 366 10.1.6 PI--Programming Interface Register (LPC I/F--D31:F0) ............................. 366 10.1.7 SCC--Sub Class Code Register (LPC I/F--D31:F0) ..................................... 367 10.1.8 BCC--Base Class Code Register (LPC I/F--D31:F0).................................... 367 10.1.9 PLT--Primary Latency Timer Register (LPC I/F--D31:F0) ............................ 367 10.1.10HEADTYP--Header Type Register (LPC I/F--D31:F0) .................................. 367 10.1.11SS--Sub System Identifiers Register (LPC I/F--D31:F0)............................. 368 10.1.12CAPP--Capability List Pointer (LPC I/F--D31:F0) ....................................... 368 10.1.13PMBASE--ACPI Base Address Register (LPC I/F--D31:F0) .......................... 368 10.1.14ACPI_CNTL--ACPI Control Register (LPC I/F -- D31:F0) ............................. 369 10.1.15GPIOBASE--GPIO Base Address Register (LPC I/F -- D31:F0) ..................... 369 10.1.16GC--GPIO Control Register (LPC I/F -- D31:F0) ........................................ 370 10.1.17PIRQ[n]_ROUT--PIRQ[A,B,C,D] Routing Control Register (LPC I/F--D31:F0) (Desktop and Mobile Only) .......................................... 370 10.1.18SIRQ_CNTL--Serial IRQ Control Register (LPC I/F--D31:F0) ....................... 371 10.1.19PIRQ[n]_ROUT--PIRQ[E,F,G,H] Routing Control Register (LPC I/F--D31:F0) ................................................................................ 372 10.1.20LPC_I/O_DEC--I/O Decode Ranges Register (LPC I/F--D31:F0) .................. 373 10.1.21LPC_EN--LPC I/F Enables Register (LPC I/F--D31:F0)................................ 374 10.1.22GEN1_DEC--LPC I/F Generic Decode Range 1 Register (LPC I/F--D31:F0) .... 375 10.1.23GEN2_DEC--LPC I/F Generic Decode Range 2Register (LPC I/F--D31:F0)..... 375 10.1.24GEN3_DEC--LPC I/F Generic Decode Range 3Register (LPC I/F--D31:F0)..... 376 10.1.25GEN4_DEC--LPC I/F Generic Decode Range 4Register (LPC I/F--D31:F0)..... 376 10.1.26FWH_SEL1--Firmware Hub Select 1 Register (LPC I/F--D31:F0) ................. 377 Intel (R) ICH7 Family Datasheet 13 10.2 10.3 10.4 10.5 10.6 10.1.27FWH_SEL2--Firmware Hub Select 2 Register (LPC I/F--D31:F0) .................. 378 10.1.28FWH_DEC_EN1--Firmware Hub Decode Enable Register (LPC I/F--D31:F0) .. 378 10.1.29BIOS_CNTL--BIOS Control Register (LPC I/F--D31:F0) .............................. 381 10.1.30FDCAP--Feature Detection Capability ID (LPC I/F--D31:F0) ........................ 382 10.1.31FDLEN--Feature Detection Capability Length (LPC I/F--D31:F0) .................. 382 10.1.32FDVER--Feature Detection Version (LPC I/F--D31:F0) ................................ 382 10.1.33FDVCT--Feature Vector Register (LPC I/F--D31:F0) ................................... 383 10.1.34RCBA--Root Complex Base Address Register (LPC I/F--D31:F0) .................. 384 DMA I/O Registers (LPC I/F--D31:F0) ................................................................. 385 10.2.1 DMABASE_CA--DMA Base and Current Address Registers (LPC I/F--D31:F0)................................................................... 386 10.2.2 DMABASE_CC--DMA Base and Current Count Registers (LPC I/F--D31:F0) ... 387 10.2.3 DMAMEM_LP--DMA Memory Low Page Registers (LPC I/F--D31:F0) ............. 387 10.2.4 DMACMD--DMA Command Register (LPC I/F--D31:F0) .............................. 388 10.2.5 DMASTA--DMA Status Register (LPC I/F--D31:F0)..................................... 388 10.2.6 DMA_WRSMSK--DMA Write Single Mask Register (LPC I/F--D31:F0) ............ 389 10.2.7 DMACH_MODE--DMA Channel Mode Register (LPC I/F--D31:F0) ................. 390 10.2.8 DMA Clear Byte Pointer Register (LPC I/F--D31:F0) ................................... 391 10.2.9 DMA Master Clear Register (LPC I/F--D31:F0) .......................................... 391 10.2.10DMA_CLMSK--DMA Clear Mask Register (LPC I/F--D31:F0) ........................ 391 10.2.11DMA_WRMSK--DMA Write All Mask Register (LPC I/F--D31:F0)................... 392 Timer I/O Registers (LPC I/F--D31:F0) ............................................................... 392 10.3.1 TCW--Timer Control Word Register (LPC I/F--D31:F0) ............................... 393 10.3.2 SBYTE_FMT--Interval Timer Status Byte Format Register (LPC I/F--D31:F0) ................................................................................ 395 10.3.3 Counter Access Ports Register (LPC I/F--D31:F0) ...................................... 396 8259 Interrupt Controller (PIC) Registers (LPC I/F--D31:F0) ................................. 396 10.4.1 Interrupt Controller I/O MAP (LPC I/F--D31:F0) ........................................ 396 10.4.2 ICW1--Initialization Command Word 1 Register (LPC I/F--D31:F0) .............. 397 10.4.3 ICW2--Initialization Command Word 2 Register (LPC I/F--D31:F0) .............. 398 10.4.4 ICW3--Master Controller Initialization Command Word 3 Register (LPC I/F--D31:F0) ......................................................... 398 10.4.5 ICW3--Slave Controller Initialization Command Word 3 Register (LPC I/F--D31:F0) ......................................................... 399 10.4.6 ICW4--Initialization Command Word 4 Register (LPC I/F--D31:F0) .............. 399 10.4.7 OCW1--Operational Control Word 1 (Interrupt Mask) Register (LPC I/F--D31:F0) .................................................................... 400 10.4.8 OCW2--Operational Control Word 2 Register (LPC I/F--D31:F0) .................. 400 10.4.9 OCW3--Operational Control Word 3 Register (LPC I/F--D31:F0) .................. 401 10.4.10ELCR1--Master Controller Edge/Level Triggered Register (LPC I/F--D31:F0).. 402 10.4.11ELCR2--Slave Controller Edge/Level Triggered Register (LPC I/F--D31:F0) ... 403 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 404 10.5.1 APIC Register Map (LPC I/F--D31:F0) ...................................................... 404 10.5.2 IND--Index Register (LPC I/F--D31:F0) ................................................... 404 10.5.3 DAT--Data Register (LPC I/F--D31:F0) .................................................... 405 10.5.4 EOIR--EOI Register (LPC I/F--D31:F0) .................................................... 405 10.5.5 ID--Identification Register (LPC I/F--D31:F0) ........................................... 406 10.5.6 VER--Version Register (LPC I/F--D31:F0) ................................................. 406 10.5.7 REDIR_TBL--Redirection Table (LPC I/F--D31:F0)...................................... 407 Real Time Clock Registers (LPC I/F--D31:F0)....................................................... 409 10.6.1 I/O Register Address Map (LPC I/F--D31:F0) ............................................ 409 10.6.2 Indexed Registers (LPC I/F--D31:F0) ...................................................... 410 10.6.2.1 RTC_REGA--Register A (LPC I/F--D31:F0) .................................. 411 10.6.2.2 RTC_REGB--Register B (General Configuration) (LPC I/F--D31:F0). 412 10.6.2.3 RTC_REGC--Register C (Flag Register) (LPC I/F--D31:F0) ............. 413 14 Intel (R) ICH7 Family Datasheet 10.7 10.8 10.9 10.6.2.4 RTC_REGD--Register D (Flag Register) (LPC I/F--D31:F0) ............ 414 Processor Interface Registers (LPC I/F--D31:F0) ................................................. 415 10.7.1 NMI_SC--NMI Status and Control Register (LPC I/F--D31:F0) .................... 415 10.7.2 NMI_EN--NMI Enable (and Real Time Clock Index) Register (LPC I/F--D31:F0).................................................................... 416 10.7.3 PORT92--Fast A20 and Init Register (LPC I/F--D31:F0) ............................. 416 10.7.4 COPROC_ERR--Coprocessor Error Register (LPC I/F--D31:F0) .................... 417 10.7.5 RST_CNT--Reset Control Register (LPC I/F--D31:F0)................................. 417 Power Management Registers (PM--D31:F0) ....................................................... 418 10.8.1 Power Management PCI Configuration Registers (PM--D31:F0) ................... 418 10.8.1.1 GEN_PMCON_1--General PM Configuration 1 Register (PM--D31:F0) ........................................................................ 419 10.8.1.2 GEN_PMCON_2--General PM Configuration 2 Register (PM--D31:F0) ........................................................................ 420 10.8.1.3 GEN_PMCON_3--General PM Configuration 3 Register (PM--D31:F0) ........................................................................ 422 10.8.1.4 Cx-STATE_CNF--Cx State Configuration Register (PM--D31:F0) (Mobile/Ultra Mobile Only) ................................... 424 10.8.1.5 C4-TIMING_CNT--C4 Timing Control Register (PM--D31:F0) (Mobile/Ultra Mobile Only) ................................... 425 10.8.1.6 BM_BREAK_EN Register (PM--D31:F0) (Mobile/Ultra Mobile Only) . 426 10.8.1.7 MSC_FUN--Miscellaneous Functionality Register (PM--D31:F0)...... 427 10.8.1.8 EL_STS--Intel(R) Quick Resume Technology Status Register (PM--D31:F0) (ICH7DH Only)................................................... 427 10.8.1.9 EL_CNT1--Intel(R) Quick Resume Technology Control 1 Register (PM--D31:F0) (ICH7DH Only)................................................... 428 10.8.1.10EL_CNT2--Intel(R) Quick Resume Technology Control 2 Register (PM--D31:F0) (ICH7DH Only)................................................... 429 10.8.1.11GPIO_ROUT--GPIO Routing Control Register (PM--D31:F0) .......... 429 10.8.2 APM I/O Decode................................................................................... 430 10.8.2.1 APM_CNT--Advanced Power Management Control Port Register ..... 430 10.8.2.2 APM_STS--Advanced Power Management Status Port Register ...... 430 10.8.3 Power Management I/O Registers ........................................................... 431 10.8.3.1 PM1_STS--Power Management 1 Status Register ........................ 432 10.8.3.2 PM1_EN--Power Management 1 Enable Register.......................... 435 10.8.3.3 PM1_CNT--Power Management 1 Control ................................... 436 10.8.3.4 PM1_TMR--Power Management 1 Timer Register ......................... 437 10.8.3.5 PROC_CNT--Processor Control Register...................................... 437 10.8.3.6 LV2 -- Level 2 Register (Mobile/Ultra Mobile Only) ....................... 439 10.8.3.7 LV3--Level 3 Register (Mobile/Ultra Mobile Only)......................... 439 10.8.3.8 LV4--Level 4 Register (Mobile/Ultra Mobile Only)......................... 439 10.8.3.9 PM2_CNT--Power Management 2 Control Register (Mobile/Ultra Mobile Only)........................................................ 440 10.8.3.10GPE0_STS--General Purpose Event 0 Status Register .................. 440 10.8.3.11GPE0_EN--General Purpose Event 0 Enables Register .................. 444 10.8.3.12SMI_EN--SMI Control and Enable Register ................................. 447 10.8.3.13SMI_STS--SMI Status Register ................................................. 449 10.8.3.14ALT_GP_SMI_EN--Alternate GPI SMI Enable Register ................... 452 10.8.3.15ALT_GP_SMI_STS--Alternate GPI SMI Status Register.................. 452 10.8.3.16GPE_CNTL-- General Purpose Control Register ............................ 453 10.8.3.17DEVACT_STS -- Device Activity Status Register .......................... 454 10.8.3.18SS_CNT-- Intel SpeedStep(R) Technology Control Register (Mobile/Ultra Mobile Only) ................................ 455 10.8.3.19C3_RES-- C3 Residency Register (Mobile/Ultra Mobile Only) ......... 455 System Management TCO Registers (D31:F0) ..................................................... 456 10.9.1 TCO_RLD--TCO Timer Reload and Current Value Register........................... 456 10.9.2 TCO_DAT_IN--TCO Data In Register........................................................ 457 10.9.3 TCO_DAT_OUT--TCO Data Out Register ................................................... 457 Intel (R) ICH7 Family Datasheet 15 10.9.4 TCO1_STS--TCO1 Status Register ........................................................... 457 10.9.5 TCO2_STS--TCO2 Status Register ........................................................... 459 10.9.6 TCO1_CNT--TCO1 Control Register .......................................................... 460 10.9.7 TCO2_CNT--TCO2 Control Register .......................................................... 461 10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers........................................ 461 10.9.9 TCO_WDCNT--TCO Watchdog Control Register .......................................... 462 10.9.10SW_IRQ_GEN--Software IRQ Generation Register ..................................... 462 10.9.11TCO_TMR--TCO Timer Initial Value Register.............................................. 462 10.10 General Purpose I/O Registers (D31:F0) ............................................................. 463 10.10.1GPIO_USE_SEL--GPIO Use Select Register ............................................... 464 10.10.2GP_IO_SEL--GPIO Input/Output Select Register........................................ 464 10.10.3GP_LVL--GPIO Level for Input or Output Register ...................................... 465 10.10.4GPO_BLINK--GPO Blink Enable Register ................................................... 465 10.10.5GPI_INV--GPIO Signal Invert Register ..................................................... 466 10.10.6GPIO_USE_SEL2--GPIO Use Select 2 Register[63:32]................................ 466 10.10.7GP_IO_SEL2--GPIO Input/Output Select 2 Register[63:32] ........................ 467 10.10.8GP_LVL2--GPIO Level for Input or Output 2 Register[63:32]....................... 467 11 UHCI Controllers Registers .................................................................................... 469 11.1 PCI Configuration Registers (USB--D29:F0/F1/F2/F3) ........................................... 469 11.1.1 VID--Vendor Identification Register (USB--D29:F0/F1/F2/F3) ..................... 470 11.1.2 DID--Device Identification Register (USB--D29:F0/F1/F2/F3) ..................... 470 11.1.3 PCICMD--PCI Command Register (USB--D29:F0/F1/F2/F3) ........................ 470 11.1.4 PCISTS--PCI Status Register (USB--D29:F0/F1/F2/F3) .............................. 471 11.1.5 RID--Revision Identification Register (USB--D29:F0/F1/F2/F3) ................... 471 11.1.6 PI--Programming Interface Register (USB--D29:F0/F1/F2/F3) .................... 472 11.1.7 SCC--Sub Class Code Register (USB--D29:F0/F1/F2/F3) ............................ 472 11.1.8 BCC--Base Class Code Register (USB--D29:F0/F1/F2/F3)........................... 472 11.1.9 MLT--Master Latency Timer Register (USB--D29:F0/F1/F2/F3) .................... 473 11.1.10HEADTYP--Header Type Register (USB--D29:F0/F1/F2/F3) ......................... 473 11.1.11BASE--Base Address Register (USB--D29:F0/F1/F2/F3) ............................. 474 11.1.12SVID -- Subsystem Vendor Identification Register (USB--D29:F0/F1/F2/F3) . 474 11.1.13SID -- Subsystem Identification Register (USB--D29:F0/F1/F2/F3) ............. 474 11.1.14INT_LN--Interrupt Line Register (USB--D29:F0/F1/F2/F3).......................... 475 11.1.15INT_PN--Interrupt Pin Register (USB--D29:F0/F1/F2/F3) ........................... 475 11.1.16USB_RELNUM--Serial Bus Release Number Register (USB--D29:F0/F1/F2/F3) ....................................................................... 475 11.1.17USB_LEGKEY--USB Legacy Keyboard/Mouse Control Register (USB--D29:F0/F1/F2/F3)........................................................... 476 11.1.18USB_RES--USB Resume Enable Register (USB--D29:F0/F1/F2/F3) .............. 478 11.1.19CWP--Core Well Policy Register (USB--D29:F0/F1/F2/F3)........................... 478 11.2 USB I/O Registers ............................................................................................ 479 11.2.1 USBCMD--USB Command Register .......................................................... 480 11.2.2 USBSTS--USB Status Register ................................................................ 483 11.2.3 USBINTR--USB Interrupt Enable Register ................................................. 484 11.2.4 FRNUM--Frame Number Register ............................................................ 484 11.2.5 FRBASEADD--Frame List Base Address Register ........................................ 485 11.2.6 SOFMOD--Start of Frame Modify Register ................................................ 486 11.2.7 PORTSC[0,1]--Port Status and Control Register ........................................ 487 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) ............................. 489 12.1 PCI Configuration Registers (SATA-D31:F2)......................................................... 489 12.1.1 VID--Vendor Identification Register (SATA--D31:F2).................................. 491 12.1.2 DID--Device Identification Register (SATA--D31:F2).................................. 491 12.1.3 PCICMD--PCI Command Register (SATA-D31:F2)...................................... 491 12.1.4 PCISTS -- PCI Status Register (SATA-D31:F2) .......................................... 492 12 16 Intel (R) ICH7 Family Datasheet 12.1.5 RID--Revision Identification Register (SATA--D31:F2) ............................... 493 12.1.6 PI--Programming Interface Register (SATA-D31:F2) ................................. 493 12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........... 493 12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........... 494 12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h........... 494 12.1.7 SCC--Sub Class Code Register (SATA-D31:F2) ......................................... 495 12.1.8 BCC--Base Class Code Register (SATA-D31:F2SATA-D31:F2) ..................... 495 12.1.9 PMLT--Primary Master Latency Timer Register (SATA-D31:F2).................... 495 12.1.10PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F2)........................................................................ 496 12.1.11PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F2) .................................................................................... 496 12.1.12SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) .......................................................................... 496 12.1.13SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) .......................................................................... 497 12.1.14BAR -- Legacy Bus Master Base Address Register (SATA-D31:F2) ............... 497 12.1.15ABAR -- AHCI Base Address Register (SATA-D31:F2) ................................ 497 12.1.15.1Non AHCI Capable (Intel(R) ICH7 Feature Supported Components Only) .................................................................. 497 12.1.15.2AHCI Capable (Intel(R) ICH7R, ICH7DH, and Mobile Only) .............. 498 12.1.16SVID--Subsystem Vendor Identification Register (SATA-D31:F2) ................ 498 12.1.17SID--Subsystem Identification Register (SATA-D31:F2)............................. 498 12.1.18CAP--Capabilities Pointer Register (SATA-D31:F2) .................................... 499 12.1.19INT_LN--Interrupt Line Register (SATA-D31:F2)....................................... 499 12.1.20INT_PN--Interrupt Pin Register (SATA-D31:F2) ........................................ 499 12.1.21IDE_TIMP -- Primary IDE Timing Register (SATA-D31:F2).......................... 499 12.1.22IDE_TIMS -- Slave IDE Timing Register (SATA-D31:F2)............................. 501 12.1.23SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F2)................. 502 12.1.24SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F2).................. 503 12.1.25IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F2) .................... 504 12.1.26PID--PCI Power Management Capability Identification Register (SATA-D31:F2)........................................................................ 506 12.1.27PC--PCI Power Management Capabilities Register (SATA-D31:F2) ............... 506 12.1.28PMCS--PCI Power Management Control and Status Register (SATA-D31:F2)........................................................................ 507 12.1.29MSICI--Message Signaled Interrupt Capability Identification (SATA-D31:F2) 507 12.1.30MSIMC--Message Signaled Interrupt Message Control (SATA-D31:F2) ......... 507 12.1.31MSIMA-- Message Signaled Interrupt Message Address (SATA-D31:F2) ....... 508 12.1.32MSIMD--Message Signaled Interrupt Message Data (SATA-D31:F2) ............ 509 12.1.33MAP--Address Map Register (SATA-D31:F2)............................................. 509 12.1.34PCS--Port Control and Status Register (SATA-D31:F2) .............................. 510 12.1.35SIR--SATA Initialization Register............................................................. 511 12.1.36SIRI--SATA Indexed Registers Index ....................................................... 512 12.1.37STRD--SATA Indexed Register Data ........................................................ 512 12.1.37.1STTT1--SATA Indexed Registers Index 00h (SATA TX Termination Test Register 1) ....................................... 513 12.1.37.2STME--SATA Indexed Registers Index C1h (SATA Test Mode Enable Register) ............................................. 513 12.1.37.3STTT2 -- SATA Indexed Registers Index 74h (SATA TX Termination Test Register 2) ....................................... 514 12.1.38SCAP0--SATA Capability Register 0 (SATA-D31:F2)................................... 514 12.1.39SCAP1--SATA Capability Register 1 (SATA-D31:F2)................................... 515 12.1.40ATC--APM Trapping Control Register (SATA-D31:F2) ................................. 516 12.1.41ATS--APM Trapping Status Register (SATA-D31:F2) .................................. 516 12.1.42SP -- Scratch Pad Register (SATA-D31:F2) .............................................. 516 Intel (R) ICH7 Family Datasheet 17 12.2 12.3 12.1.43BFCS--BIST FIS Control/Status Register (SATA-D31:F2) ............................ 517 12.1.44BFTD1--BIST FIS Transmit Data1 Register (SATA-D31:F2) ......................... 518 12.1.45BFTD2--BIST FIS Transmit Data2 Register (SATA-D31:F2) ......................... 519 Bus Master IDE I/O Registers (D31:F2)............................................................... 519 12.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F2) ........................... 520 12.2.2 BMIS[P,S]--Bus Master IDE Status Register (D31:F2) ................................ 521 12.2.3 BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F2) ........ 522 12.2.4 AIR--AHCI Index Register (D31:F2)......................................................... 522 12.2.5 AIDR--AHCI Index Data Register (D31:F2) ............................................... 522 AHCI Registers (D31:F2) (Intel(R) ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) .... 523 12.3.1 AHCI Generic Host Control Registers (D31:F2).......................................... 524 12.3.1.1 CAP--Host Capabilities Register (D31:F2) ................................... 524 12.3.1.2 GHC--Global ICH7 Control Register (D31:F2) .............................. 526 12.3.1.3 IS--Interrupt Status Register (D31:F2) ...................................... 527 12.3.1.4 PI--Ports Implemented Register (D31:F2)................................... 528 12.3.1.5 VS--AHCI Version (D31:F2) ...................................................... 528 12.3.2 Port Registers (D31:F2) ......................................................................... 529 12.3.2.1 PxCLB--Port [3:0] Command List Base Address Register (D31:F2) . 531 12.3.2.2 PxCLBU--Port [3:0] Command List Base Address Upper 32-Bits Register (D31:F2)......................................................... 531 12.3.2.3 PxFB--Port [3:0] FIS Base Address Register (D31:F2) .................. 531 12.3.2.4 PxFBU--Port [3:0] FIS Base Address Upper 32-Bits Register (D31:F2) ................................................................... 532 12.3.2.5 PxIS--Port [3:0] Interrupt Status Register (D31:F2) .................... 532 12.3.2.6 PxIE--Port [3:0] Interrupt Enable Register (D31:F2) .................... 533 12.3.2.7 PxCMD--Port [3:0] Command Register (D31:F2) ......................... 535 12.3.2.8 PxTFD--Port [3:0] Task File Data Register (D31:F2) ..................... 538 12.3.2.9 PxSIG--Port [3:0] Signature Register (D31:F2) ........................... 538 12.3.2.10PxSSTS--Port [3:0] Serial ATA Status Register (D31:F2)............... 539 12.3.2.11PxSCTL -- Port [3:0] Serial ATA Control Register (D31:F2) ............ 540 12.3.2.12PxSERR--Port [3:0] Serial ATA Error Register (D31:F2)................. 541 12.3.2.13PxSACT--Port [3:0] Serial ATA Active (D31:F2) ........................... 542 12.3.2.14PxCI--Port [3:0] Command Issue Register (D31:F2) .................... 543 13 EHCI Controller Registers (D29:F7) ....................................................................... 545 13.1 USB EHCI Configuration Registers (USB EHCI--D29:F7)........................................................................................ 545 13.1.1 VID--Vendor Identification Register (USB EHCI--D29:F7) ........................... 546 13.1.2 DID--Device Identification Register (USB EHCI--D29:F7) ........................... 546 13.1.3 PCICMD--PCI Command Register (USB EHCI--D29:F7) .............................. 547 13.1.4 PCISTS--PCI Status Register (USB EHCI--D29:F7) .................................... 548 13.1.5 RID--Revision Identification Register (USB EHCI--D29:F7) ......................... 549 13.1.6 PI--Programming Interface Register (USB EHCI--D29:F7) .......................... 549 13.1.7 SCC--Sub Class Code Register (USB EHCI--D29:F7) .................................. 549 13.1.8 BCC--Base Class Code Register (USB EHCI--D29:F7) ................................ 549 13.1.9 PMLT--Primary Master Latency Timer Register (USB EHCI--D29:F7)............. 550 13.1.10MEM_BASE--Memory Base Address Register (USB EHCI--D29:F7)............... 550 13.1.11SVID--USB EHCI Subsystem Vendor ID Register (USB EHCI--D29:F7) ......... 550 13.1.12SID--USB EHCI Subsystem ID Register (USB EHCI--D29:F7)...................... 551 13.1.13CAP_PTR--Capabilities Pointer Register (USB EHCI--D29:F7) ...................... 551 13.1.14INT_LN--Interrupt Line Register (USB EHCI--D29:F7) ............................... 551 13.1.15INT_PN--Interrupt Pin Register (USB EHCI--D29:F7) ................................. 551 13.1.16PWR_CAPID--PCI Power Management Capability ID Register (USB EHCI--D29:F7)................................................................. 552 13.1.17NXT_PTR1--Next Item Pointer #1 Register (USB EHCI--D29:F7) ................. 552 13.1.18PWR_CAP--Power Management Capabilities Register (USB EHCI--D29:F7)............................................................................. 552 18 Intel (R) ICH7 Family Datasheet 13.2 13.1.19PWR_CNTL_STS--Power Management Control/ Status Register (USB EHCI--D29:F7) ...................................................... 553 13.1.20DEBUG_CAPID--Debug Port Capability ID Register (USB EHCI--D29:F7) ...... 554 13.1.21NXT_PTR2--Next Item Pointer #2 Register (USB EHCI--D29:F7) ................ 554 13.1.22DEBUG_BASE--Debug Port Base Offset Register (USB EHCI--D29:F7) ......... 554 13.1.23USB_RELNUM--USB Release Number Register (USB EHCI--D29:F7) ............ 555 13.1.24FL_ADJ--Frame Length Adjustment Register (USB EHCI--D29:F7) .............. 555 13.1.25PWAKE_CAP--Port Wake Capability Register (USB EHCI--D29:F7) ............... 556 13.1.26LEG_EXT_CAP--USB EHCI Legacy Support Extended Capability Register (USB EHCI--D29:F7).................................................. 556 13.1.27LEG_EXT_CS--USB EHCI Legacy Support Extended Control / Status Register (USB EHCI--D29:F7) ......................................... 557 13.1.28SPECIAL_SMI--Intel Specific USB 2.0 SMI Register (USB EHCI--D29:F7) ..... 559 13.1.29ACCESS_CNTL--Access Control Register (USB EHCI--D29:F7) .................... 560 Memory-Mapped I/O Registers .......................................................................... 561 13.2.1 Host Controller Capability Registers ........................................................ 561 13.2.1.1 CAPLENGTH--Capability Registers Length Register....................... 561 13.2.1.2 HCIVERSION--Host Controller Interface Version Number Register................................................................................. 562 13.2.1.3 HCSPARAMS--Host Controller Structural Parameters .................... 562 13.2.1.4 HCCPARAMS--Host Controller Capability Parameters Register........ 563 13.2.2 Host Controller Operational Registers ...................................................... 564 13.2.2.1 USB2.0_CMD--USB 2.0 Command Register ................................ 565 13.2.2.2 USB2.0_STS--USB 2.0 Status Register ...................................... 568 13.2.2.3 USB2.0_INTR--USB 2.0 Interrupt Enable Register ....................... 570 13.2.2.4 FRINDEX--Frame Index Register ............................................... 571 13.2.2.5 CTRLDSSEGMENT--Control Data Structure Segment Register ........ 572 13.2.2.6 PERIODICLISTBASE--Periodic Frame List Base Address Register .... 572 13.2.2.7 ASYNCLISTADDR--Current Asynchronous List Address Register ..... 573 13.2.2.8 CONFIGFLAG--Configure Flag Register ....................................... 573 13.2.2.9 PORTSC--Port N Status and Control Register .............................. 573 13.2.3 USB 2.0-Based Debug Port Register ........................................................ 577 13.2.3.1 CNTL_STS--Control/Status Register .......................................... 577 13.2.3.2 USBPID--USB PIDs Register ..................................................... 580 13.2.3.3 DATABUF[7:0]--Data Buffer Bytes[7:0] Register ......................... 581 13.2.3.4 CONFIG--Configuration Register ............................................... 581 14 SMBus Controller Registers (D31:F3) .................................................................... 583 14.1 PCI Configuration Registers (SMBUS--D31:F3) .................................................... 583 14.1.1 VID--Vendor Identification Register (SMBUS--D31:F3) .............................. 583 14.1.2 DID--Device Identification Register (SMBUS--D31:F3) .............................. 584 14.1.3 PCICMD--PCI Command Register (SMBUS--D31:F3) ................................. 584 14.1.4 PCISTS--PCI Status Register (SMBUS--D31:F3) ....................................... 585 14.1.5 RID--Revision Identification Register (SMBUS--D31:F3) ............................ 585 14.1.6 PI--Programming Interface Register (SMBUS--D31:F3) ............................. 586 14.1.7 SCC--Sub Class Code Register (SMBUS--D31:F3) ..................................... 586 14.1.8 BCC--Base Class Code Register (SMBUS--D31:F3).................................... 586 14.1.9 SMB_BASE--SMBUS Base Address Register (SMBUS--D31:F3) ................... 586 14.1.10SVID -- Subsystem Vendor Identification Register (SMBUS--D31:F2/F4) ..... 587 14.1.11SID -- Subsystem Identification Register (SMBUS--D31:F2/F4) .................. 587 14.1.12INT_LN--Interrupt Line Register (SMBUS--D31:F3)................................... 587 14.1.13INT_PN--Interrupt Pin Register (SMBUS--D31:F3) .................................... 587 14.1.14HOSTC--Host Configuration Register (SMBUS--D31:F3)............................. 588 14.2 SMBus I/O Registers ........................................................................................ 588 14.2.1 HST_STS--Host Status Register (SMBUS--D31:F3) ................................... 589 14.2.2 HST_CNT--Host Control Register (SMBUS--D31:F3) .................................. 591 14.2.3 HST_CMD--Host Command Register (SMBUS--D31:F3) ............................. 593 Intel (R) ICH7 Family Datasheet 19 14.2.4 XMIT_SLVA--Transmit Slave Address Register (SMBUS--D31:F3)................. 593 14.2.5 HST_D0--Host Data 0 Register (SMBUS--D31:F3)..................................... 593 14.2.6 HST_D1--Host Data 1 Register (SMBUS--D31:F3)..................................... 593 14.2.7 Host_BLOCK_DB--Host Block Data Byte Register (SMBUS--D31:F3) ............ 594 14.2.8 PEC--Packet Error Check (PEC) Register (SMBUS--D31:F3) ........................ 594 14.2.9 RCV_SLVA--Receive Slave Address Register (SMBUS--D31:F3) ................... 595 14.2.10SLV_DATA--Receive Slave Data Register (SMBUS--D31:F3) ........................ 595 14.2.11AUX_STS--Auxiliary Status Register (SMBUS--D31:F3).............................. 595 14.2.12AUX_CTL--Auxiliary Control Register (SMBUS--D31:F3) ............................. 596 14.2.13SMLINK_PIN_CTL--SMLink Pin Control Register (SMBUS--D31:F3) .............. 596 14.2.14SMBUS_PIN_CTL--SMBUS Pin Control Register (SMBUS--D31:F3) ............... 597 14.2.15SLV_STS--Slave Status Register (SMBUS--D31:F3)................................... 597 14.2.16SLV_CMD--Slave Command Register (SMBUS--D31:F3)............................. 598 14.2.17NOTIFY_DADDR--Notify Device Address Register (SMBUS--D31:F3) ............ 598 14.2.18NOTIFY_DLOW--Notify Data Low Byte Register (SMBUS--D31:F3)............... 599 14.2.19NOTIFY_DHIGH--Notify Data High Byte Register (SMBUS--D31:F3) ............. 599 15 IDE Controller Registers (D31:F1).......................................................................... 601 15.1 PCI Configuration Registers (IDE--D31:F1) ......................................................... 601 15.1.1 VID--Vendor Identification Register (IDE--D31:F1).................................... 602 15.1.2 DID--Device Identification Register (IDE--D31:F1).................................... 602 15.1.3 PCICMD--PCI Command Register (IDE--D31:F1)....................................... 602 15.1.4 PCISTS -- PCI Status Register (IDE--D31:F1)........................................... 603 15.1.5 RID--Revision Identification Register (IDE--D31:F1).................................. 603 15.1.6 PI--Programming Interface Register (IDE--D31:F1)................................... 604 15.1.7 SCC--Sub Class Code Register (IDE--D31:F1) .......................................... 604 15.1.8 BCC--Base Class Code Register (IDE--D31:F1) ......................................... 604 15.1.9 CLS--Cache Line Size Register (IDE--D31:F1) .......................................... 604 15.1.10PMLT--Primary Master Latency Timer Register (IDE--D31:F1) ..................... 605 15.1.11PCMD_BAR--Primary Command Block Base Address Register (IDE--D31:F1) ......................................................................... 605 15.1.12PCNL_BAR--Primary Control Block Base Address Register (IDE--D31:F1) ..... 605 15.1.13SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) ........................................................................... 606 15.1.14SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) ........................................................................... 606 15.1.15BM_BASE -- Bus Master Base Address Register (IDE--D31:F1) ................... 607 15.1.16IDE_SVID -- Subsystem Vendor Identification (IDE--D31:F1) ..................... 607 15.1.17IDE_SID -- Subsystem Identification Register (IDE--D31:F1) ..................... 607 15.1.18INTR_LN--Interrupt Line Register (IDE--D31:F1) ...................................... 608 15.1.19INTR_PN--Interrupt Pin Register (IDE--D31:F1)........................................ 608 15.1.20IDE_TIMP -- IDE Primary Timing Register (IDE--D31:F1) ........................... 608 15.1.21IDE_TIMS -- IDE Secondary Timing Register (IDE--D31:F1) ....................... 610 15.1.22SLV_IDETIM--Slave (Drive 1) IDE Timing Register (IDE--D31:F1) (Desktop and Mobile Only) ............................................... 610 15.1.23SDMA_CNT--Synchronous DMA Control Register (IDE--D31:F1) .................. 611 15.1.24SDMA_TIM--Synchronous DMA Timing Register (IDE--D31:F1) ................... 611 15.1.25IDE_CONFIG--IDE I/O Configuration Register (IDE--D31:F1)...................... 612 15.1.26ATC--APM Trapping Control Register (IDE--D31:F1)................................... 614 15.1.27ATS--APM Trapping Status Register (IDE--D31:F1).................................... 614 15.2 Bus Master IDE I/O Registers (IDE--D31:F1) ....................................................... 615 15.2.1 BMICP--Bus Master IDE Command Register (IDE--D31:F1) ........................ 615 15.2.2 BMISP--Bus Master IDE Status Register (IDE--D31:F1) ............................. 616 15.2.3 BMIDP--Bus Master IDE Descriptor Table Pointer Register (IDE--D31:F1) ..... 617 20 Intel (R) ICH7 Family Datasheet 16 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) ................. 619 16.1 AC '97 Audio PCI Configuration Space (Audio--D30:F2) ........................................ 619 16.1.1 VID--Vendor Identification Register (Audio--D30:F2) ................................ 620 16.1.2 DID--Device Identification Register (Audio--D30:F2)................................. 620 16.1.3 PCICMD--PCI Command Register (Audio--D30:F2) ................................... 621 16.1.4 PCISTS--PCI Status Register (Audio--D30:F2) ......................................... 622 16.1.5 RID--Revision Identification Register (Audio--D30:F2) .............................. 622 16.1.6 PI--Programming Interface Register (Audio--D30:F2) ............................... 623 16.1.7 SCC--Sub Class Code Register (Audio--D30:F2) ....................................... 623 16.1.8 BCC--Base Class Code Register (Audio--D30:F2) ...................................... 623 16.1.9 HEADTYP--Header Type Register (Audio--D30:F2) .................................... 623 16.1.10NAMBAR--Native Audio Mixer Base Address Register (Audio--D30:F2) ......... 624 16.1.11NABMBAR--Native Audio Bus Mastering Base Address Register (Audio--D30:F2) ...................................................................... 625 16.1.12MMBAR--Mixer Base Address Register (Audio--D30:F2) ............................. 625 16.1.13MBBAR--Bus Master Base Address Register (Audio--D30:F2)...................... 626 16.1.14SVID--Subsystem Vendor Identification Register (Audio--D30:F2) .............. 626 16.1.15SID--Subsystem Identification Register (Audio--D30:F2)........................... 627 16.1.16CAP_PTR--Capabilities Pointer Register (Audio--D30:F2) ........................... 627 16.1.17INT_LN--Interrupt Line Register (Audio--D30:F2) ..................................... 627 16.1.18INT_PN--Interrupt Pin Register (Audio--D30:F2) ...................................... 628 16.1.19PCID--Programmable Codec Identification Register (Audio--D30:F2) ........... 628 16.1.20CFG--Configuration Register (Audio--D30:F2) .......................................... 628 16.1.21PID--PCI Power Management Capability Identification Register (Audio--D30:F2) ...................................................................... 629 16.1.22PC--Power Management Capabilities Register (Audio--D30:F2) ................... 629 16.1.23PCS--Power Management Control and Status Register (Audio--D30:F2)....... 630 16.2 AC '97 Audio I/O Space (D30:F2) ...................................................................... 631 16.2.1 x_BDBAR--Buffer Descriptor Base Address Register (Audio--D30:F2) .......... 635 16.2.2 x_CIV--Current Index Value Register (Audio--D30:F2) .............................. 635 16.2.3 x_LVI--Last Valid Index Register (Audio--D30:F2) .................................... 636 16.2.4 x_SR--Status Register (Audio--D30:F2) .................................................. 636 16.2.5 x_PICB--Position In Current Buffer Register (Audio--D30:F2) ..................... 638 16.2.6 x_PIV--Prefetched Index Value Register (Audio--D30:F2) .......................... 638 16.2.7 x_CR--Control Register (Audio--D30:F2) ................................................. 639 16.2.8 GLOB_CNT--Global Control Register (Audio--D30:F2)................................ 640 16.2.9 GLOB_STA--Global Status Register (Audio--D30:F2) ................................. 642 16.2.10CAS--Codec Access Semaphore Register (Audio--D30:F2) ......................... 644 16.2.11SDM--SDATA_IN Map Register (Audio--D30:F2) ....................................... 645 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)............... 647 17.1 AC '97 Modem PCI Configuration Space (D30:F3) ................................................ 647 17.1.1 VID--Vendor Identification Register (Modem--D30:F3) .............................. 648 17.1.2 DID--Device Identification Register (Modem--D30:F3) .............................. 648 17.1.3 PCICMD--PCI Command Register (Modem--D30:F3) ................................. 648 17.1.4 PCISTS--PCI Status Register (Modem--D30:F3) ....................................... 649 17.1.5 RID--Revision Identification Register (Modem--D30:F3) ............................ 650 17.1.6 PI--Programming Interface Register (Modem--D30:F3) ............................. 650 17.1.7 SCC--Sub Class Code Register (Modem--D30:F3) ..................................... 650 17.1.8 BCC--Base Class Code Register (Modem--D30:F3).................................... 650 17.1.9 HEADTYP--Header Type Register (Modem--D30:F3) .................................. 650 17.1.10MMBAR--Modem Mixer Base Address Register (Modem--D30:F3) ................ 651 17.1.11MBAR--Modem Base Address Register (Modem--D30:F3)........................... 651 17.1.12SVID--Subsystem Vendor Identification Register (Modem--D30:F3) ............ 652 17.1.13SID--Subsystem Identification Register (Modem--D30:F3) ........................ 652 17 Intel (R) ICH7 Family Datasheet 21 17.2 17.1.14CAP_PTR--Capabilities Pointer Register (Modem--D30:F3).......................... 652 17.1.15INT_LN--Interrupt Line Register (Modem--D30:F3) ................................... 653 17.1.16INT_PIN--Interrupt Pin Register (Modem--D30:F3) ................................... 653 17.1.17PID--PCI Power Management Capability Identification Register (Modem--D30:F3) .................................................................... 653 17.1.18PC--Power Management Capabilities Register (Modem--D30:F3) ................. 654 17.1.19PCS--Power Management Control and Status Register (Modem--D30:F3) ..... 654 AC '97 Modem I/O Space (D30:F3) .................................................................... 655 17.2.1 x_BDBAR--Buffer Descriptor List Base Address Register (Modem--D30:F3)... 657 17.2.2 x_CIV--Current Index Value Register (Modem--D30:F3) ............................ 657 17.2.3 x_LVI--Last Valid Index Register (Modem--D30:F3)................................... 657 17.2.4 x_SR--Status Register (Modem--D30:F3)................................................. 658 17.2.5 x_PICB--Position in Current Buffer Register (Modem--D30:F3) ................... 659 17.2.6 x_PIV--Prefetch Index Value Register (Modem--D30:F3)............................ 659 17.2.7 x_CR--Control Register (Modem--D30:F3) ............................................... 660 17.2.8 GLOB_CNT--Global Control Register (Modem--D30:F3) .............................. 661 17.2.9 GLOB_STA--Global Status Register (Modem--D30:F3) ............................... 662 17.2.10CAS--Codec Access Semaphore Register (Modem--D30:F3) ....................... 664 18 PCI Express* Configuration Registers (Desktop and Mobile Only) .......................... 665 18.1 PCI Express* Configuration Registers (PCI Express--D28:F0/F1/F2/F3/F4/F5) .............................................................. 665 18.1.1 VID--Vendor Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 667 18.1.2 DID--Device Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 667 18.1.3 PCICMD--PCI Command Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 667 18.1.4 PCISTS--PCI Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 668 18.1.5 RID--Revision Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 669 18.1.6 PI--Programming Interface Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 669 18.1.7 SCC--Sub Class Code Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 669 18.1.8 BCC--Base Class Code Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 670 18.1.9 CLS--Cache Line Size Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 670 18.1.10PLT--Primary Latency Timer Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 670 18.1.11HEADTYP--Header Type Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 670 18.1.12BNUM--Bus Number Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 671 18.1.13IOBL--I/O Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 671 18.1.14SSTS--Secondary Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 672 18.1.15MBL--Memory Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 673 18.1.16PMBL--Prefetchable Memory Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 673 18.1.17PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)....................................... 674 22 Intel (R) ICH7 Family Datasheet 18.1.18PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ...................................... 674 18.1.19CAPP--Capabilities List Pointer Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 674 18.1.20INTR--Interrupt Information Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 675 18.1.21BCTRL--Bridge Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 676 18.1.22CLIST--Capabilities List Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 677 18.1.23XCAP--PCI Express* Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 677 18.1.24DCAP--Device Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 678 18.1.25DCTL--Device Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 679 18.1.26DSTS--Device Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 680 18.1.27LCAP--Link Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 681 18.1.28LCTL--Link Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 682 18.1.29LSTS--Link Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ............ 683 18.1.30SLCAP--Slot Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 684 18.1.31SLCTL--Slot Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) .......... 685 18.1.32SLSTS--Slot Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)........... 686 18.1.33RCTL--Root Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)........... 687 18.1.34RSTS--Root Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ........... 687 18.1.35MID--Message Signaled Interrupt Identifiers Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 688 18.1.36MC--Message Signaled Interrupt Message Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 688 18.1.37MA--Message Signaled Interrupt Message Address Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ...................................... 688 18.1.38MD--Message Signaled Interrupt Message Data Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 689 18.1.39SVCAP--Subsystem Vendor Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 689 18.1.40SVID--Subsystem Vendor Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 689 18.1.41PMCAP--Power Management Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 689 18.1.42PMC--PCI Power Management Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 690 18.1.43PMCS--PCI Power Management Control and Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ...................................... 690 18.1.44MPC--Miscellaneous Port Configuration Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 691 18.1.45SMSCS--SMI/SCI Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ... 693 18.1.46RPDCGEN - Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)................................. 694 18.1.47IPWS--Intel(R) PRO/Wireless 3945ABG Status (PCI Express--D28:F0/F1/F2/F3/F4/F5) (Mobile Only) ............................... 694 18.1.48VCH--Virtual Channel Capability Header Register (PCI Express--D28:F0/F1/F2/F3/F4/F5)................................................... 695 Intel (R) ICH7 Family Datasheet 23 18.1.49VCAP2--Virtual Channel Capability 2 Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 695 18.1.50PVC--Port Virtual Channel Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 695 18.1.51PVS -- Port Virtual Channel Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 696 18.1.52V0CAP -- Virtual Channel 0 Resource Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 696 18.1.53V0CTL -- Virtual Channel 0 Resource Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 697 18.1.54V0STS -- Virtual Channel 0 Resource Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 697 18.1.55UES -- Uncorrectable Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 698 18.1.56UEM -- Uncorrectable Error Mask (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 699 18.1.57UEV -- Uncorrectable Error Severity Q(PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................. 700 18.1.58CES -- Correctable Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 701 18.1.59CEM -- Correctable Error Mask Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 701 18.1.60AECC -- Advanced Error Capabilities and Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 702 18.1.61RES -- Root Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 702 18.1.62RCTCL -- Root Complex Topology Capability List Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 703 18.1.63ESD -- Element Self Description Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 703 18.1.64ULD -- Upstream Link Description Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 704 18.1.65ULBA -- Upstream Link Base Address Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 704 18.1.66PEETM -- PCI Express Extended Test Mode Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) ................................................... 704 19 Intel(R) High Definition Audio Controller Registers (D27:F0).................................... 705 19.1 Intel(R) High Definition Audio PCI Configuration Space (Intel(R) High Definition Audio-- D27:F0) .............................................................................................. 705 19.1.1 VID--Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 707 19.1.2 DID--Device Identification Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 707 19.1.3 PCICMD--PCI Command Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 708 19.1.4 PCISTS--PCI Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 709 19.1.5 RID--Revision Identification Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 709 19.1.6 PI--Programming Interface Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 710 19.1.7 SCC--Sub Class Code Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 710 19.1.8 BCC--Base Class Code Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 710 19.1.9 CLS--Cache Line Size Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 710 24 Intel (R) ICH7 Family Datasheet 19.1.10LT--Latency Timer Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 710 19.1.11HEADTYP--Header Type Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 711 19.1.12HDBARL--Intel(R) High Definition Audio Lower Base Address Register (Intel(R) High Definition Audio--D27:F0) ................................................... 711 19.1.13HDBARU--Intel(R) High Definition Audio Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 711 19.1.14SVID--Subsystem Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 712 19.1.15SID--Subsystem Identification Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 712 19.1.16CAPPTR--Capabilities Pointer Register (Audio--D30:F2) ............................. 713 19.1.17INTLN--Interrupt Line Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 713 19.1.18INTPN--Interrupt Pin Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 713 19.1.19HDCTL--Intel(R) High Definition Audio Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 714 19.1.20TCSEL--Traffic Class Select Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 715 19.1.21DCKCTL--Docking Control Register (Mobile Only) (Intel(R) High Definition Audio Controller--D27:F0)..................................... 715 19.1.22DCKSTS--Docking Status Register (Intel(R) High Definition Audio Controller--D27:F0) (Mobile Only) ................. 716 19.1.23PID--PCI Power Management Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 716 19.1.24PC--Power Management Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 716 19.1.25PCS--Power Management Control and Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 717 19.1.26MID--MSI Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 718 19.1.27MMC--MSI Message Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 718 19.1.28MMLA--MSI Message Lower Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 718 19.1.29MMUA--MSI Message Upper Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 718 19.1.30MMD--MSI Message Data Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 719 19.1.31PXID--PCI Express* Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only)719 19.1.32PXC--PCI Express* Capabilities Register (Desktop and Mobile Only) (Intel(R) High Definition Audio Controller--D27:F0)..................................... 719 19.1.33DEVCAP--Device Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 720 19.1.34DEVC--Device Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 721 19.1.35DEVS--Device Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 721 19.1.36VCCAP--Virtual Channel Enhanced Capability Header (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) .................................................................... 722 19.1.37PVCCAP1--Port VC Capability Register 1 (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) .................................................................... 722 Intel (R) ICH7 Family Datasheet 25 19.2 19.1.38PVCCAP2 -- Port VC Capability Register 2 (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 722 19.1.39PVCCTL -- Port VC Control Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 723 19.1.40PVCSTS--Port VC Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 723 19.1.41VC0CAP--VC0 Resource Capability Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 723 19.1.42VC0CTL--VC0 Resource Control Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 724 19.1.43VC0STS--VC0 Resource Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 724 19.1.44VCiCAP--VCi Resource Capability Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 725 19.1.45VCiCTL--VCi Resource Control Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 725 19.1.46VCiSTS--VCi Resource Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 726 19.1.47RCCAP--Root Complex Link Declaration Enhanced Capability Header Register (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) ........................................ 726 19.1.48ESD--Element Self Description Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 726 19.1.49L1DESC--Link 1 Description Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 727 19.1.50L1ADDL--Link 1 Lower Address Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 727 19.1.51L1ADDU--Link 1 Upper Address Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 727 (R) High Definition Audio Memory-Mapped Configuration Registers Intel (Intel(R) High Definition Audio-- D27:F0).............................................................. 728 19.2.1 GCAP--Global Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 732 19.2.2 VMIN--Minor Version Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 732 19.2.3 VMAJ--Major Version Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 732 19.2.4 OUTPAY--Output Payload Capability Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 733 19.2.5 INPAY--Input Payload Capability Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 733 19.2.6 GCTL--Global Control Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 734 19.2.7 WAKEEN--Wake Enable Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 735 19.2.8 STATESTS--State Change Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 735 19.2.9 GSTS--Global Status Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 736 19.2.10ECAP--Extended Capabilities (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 737 19.2.11OUTSTRMPAY--Output Stream Payload Capability (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 737 19.2.12INSTRMPAY--Input Stream Payload Capability (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 738 19.2.13INTCTL--Interrupt Control Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 739 26 Intel (R) ICH7 Family Datasheet 19.2.14INTSTS--Interrupt Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 740 19.2.15WALCLK--Wall Clock Counter Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 741 19.2.16SSYNC--Stream Synchronization Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 741 19.2.17CORBLBASE--CORB Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 742 19.2.18CORBUBASE--CORB Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 742 19.2.19CORBWP--CORB Write Pointer Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 742 19.2.20CORBRP--CORB Read Pointer Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 743 19.2.21CORBCTL--CORB Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 743 19.2.22CORBST--CORB Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 744 19.2.23CORBSIZE--CORB Size Register Intel(R) High Definition Audio Controller--D27:F0) ...................................... 744 19.2.24RIRBLBASE--RIRB Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 744 19.2.25RIRBUBASE--RIRB Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 745 19.2.26RIRBWP--RIRB Write Pointer Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 745 19.2.27RINTCNT--Response Interrupt Count Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 746 19.2.28RIRBCTL--RIRB Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 746 19.2.29RIRBSTS--RIRB Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 747 19.2.30RIRBSIZE--RIRB Size Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 747 19.2.31IC--Immediate Command Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 747 19.2.32IR--Immediate Response Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 748 19.2.33IRS--Immediate Command Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 748 19.2.34DPLBASE--DMA Position Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 749 19.2.35DPUBASE--DMA Position Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 749 19.2.36SDCTL--Stream Descriptor Control Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 750 19.2.37SDSTS--Stream Descriptor Status Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 752 19.2.38SDLPIB--Stream Descriptor Link Position in Buffer Register (Intel(R) High Definition Audio Controller--D27:F0) ........................ 753 19.2.39SDCBL--Stream Descriptor Cyclic Buffer Length Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 753 19.2.40SDLVI--Stream Descriptor Last Valid Index Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 754 19.2.41SDFIFOW--Stream Descriptor FIFO Watermark Register (Intel(R) High Definition Audio Controller--D27:F0)..................................... 754 Intel (R) ICH7 Family Datasheet 27 19.2.42SDFIFOS--Stream Descriptor FIFO Size Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 755 19.2.43SDFMT--Stream Descriptor Format Register (Intel(R) High Definition Audio Controller--D27:F0) ..................................... 756 19.2.44SDBDPL--Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) ............. 757 19.2.45SDBDPU--Stream Descriptor Buffer Descriptor List PointerUpper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) ............. 757 20 High Precision Event Timer Registers..................................................................... 759 20.1 Memory Mapped Registers ................................................................................ 759 20.1.1 GCAP_ID--General Capabilities and Identification Register.......................... 760 20.1.2 GEN_CONF--General Configuration Register ............................................. 761 20.1.3 GINTR_STA--General Interrupt Status Register ......................................... 761 20.1.4 MAIN_CNT--Main Counter Value Register ................................................. 762 20.1.5 TIMn_CONF--Timer n Configuration and Capabilities Register...................... 762 20.1.6 TIMn_COMP--Timer n Comparator Value Register ...................................... 764 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) ................................. 765 21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ........................ 765 21.1.1 SPIS--SPI Status Register (SPI Memory Mapped Configuration Registers) ............................................................................................ 767 21.1.2 SPIC--SPI Control Register (SPI Memory Mapped Configuration Registers) ............................................................................................ 768 21.1.3 SPIA--SPI Address Register (SPI Memory Mapped Configuration Registers) ............................................................................................ 769 21.1.4 SPID[N] --SPI Data N Register (SPI Memory Mapped Configuration Registers) ............................................................................................ 769 21.1.5 BBAR--BIOS Base Address Register (SPI Memory Mapped Configuration Registers).......................................... 770 21.1.6 PREOP--Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 770 21.1.7 OPTYPE--Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 771 21.1.8 OPMENU--Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers).......................................... 772 21.1.9 PBR[N]--Protected BIOS Range [N] (SPI Memory Mapped Configuration Registers).......................................... 772 Ballout Definition ................................................................................................... 773 22.1 Desktop, Mobile, and Digital Home Component Ballout.......................................... 773 22.2 Ultra Mobile Component Ballout ......................................................................... 782 Electrical Characteristics........................................................................................ 789 23.1 Thermal Specifications...................................................................................... 789 23.2 Absolute Maximum Ratings ............................................................................... 789 23.3 DC Characteristics ........................................................................................... 790 23.4 AC Characteristics............................................................................................ 801 23.5 Timing Diagrams ............................................................................................. 817 Package Information ............................................................................................. 835 24.1 Desktop and Mobile Package Information ............................................................ 835 24.2 Ultra Mobile Package Information ....................................................................... 837 Testability (Desktop and Mobile Only).................................................................... 839 25.1 XOR Chain Tables............................................................................................. 841 21 22 23 24 25 28 Intel (R) ICH7 Family Datasheet Figures 2-1 Interface Signals Block Diagram (Desktop Only)........................................................... 52 2-2 Interface Signals Block Diagram (Mobile Only) ............................................................ 53 2-3 Interface Signals Block Diagram (Ultra Mobile Only) ..................................................... 54 2-4 Example External RTC Circuit..................................................................................... 78 4-1 Desktop Only Conceptual System Clock Diagram .......................................................... 96 4-2 Mobile Only Conceptual Clock Diagram........................................................................ 96 4-3 Ultra Mobile Only Conceptual Clock Diagram ................................................................ 97 5-1 Generation of SERR# to Platform ............................................................................. 105 5-2 64-Word EEPROM Read Instruction Waveform............................................................ 112 5-3 LPC Interface Diagram ............................................................................................ 118 5-4 LPC Bridge SERR# Generation ................................................................................. 123 5-5 Intel(R) ICH7 DMA Controller ..................................................................................... 124 5-6 DMA Request Assertion through LDRQ# .................................................................... 127 5-7 Coprocessor Error Timing Diagram ........................................................................... 151 5-8 Physical Region Descriptor Table Entry...................................................................... 186 5-9 SATA Power States................................................................................................. 195 5-10USB Legacy Keyboard Flow Diagram......................................................................... 205 5-11 Intel(R) ICH7-USB Port Connections .......................................................................... 212 5-12Intel(R) ICH7-Based Audio Codec '97 Specification, Version 2.3...................................... 233 5-13AC '97 2.3 Controller-Codec Connection .................................................................... 235 5-14AC-Link Protocol .................................................................................................... 236 5-15AC-Link Powerdown Timing ..................................................................................... 237 5-16SDIN Wake Signaling.............................................................................................. 238 22-1 Desktop and Mobile Component Ballout (Topview-Left Side) ....................................... 774 22-2Desktop and Mobile Component Ballout (Topview-Right Side) ...................................... 775 22-3Intel(R) ICH7-U Ballout (top view, left side)................................................................. 782 22-4Intel(R) ICH7-U Ballout (top view, right side)............................................................... 783 23-1Clock Timing ......................................................................................................... 817 23-2Valid Delay from Rising Clock Edge........................................................................... 817 23-3Setup and Hold Times............................................................................................. 817 23-4Float Delay ........................................................................................................... 818 23-5Pulse Width ........................................................................................................... 818 23-6Output Enable Delay............................................................................................... 818 23-7IDE PIO Mode........................................................................................................ 819 23-8IDE Multiword DMA ................................................................................................ 819 23-9Ultra ATA Mode (Drive Initiating a Burst Read)........................................................... 820 23-10Ultra ATA Mode (Sustained Burst) .......................................................................... 820 23-11Ultra ATA Mode (Pausing a DMA Burst).................................................................... 821 23-12Ultra ATA Mode (Terminating a DMA Burst).............................................................. 821 23-13USB Rise and Fall Times ........................................................................................ 822 23-14USB Jitter............................................................................................................ 822 23-15USB EOP Width .................................................................................................... 822 23-16SMBus Transaction ............................................................................................... 823 23-17SMBus Timeout.................................................................................................... 823 23-18Power Sequencing and Reset Signal Timings (Desktop Only) ...................................... 824 23-19Power Sequencing and Reset Signal Timings (Mobile/Ultra Mobile Only)....................... 825 23-20G3 (Mechanical Off) to S0 Timings (Desktop Only).................................................... 826 23-21G3 (Mechanical Off) to S0 Timings (Mobile/Ultra Mobile Only) .................................... 827 23-22S0 to S1 to S0 Timing (Desktop Only)..................................................................... 827 23-23S0 to S5 to S0 Timings, S3COLD (Desktop Only)........................................................ 828 23-24S0 to S5 to S0 Timings, S3HOT (Desktop Only) ......................................................... 829 23-25S0 to S5 to S0 Timings, S3COLD (Mobile/Ultra Mobile Only) ........................................ 830 23-26S0 to S5 to S0 Timings, S3HOT (Mobile/Ultra Mobile Only).......................................... 831 Intel (R) ICH7 Family Datasheet 29 23-27C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 831 23-28C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832 23-29C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832 23-30AC '97 Data Input and Output Timings (Desktop and Mobile Only)............................... 833 23-31Intel(R) High Definition Audio Input and Output Timings .............................................. 833 23-32SPI Timings (Desktop and Mobile Only) ................................................................... 834 24-1Intel(R) ICH7 Package (Top View)............................................................................... 835 24-2Intel(R) ICH7 Package (Bottom View).......................................................................... 836 24-3Intel(R) ICH7 Package (Side View).............................................................................. 836 24-4Intel ICH7-U Package Drawing ................................................................................. 837 25-1XOR Chain Test Mode Selection, Entry and Testing...................................................... 839 25-2Example XOR Chain Circuitry ................................................................................... 840 Tables 1-1 Industry Specifications ..............................................................................................39 1-2 PCI Devices and Functions .........................................................................................43 1-3 Intel(R) ICH7 Desktop/Server Family ............................................................................50 1-4 Intel(R) ICH7-M Mobile and ICH7-U Ultra Mobile Components ...........................................50 2-1 Direct Media Interface Signals ....................................................................................55 2-2 PCI Express* Signals ................................................................................................55 2-3 Platform LAN Connect Interface Signals .......................................................................56 2-4 EEPROM Interface Signals..........................................................................................56 2-5 Firmware Hub Interface Signals ..................................................................................56 2-6 PCI Interface Signals ................................................................................................57 2-7 Serial ATA Interface Signals .......................................................................................59 2-8 IDE Interface Signals ................................................................................................60 2-9 LPC Interface Signals ................................................................................................62 2-10Interrupt Signals ......................................................................................................62 2-11USB Interface Signals ...............................................................................................63 2-12Power Management Interface Signals ..........................................................................64 2-13Processor Interface Signals ........................................................................................66 2-14SM Bus Interface Signals ...........................................................................................68 2-15System Management Interface Signals ........................................................................68 2-16Real Time Clock Interface ..........................................................................................69 2-17Other Clocks ............................................................................................................69 2-18Miscellaneous Signals................................................................................................70 2-19AC '97/Intel(R) High Definition Audio Link Signals ...........................................................71 2-20Serial Peripheral Interface (SPI) Signals ......................................................................72 2-21General Purpose I/O Signals ......................................................................................72 2-22Power and Ground Signals .........................................................................................74 2-23Functional Strap Definitions .......................................................................................76 3-1 Integrated Pull-Up and Pull-Down Resistors..................................................................79 3-2 IDE Series Termination Resistors ................................................................................80 3-3 Power Plane and States for Output and I/O Signals for Desktop Only Configurations ..........81 3-4 Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations .........................................................................................................86 3-5 Power Plane for Input Signals for Desktop Only Configurations .......................................90 3-6 Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations ........................92 4-1 Intel(R) ICH7 and System Clock Domains ......................................................................95 5-1 PCI Bridge Initiator Cycle Types .................................................................................99 5-2 Type 1 Address Format ........................................................................................... 102 5-3 MSI vs. PCI IRQ Actions .......................................................................................... 104 5-4 Advanced TCO Functionality ..................................................................................... 114 5-5 LPC Cycle Types Supported...................................................................................... 119 30 Intel (R) ICH7 Family Datasheet 5-6 Start Field Bit Definitions ........................................................................................ 119 5-7 Cycle Type Bit Definitions........................................................................................ 120 5-8 Transfer Size Bit Definition ...................................................................................... 120 5-9 SYNC Bit Definition................................................................................................. 121 5-10DMA Transfer Size.................................................................................................. 126 5-11Address Shifting in 16-Bit I/O DMA Transfers ............................................................. 126 5-12Counter Operating Modes........................................................................................ 131 5-13Interrupt Controller Core Connections ....................................................................... 133 5-14Interrupt Status Registers ....................................................................................... 134 5-15Content of Interrupt Vector Byte .............................................................................. 134 5-16APIC Interrupt Mapping .......................................................................................... 140 5-17Interrupt Message Address Format ........................................................................... 142 5-18Interrupt Message Data Format ............................................................................... 143 5-19Stop Frame Explanation .......................................................................................... 144 5-20Data Frame Format ................................................................................................ 145 5-21Configuration Bits Reset by RTCRST# Assertion ......................................................... 148 5-22INIT# Going Active ................................................................................................ 150 5-23NMI Sources.......................................................................................................... 151 5-24DP Signal Differences ............................................................................................. 152 5-25General Power States for Systems Using Intel(R) ICH7.................................................. 153 5-26State Transition Rules for Intel(R) ICH7 ...................................................................... 155 5-27System Power Plane ............................................................................................... 156 5-28Causes of SMI# and SCI ......................................................................................... 157 5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160 5-30Sleep Types .......................................................................................................... 163 5-31Causes of Wake Events........................................................................................... 164 5-32GPI Wake Events ................................................................................................... 165 5-33Transitions Due to Power Failure .............................................................................. 166 5-34Transitions Due to Power Button .............................................................................. 167 5-35Transitions Due to RI# Signal .................................................................................. 168 5-36Write Only Registers with Read Paths in ALT Access Mode ........................................... 171 5-37PIC Reserved Bits Return Values .............................................................................. 173 5-38Register Write Accesses in ALT Access Mode .............................................................. 173 5-39Intel(R) ICH7 Clock Inputs ........................................................................................ 176 5-40Heartbeat Message Data ......................................................................................... 182 5-41 IDE Transaction Timings (PCI Clocks) ...................................................................... 184 5-42Interrupt/Active Bit Interaction Definition .................................................................. 188 5-43SATA Features Support in Intel(R) ICH7 ...................................................................... 191 5-44SATA Feature Description........................................................................................ 192 5-45Legacy Replacement Routing ................................................................................... 198 5-46Bits Maintained in Low Power States ......................................................................... 204 5-47USB Legacy Keyboard State Transitions .................................................................... 205 5-48UHCI vs. EHCI ....................................................................................................... 207 5-49Debug Port Behavior .............................................................................................. 215 5-50I2C Block Read ...................................................................................................... 223 5-51Enable for SMBALERT# ........................................................................................... 225 5-52Enables for SMBus Slave Write and SMBus Host Events............................................... 225 5-53Enables for the Host Notify Command ....................................................................... 226 5-54Slave Write Registers ............................................................................................. 227 5-55Command Types .................................................................................................... 228 5-56Read Cycle Format ................................................................................................. 229 5-57Data Values for Slave Read Registers........................................................................ 229 5-58Host Notify Format ................................................................................................. 231 5-59Features Supported by Intel(R) ICH7 .......................................................................... 232 5-60Output Tag Slot 0 .................................................................................................. 237 Intel (R) ICH7 Family Datasheet 31 5-61SPI Implementation Options .................................................................................... 245 5-62Required Commands and Opcodes ............................................................................ 247 5-63Intel(R) ICH7 Standard SPI Commands ....................................................................... 247 5-64Flash Protection Mechanism Summary....................................................................... 248 6-1 PCI Devices and Functions ....................................................................................... 254 6-2 Fixed I/O Ranges Decoded by Intel(R) ICH7 ................................................................. 256 6-3 Variable I/O Decode Ranges..................................................................................... 258 6-4 Memory Decode Ranges from Processor Perspective.................................................... 259 7-1 Chipset Configuration Register Memory Map (Memory Space) ....................................... 263 8-1 LAN Controller PCI Register Address Map (LAN Controller--B1:D8:F0) ........................... 303 8-2 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM .......................... 310 8-3 Data Register Structure ........................................................................................... 314 8-4 Intel(R) ICH7 Integrated LAN Controller CSR Space Register Address Map........................ 315 8-5 Self-Test Results Format ......................................................................................... 320 8-6 Statistical Counters................................................................................................. 327 8-7 ASF Register Address Map ....................................................................................... 329 9-1 PCI Bridge Register Address Map (PCI-PCI--D30:F0) ................................................... 345 10-1LPC Interface PCI Register Address Map (LPC I/F--D31:F0) .......................................... 363 10-2DMA Registers ....................................................................................................... 385 10-3PIC Registers (LPC I/F--D31:F0)............................................................................... 396 10-4APIC Direct Registers (LPC I/F--D31:F0) ................................................................... 404 10-5APIC Indirect Registers (LPC I/F--D31:F0) ................................................................. 404 10-6RTC I/O Registers (LPC I/F--D31:F0) ........................................................................ 409 10-7RTC (Standard) RAM Bank (LPC I/F--D31:F0) ............................................................ 410 10-8Processor Interface PCI Register Address Map (LPC I/F--D31:F0).................................. 415 10-9Power Management PCI Register Address Map (PM--D31:F0) ....................................... 418 10-10APM Register Map ................................................................................................. 430 10-11ACPI and Legacy I/O Register Map .......................................................................... 431 10-12TCO I/O Register Address Map ............................................................................... 456 10-13Registers to Control GPIO Address Map.................................................................... 463 11-1UHCI Controller PCI Register Address Map (USB--D29:F0/F1/F2/F3) ............................. 469 11-2USB I/O Registers .................................................................................................. 479 11-3Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation .................. 482 12-1SATA Controller PCI Register Address Map (SATA-D31:F2) .......................................... 489 12-2Bus Master IDE I/O Register Address Map.................................................................. 519 12-3AHCI Register Address Map...................................................................................... 523 12-4Generic Host Controller Register Address Map ............................................................ 524 12-5Port [3:0] DMA Register Address Map ....................................................................... 529 13-1USB EHCI PCI Register Address Map (USB EHCI--D29:F7) ........................................... 545 13-2Enhanced Host Controller Capability Registers ............................................................ 561 13-3Enhanced Host Controller Operational Register Address Map ........................................ 564 13-4Debug Port Register Address Map ............................................................................. 577 14-1SMBus Controller PCI Register Address Map (SMBUS--D31:F3)..................................... 583 14-2SMBus I/O Register Address Map.............................................................................. 588 15-1IDE Controller PCI Register Address Map (IDE-D31:F1) ............................................... 601 15-2Bus Master IDE I/O Registers ................................................................................... 615 16-1AC `97 Audio PCI Register Address Map (Audio--D30:F2) ............................................. 619 16-2Intel(R) ICH7 Audio Mixer Register Configuration .......................................................... 631 16-3Native Audio Bus Master Control Registers ................................................................. 633 17-1AC `97 Modem PCI Register Address Map (Modem--D30:F3) ........................................ 647 17-2Intel(R) ICH7 Modem Mixer Register Configuration........................................................ 655 17-3Modem Registers.................................................................................................... 656 18-1PCI Express* Configuration Registers Address Map (PCI Express--D28:F0/F1/F2/F3/F4/F5)..................................................................... 665 32 Intel (R) ICH7 Family Datasheet 19-1Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0)....................................................................... 705 19-2Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0)....................................................................... 728 20-1Memory-Mapped Registers ...................................................................................... 759 21-1Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) ........................................................... 765 22-1 Desktop and Mobile Component Ballout by Signal Name ............................................. 776 22-2Intel(R) ICH7-U Ballout by Signal Name ...................................................................... 784 23-1Intel(R) ICH7 Absolute Maximum Ratings .................................................................... 789 23-2DC Current Characteristics ...................................................................................... 790 23-3DC Current Characteristics (Mobile/Ultra Mobile Only) ................................................. 791 23-4DC Characteristic Input Signal Association................................................................. 792 23-5DC Input Characteristics ......................................................................................... 794 23-6DC Characteristic Output Signal Association............................................................... 796 23-7DC Output Characteristics ....................................................................................... 798 23-8Other DC Characteristics ......................................................................................... 799 23-9Clock Timings ........................................................................................................ 801 23-10PCI Interface Timing............................................................................................. 803 23-11IDE PIO Mode Timings .......................................................................................... 804 23-12IDE Multiword DMA Timings ................................................................................... 804 23-13Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ............................................................ 805 23-14Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ............................................................ 807 23-15Universal Serial Bus Timing ................................................................................... 809 23-16SATA Interface Timings (Desktop and Mobile Only) ................................................... 810 23-17SMBus Timing...................................................................................................... 810 23-19LPC Timing .......................................................................................................... 811 23-20Miscellaneous Timings........................................................................................... 811 23-18AC '97 / Intel(R) High Definition Audio Timing ............................................................ 811 23-21SPI Timings (Desktop and Mobile Only) ................................................................... 812 23-22(Power Sequencing and Reset Signal Timings........................................................... 812 23-23Power Management Timings .................................................................................. 814 25-1XOR Test Pattern Example ...................................................................................... 840 25-2XOR Chain 1 (REQ[4:1]# = 0000)............................................................................ 841 25-3XOR Chain 2 (REQ[4:1]# = 0001)............................................................................ 842 25-4XOR Chain 3 (REQ[4:1]# = 0010)............................................................................ 843 25-5XOR Chain 4-1 (REQ[4:1]# = 0011)......................................................................... 844 25-6XOR Chain 4-2 (REQ[4:1]# = 0011)......................................................................... 845 25-7XOR Chain 5 (REQ[4:1]# = 0100)............................................................................ 846 Intel (R) ICH7 Family Datasheet 33 Revision History Revision -001 -002 -003 * * * * Initial release Description Date April 2005 January 2006 April 2007 Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH Added specifications for the ICH7-U Added Documentation Changes/Specification Changes from Spec Update Revision -020. 34 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Family Features Direct Media Interface -- 10 Gb/s each direction, full duplex -- Transparent to software PCI Express* (Desktop and Mobile Only) -- 4 PCI Express root ports -- NEW: 2 Additional PCI Express root ports (ICH7R/ Digital Home only) configurable as x1 only -- Supports PCI Express 1.0a -- Ports 1-4 can be statically configured as 4x1, or 1x4. -- Support for full 2.5 Gb/s bandwidth in each direction per x1 lane -- Module based Hot-Plug supported (e.g., ExpressCard*) (Desktop and Mobile Only) PCI Bus Interface -- Supports PCI Rev 2.3 Specification at 33 MHz -- New: Six available PCI REQ/GNT pairs (3 pairs on Ultra Mobile) -- Support for 64-bit addressing on PCI using DAC protocol Integrated Serial ATA Host Controller (Desktop and Mobile Only) -- Four ports (desktop only) or two ports (Mobile only) -- NEW: Data transfer rates up to 3.0 Gb/s (300 MB/s) (Desktop Only) -- Integrated AHCI controller (RAID, Digital Home and Mobile only) Intel(R) Matrix Storage Technology (RAID and Digital Home only) -- Configures the ICH7 SATA controller as a RAID controller supporting RAID 0/1/10 (RAID and ICH7 DH only) -- Configures the ICH7 SATA controller as a RAID controller supporting RAID 0/1 (ICH7-M DH) -- NEW: Support for RAID 5 (RAID and ICH7 DH only) Integrated IDE Controller -- Independent timing of up to two drives (one drive on Ultra Mobile) -- Ultra ATA/100/66/33, BMIDE and PIO modes -- Tri-state modes to enable swap bay -- Supports ATA/ATAPI-7 Intel(R) High Definition Audio Interface -- PCI Express endpoint -- Independent Bus Master logic for eight general purpose streams: four input and four output -- Support three external Codecs -- Supports variable length stream slots -- Supports multichannel, 32-bit sample depth and 192 kHz sample rate output -- Provides mic array support -- Allows for non-48 kHz sampling output -- Support for ACPI Device States -- NEW: Docking Support (Mobile Only) -- NEW: Low Voltage Mode (Mobile/Ultra Mobile Only) AC-Link for Audio and Telephony CODECs (Desktop and Mobile Only) -- Support for three AC `97 2.3 codecs. -- Independent bus master logic for 8 channels (PCM In/ Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/ Out, S/PDIF Out) -- Support for up to six channels of PCM audio output (full AC3 decode) -- Supports wake-up events USB 2.0 -- Includes four UHCI Host Controllers, supporting eight external ports -- Includes one EHCI Host Controller that supports all eight ports -- Includes one USB 2.0 High-speed Debug Port -- Supports wake-up from sleeping states S1-S5 -- Supports legacy Keyboard/Mouse software Integrated LAN Controller (Desktop and Mobile Only) -- Integrated ASF Management Controller -- Supports IEEE 802.3 -- LAN Connect Interface (LCI) -- 10/100 Mb/s Ethernet Support NEW: Intel Active Management Technology (Desktop and Mobile Only) NEW: Intel(R) Quick Resume Technology Support (Digital Home Only) Power Management Logic -- Supports ACPI 3.0 -- ACPI-defined power states (C1, S1, S3-S5 for Desktop and C1-C4, S1, S3-S5 for Mobile/Ultra Mobile) -- ACPI Power Management Timer -- (Mobile/Ultra Mobile Only) Support for "Intel SpeedStep(R) Technology" processor power control and "Deeper Sleep" power state -- PCI CLKRUN# and PME# support -- SMI# generation -- All registers readable/restorable for proper resume from 0 V suspend states -- Support for APM-based legacy power management for non-ACPI Desktop and Mobile implementations External Glue Integration -- Integrated Pull-up, Pull-down and Series Termination resistors on IDE, processor interface -- Integrated Pull-down and Series resistors on USB Enhanced DMA Controller -- Two cascaded 8237 DMA controllers -- Supports LPC DMA (Desktop and Mobile Only) Intel (R) ICH7 Family Datasheet 35 SMBus -- Flexible SMBus/SMLink architecture to optimize for ASF -- Provides independent manageability bus through SMLink interface -- Supports SMBus 2.0 Specification -- Host interface allows processor to communicate via SMBus -- Slave interface allows an internal or external Microcontroller to access system resources -- Compatible with most two-wire components that are also I2C compatible High Precision Event Timers -- Advanced operating system interrupt scheduling Timers Based on 82C54 -- System timer, Refresh request, Speaker tone output Real-Time Clock -- 256-byte battery-backed CMOS RAM -- Integrated oscillator components -- Lower Power DC/DC Converter implementation System TCO Reduction Circuits -- Timers to generate SMI# and Reset upon detection of system hang -- Timers to detect improper processor reset -- Integrated processor frequency strap logic -- Supports ability to disable external devices Interrupt Controller -- Supports up to eight PCI interrupt pins -- Supports PCI 2.3 Message Signaled Interrupts -- Two cascaded 82C59 with 15 interrupts -- Integrated I/O APIC capability with 24 interrupts -- Supports Processor System Bus interrupt delivery 1.05 V operation with 1.5 V and 3.3 V I/O -- 5 V tolerant buffers on IDE, PCI, USB and Legacy signals NEW: 1.05 V Core Voltage Integrated 1.05 V Voltage Regulator (INTVR) for the Suspend and LAN wells (Desktop and Mobile Only) Firmware Hub I/F supports BIOS Memory size up to 8 MBytes (Desktop and Mobile Only) NEW: Serial Peripheral Interface (SPI) for Serial and Shared Flash (Desktop and Mobile Only) Low Pin Count (LPC) I/F -- Supports two Master/DMA devices. -- Support for Security Device (Trusted Platform Module) connected to LPC. GPIO -- TTL, Open-Drain, Inversion NEW: Package 31 mm x 31 mm 652 mBGA (Desktop and Mobile Only) New: Package 15 mm x 15 mm, 452 balls (Ultra Mobile only) Desktop Configuration DMI (To (G)MCH) USB 2.0 (Supports 8 USB ports) Power Management Clock Generators IDE SATA (4 ports) AC '97/Intel(R) High Definition Audio Codec(s) Intel(R) ICH7 System Management (TCO) SMBus 2.0/I2C PCI Bus SPI BIOS Intel(R) PCI Express Gigabit Ethernet PCI Express* x1 LAN Connect GPIO LPC I/F Other ASICs (Optional) S L O T ... S L O T Super I/O TPM (Optional) Firmware Hub 36 Intel (R) ICH7 Family Datasheet Mobile Configuration DMI (To (G)MCH) USB 2.0 (Supports 8 USB ports) Power Management Clock Generators IDE SATA (2 ports) AC'97/Intel(R) High Definition Audio Codec(s) Intel(R) ICH7-M System Management (TCO) SMBus 2.0/I2C PCI Bus Docking Bridge PCI Express x1 LAN Connect GPIO Other ASICs (Optional) Cardbus Controller (& attached slots) LPC I/F Super I/O SPI BIOS TPM (Optional) Flash BIOS Ultra Mobile Configuration DMI (To GMCH) USB 2.0 (Supports 8 USB ports) Power Management Clock Generators IDE Intel(R) High Definition Audio Codec(s) GPIO Intel(R) ICH7-U System Management (TCO) SMBus 2.0/I2C PCI Bus 3 PCI Other ASICs (Optional) LPC I/F Super I/O TPM (Optional) Flash BIOS Intel (R) ICH7 Family Datasheet 37 38 Intel (R) ICH7 Family Datasheet Introduction 1 Introduction This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel(R) I/O Controller Hub 7 (ICH7) Family based products. This document is the datasheet for the following: * Intel(R) 82801GB ICH7 (ICH7) * Intel(R) 82801GR ICH7 RAID (ICH7R) * Intel(R) 82801GDH ICH7 Digital Home (ICH7DH) * Intel(R) 82801GBM ICH7 Mobile (ICH7-M) * Intel(R) 82801GHM ICH7 Mobile Digital Home (ICH7-M DH) * Intel(R) 82801GU ICH7-U Ultra Mobile (ICH7-U) Section 1.2 provides high-level feature differences for the ICH7 Family components. Note: Throughout this datasheet, ICH7 is used as a general ICH7 term and refers to the 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U components, unless specifically noted otherwise. Throughout this datasheet, the term "Desktop" refers to any implementation, be it in a desktop, server, workstation, etc., unless specifically noted otherwise. Throughout this datasheet, the terms "Desktop", "Digital Home" "Mobile", and "Ultra Mobile" refer to the following components, unless specifically noted otherwise: * Desktop refers to the 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH. * Digital Home refers to the 82801GDH ICH7DH and 82801GHM ICH7-M DH. * Mobile refers to the 82801GBM ICH7-M, and 82801GHM ICH7-M DH. * Ultra Mobile refers to the 82801GU ICH7-U. Note: Note: Note: "Desktop and Mobile Only" refers to all components in this document except the 82801GU ICH7-U Ultra Mobile component. This datasheet assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, IDE, AHCI, SATA, Intel(R) High Definition Audio (Intel(R) HD Audio), AC '97, SMBus, PCI, ACPI and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in Table 1-1 for the complete details. Table 1-1. Industry Specifications Specification Intel(R) I/O Controller Hub ICH7 Family Specification Update Intel(R) I/O Controller Hub ICH7 Family Thermal Mechanical Guidelines PCI Express* Base Specification, Revision 1.0a Low Pin Count Interface Specification, Revision 1.1 (LPC) Audio Codec `97 Component Specification, Version 2.3 (AC '97) Location http://developer.intel.com//design/ chipsets/specupdt/307014.htm http://developer.intel.com//design/ chipsets/designex/307015.htm http://www.pcisig.com/specifications http://developer.intel.com/design/ chipsets/industry/lpc.htm http://www.intel.com/design/ chipsets/audio/ Intel (R) ICH7 Family Datasheet 39 Introduction Table 1-1. Industry Specifications Specification System Management Bus Specification, Version 2.0 (SMBus) PCI Local Bus Specification, Revision 2.3 (PCI) PCI Mobile Design Guide, Revision 1.1 PCI Power Management Specification, Revision 1.1 Universal Serial Bus Specification (USB), Revision 2.0 Advanced Configuration and Power Interface, Version 2.0 (ACPI) Universal Host Controller Interface, Revision 1.1 (UHCI) Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI) Serial ATA Specification, Revision 1.0a Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 Alert Standard Format Specification, Version 1.03 IEEE 802.3 Fast Ethernet AT Attachment - 6 with Packet Interface (ATA/ATAPI 6) IA-PC HPET (High Precision Event Timers) Specification, Revision 1.0 Location http://www.smbus.org/specs/ http://www.pcisig.com/specifications http://www.pcisig.com/specifications http://www.pcisig.com/specifications http://www.usb.org/developers/docs http://www.acpi.info/spec.htm http://developer.intel.com/design/ USB/UHCI11D.htm http://developer.intel.com/ technology/usb/ehcispec.htm http://www.serialata.org/ specifications.asp http://www.serialata.org/ specifications.asp http://www.dmtf.org/standards/asf http://standards.ieee.org/ getieee802/ http://T13.org (T13 1410D) http://www.intel.com/ hardwaredesign/hpetspec.htm Chapter 1. Introduction Chapter 1 introduces the ICH7 and provides information on manual organization and gives a general overview of the ICH7. Chapter 2. Signal Description Chapter 2 provides a block diagram of the ICH7 interface signals and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. Intel(R) ICH7 Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. Chapter 4. Intel(R) ICH7 and System Clock Domains Chapter 4 provides a list of each clock domain associated with the ICH7 in an ICH7 based system. Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH7. All PCI buses, devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH7's external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. 40 Intel (R) ICH7 Family Datasheet Introduction Chapter 6. Register and Memory Mappings Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH7. Chapter 7. Chipset Configuration Registers Chapter 7 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains the root complex register block, which describes the behavior of the upstream internal link. Chapter 8. LAN Controller Registers Chapter 8 provides a detailed description of all registers that reside in the ICH7's integrated LAN controller. The integrated LAN controller resides on the ICH7's external PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0). Chapter 9. PCI-to-PCI Bridge Registers Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 10. LPC Bridge Registers Chapter 10 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH7 including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC. Chapter 11. SATA Controller Registers Chapter 12 provides a detailed description of all registers that reside in the SATA controller. This controller resides at Device 31, Function 2 (D31:F2). Chapter 12. UHCI Controller Registers Chapter 11 provides a detailed description of all registers that reside in the four UHCI host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3 (D29:F0/F1/F2/F3). Chapter 13. EHCI Controller Registers Chapter 13 provides a detailed description of all registers that reside in the EHCI host controller. This controller resides at Device 29, Function 7 (D29:F7). Chapter 14. SMBus Controller Registers Chapter 14 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 15. IDE Controller Registers Chapter 15 provides a detailed description of all registers that reside in the IDE controller. This controller resides at Device 31, Function 1 (D31:F1). Chapter 16. AC '97 Audio Controller Registers Chapter 16 provides a detailed description of all registers that reside in the audio controller. This controller resides at Device 30, Function 2 (D30:F2). Note that this section of the datasheet does not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 17. AC '97 Modem Controller Registers Chapter 17 provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 30, Function 3 (D30:F3). Note that this section of the datasheet does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. Chapter 18. Intel(R) High Definition Audio Controller Registers Chapter 18 provides a detailed description of all registers that reside in the Intel(R) High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 19. PCI Express* Port Controller Registers Chapter 19 provides a detailed description of all registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5). Intel (R) ICH7 Family Datasheet 41 Introduction Chapter 20. High Precision Event Timers Registers Chapter 20 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 21. Serial Peripheral Interface Registers Chapter 21 provides a detailed description of all registers that reside in the SPI memory mapped register space. Chapter 22. Ballout Definition Chapter 22 provides a table of each signal and its ball assignment in the 652-mBGA package. Chapter 23. Electrical Characteristics Chapter 23 provides all AC and DC characteristics including detailed timing diagrams. Chapter 24. Package Information Chapter 24 provides drawings of the physical dimensions and characteristics of the 652-mBGA package. Chapter 25. Testability Chapter 25 provides detail about the implementation of test modes provided in the ICH7. 1.1 Overview The ICH7 provides extensive I/O support. Functions and capabilities include: * PCI Express* Base Specification, Revision 1.0a support (Desktop and Mobile Only) * PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports up to six Req/Gnt pairs; three pairs on Ultra Mobile). * ACPI Power Management Logic Support * Enhanced DMA controller, interrupt controller, and timer functions (Desktop and Mobile Only) * Integrated Serial ATA host controller with independent DMA operation on four ports (Desktop only) or two ports (Mobile Only) and AHCI (ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) support. (SATA not supported on Ultra Mobile) * Integrated IDE controller supports Ultra ATA100/66/33 * USB host interface with support for eight USB ports; four UHCI host controllers; one EHCI high-speed USB 2.0 Host controller * Integrated LAN controller (Desktop and Mobile Only) * System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices (Desktop and Mobile Only) * Supports Audio Codec '97, Revision 2.3 Specification (a.k.a., AC '97 Component Specification, Revision 2.3) which provides a link for Audio and Telephony codecs (up to 7 channels) (Desktop and Mobile Only) * Supports Intel High Definition Audio * Supports Intel(R) Matrix Storage Technology (ICH7R, ICH7DH, and Mobile Only) * Supports Intel(R) Active Management Technology (Desktop and Mobile Only) * Low Pin Count (LPC) interface * Firmware Hub (FWH) interface support * Serial Peripheral Interface (SPI) support (Desktop and Mobile Only) 42 Intel (R) ICH7 Family Datasheet Introduction The ICH7 incorporates a variety of PCI functions that are divided into six logical devices (B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8) as listed in Table 1-2. D30 is the DMI-to-PCI bridge and the AC '97 Audio and Modem controller functions, D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and SMBus controller, D29 contains the four USB UHCI controllers and one USB EHCI controller, and D27 contains the PCI Express root ports. B1:D8 is the integrated LAN controller. Table 1-2. PCI Devices and Functions Bus:Device:Function Bus 0:Device 30:Function 0 Bus 0:Device 30:Function 2 Bus 0:Device 30:Function 3 Bus 0:Device 31:Function 0 Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 0:Device 29:Function 0 Bus 0:Device 29:Function 1 Bus 0:Device 29:Function 2 Bus 0:Device 29:Function 3 Bus 0:Device 29:Function 7 Bus 0:Device 28:Function 0 Bus 0:Device 28:Function 1 Bus 0:Device 28:Function 2 Bus 0:Device 28:Function 3 Bus 0:Device 28:Function 4 Bus 0:Device 28:Function 5 Bus 0:Device 27:Function 0 Bus n:Device 8:Function 0 PCI-to-PCI Bridge AC '97 Audio Controller (Desktop and Mobile Only) AC '97 Modem Controller (Desktop and Mobile Only) LPC Controller1 IDE Controller SATA Controller (Desktop and Mobile Only) SMBus Controller USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 USB UHCI Controller #4 USB 2.0 EHCI Controller PCI Express* Port 1 (Desktop and Mobile Only) PCI Express Port 2 (Desktop and Mobile Only) PCI Express Port 3 (Desktop and Mobile Only) PCI Express Port 4 (Desktop and Mobile Only) PCI Express Port 5 (Intel(R) ICH7R, ICH7DH, and ICH7-M DH Only) PCI Express Port 6 (Intel ICH7R, ICH7DH, and ICH7-M DH Only) Intel(R) High Definition Audio Controller LAN Controller (Desktop and Mobile Only) Function Description NOTES: 1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA. The following sub-sections provide an overview of the ICH7 capabilities. Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. Intel (R) ICH7 Family Datasheet 43 Introduction PCI Express* Interface (Desktop and Mobile Only) The ICH7R, ICH7DH, ICH7-M DH have six PCI Express root ports and the ICH7 and ICH7-M have four PCI Express root ports (ports 1-4), supporting the PCI Express Base Specification, Revision 1.0a. PCI Express root ports 1-4 can be statically configured as four x1 ports or ganged together to form one x4 port. Ports 5 and 6 on the ICH7R, ICH7DH, and ICH7-M DH can only be used as two x1 ports. Each Root Port supports 2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent). Serial ATA (SATA) Controller (Desktop and Mobile Only) The ICH7 has an integrated SATA host controller that supports independent DMA operation on four ports (desktop only) or two ports (mobile only) and supports data transfer rates of up to 3.0 Gb/s (300 MB/s). The SATA controller contains two modes of operation - a legacy mode using I/O space, and an AHCI mode using memory space. SATA and PATA can also be used in a combined function mode (where the SATA function is used with PATA). In this combined function mode, AHCI mode is not used. Software that uses legacy mode will not have AHCI capabilities. The ICH7 supports the Serial ATA Specification, Revision 1.0a. The ICH7 also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). AHCI (Intel(R) ICH7R, ICH7DH, and Mobile Only) The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices--each device is treated as a master--and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug (Desktop and Mobile Only). AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. Intel(R) Matrix Storage Technology (Intel(R) ICH7R, ICH7DH, and ICH7-M DH Only) The ICH7 provides support for Intel Matrix Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality (RAID 0/1 functionality for ICH7-M DH) on up to 4 SATA ports of ICH7. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft* Windows* compatible driver, and a user interface for configuration and management of the RAID capability of ICH7. PCI Interface The ICH7 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters (three on Ultra Mobile) in addition to the internal ICH7 requests. This allows for combinations of up to six PCI down devices (three on Ultra Mobile) and PCI slots. 44 Intel (R) ICH7 Family Datasheet Introduction IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile) providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The ICH7's IDE system contains a single, independent IDE signal channel that can be electrically isolated. There are integrated series resistors on the data and control lines (see Section 5.16 for details). Low Pin Count (LPC) Interface The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. Serial Peripheral Interface (SPI) (Desktop and Mobile Only) The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH. Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0-3 are hardwired to 8-bit, count-bybyte transfers, and channels 5-7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA, through the ICH7's DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0- 3 are 8-bit channels. Channels 5-7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The ICH7 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH7 supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform. Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the ICH7 incorporates the Advanced Programmable Interrupt Controller (APIC). Intel (R) ICH7 Family Datasheet 45 Introduction Universal Serial Bus (USB) Controller The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH7 also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. The ICH7 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and low-speed capable. ICH7's port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See Section 5.19 and Section 5.20 for details. LAN Controller (Desktop and Mobile Only) The ICH7's integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The LAN controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.3 for details. Alert Standard Format (ASF) Management Controller (Desktop and Mobile Only) ICH7 integrates an Alert Standard Format controller in addition to the integrated LAN controller, allowing interface system-monitoring devices to communicate through the integrated LAN controller to the network. This makes remote manageability and system hardware monitoring possible using ASF. The ASF controller can collect and send various information from system components such as the processor, chipset, BIOS and sensors on the motherboard to a remote server running a management console. The controller can also be programmed to accept commands back from the management console and execute those commands on the local system. 46 Intel (R) ICH7 Family Datasheet Introduction RTC The ICH7 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on ICH7 configuration. Enhanced Power Management The ICH7's power management functions include enhanced clock control and various low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-to-Disk). A hardwarebased thermal management circuit permits software-independent entrance to lowpower states. The ICH7 contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 3.0. Intel(R) Quick Resume Technology (Digital Home Only) ICH7 implements Intel Quick Resume Technology that provides the capability to design a PC with a single power button that reliably and instantly (user's perception) turns the PC On and Off. When the system is On and the user presses the power button, the display instantly goes dark, sound is muted, and there is no response to keyboard/ mouse commands (except for keyboard power button). When the system is Off and the user presses the power button, picture and sound quickly return, and the keyboard/ mouse return to normal functionality, allowing user input. Intel(R) Active Management Technology (Intel(R) AMT) (Desktop and Mobile Only) Intel Active Management Technology is the next generation of client manageability via the wired network. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. Intel (R) ICH7 Family Datasheet 47 Introduction Manageability In addition to Intel AMT the ICH7 integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. * TCO Timer. The ICH7's integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock. * Processor Present Indicator. The ICH7 looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH7 will reboot the system. * ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the ICH7. The host controller can instruct the ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt. * Function Disable. The ICH7 provides the ability to disable the following integrated functions: AC '97 Modem, AC '97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SATA, or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disable functions. * Intruder Detect. The ICH7 provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The ICH7 can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal. System Management Bus (SMBus 2.0) (Desktop and Mobile Only) The ICH7 contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented. The ICH7's SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the ICH7 supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. ICH7's SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices. 48 Intel (R) ICH7 Family Datasheet Introduction Intel(R) High Definition Audio Controller The Intel(R) High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The ICH7 Intel HD Audio digital link shares pins with the AC-link. Concurrent operation of Intel HD Audio and AC '97 functionality is not supported. The ICH7 Intel HD Audio controller supports up to 3 codecs. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel(R) HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the ICH7 adds support for an arrays of microphones. The Intel HD Audio controller uses multi-purpose DMA engines, as opposed to dedicated DMA engines in AC '97 (Desktop and Mobile Only), to effectively manage the link bandwidth and support simultaneous independent streams on the link. The capability enables new exciting usage models with Intel HD Audio (e.g., listening to music while playing multi-player game on the internet.) The Intel HD Audio controller also supports isochronous data transfers allowing glitch-free audio to the system. Note: Users interested in providing feedback on the Intel High Definition Audio Specification or planning to implement the Intel High Definition Audio Specification into a future product will need to execute the Intel High Definition Audio Specification Developer's Agreement. For more information, contact nextgenaudio@intel.com. AC '97 2.3 Controller (Desktop and Mobile Only) The ICH7 integrates an Audio Codec '97 Component Specification, Version 2.3 controller that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or a combination of ACs and a single MC. The ICH7 supports up to six channels of PCM audio output (full AC3 decode). For a complete surround-sound experience, six-channel audio consists of: front left, front right, back left, back right, center, and subwoofer. ICH7 has expanded support for up to three audio codecs on the AC-link. In addition, an AC '97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC '97. The ICH7-integrated AC '97 controller allows up to three external codecs to be connected to the ICH7. The system designer can provide AC '97 modem with a modem codec, or both audio and modem with up to two audio codecs with a modem codec. Intel (R) ICH7 Family Datasheet 49 Introduction 1.2 Intel(R) ICH7 Family High-Level Component Differences Intel(R) ICH7 Desktop/Server Family1 Base Features Intel(R) Matrix Storage Technology RAID 0/1/5/10 / AHCI No/No Yes / Yes Yes / Yes 6 PCI Express Ports Intel(R) AMT Support Intel(R) Quick Resume Technology No Yes No Table 1-3. Product Name Intel(R) ICH7 Base (ICH7) ICH7 Digital Home (ICH7DH) ICH7 RAID (ICH7R) Yes Yes Yes No2 Yes2 Yes2 Yes Yes Yes NOTES: 1. Feature capability can be read in D31:F0:Offset E4h. 2. The ICH7 Base (ICH7) supports Ports 1:4; ICH7 RAID (ICH7R) and ICH7 Digital Home (ICH7DH) supports Ports 1:6. Table 1-4. Intel(R) ICH7-M Mobile and ICH7-U Ultra Mobile Components1 Product Name Short Name ICH7-M ICH7-M DH ICH7-U Base Features Yes Yes Not all features AHCI Intel(R) Matrix Storage Technology RAID 0/1 No Yes No 6 PCI Express* Ports No Yes No Intel(R) AMT Ready Yes Yes No ICH7 Mobile ICH7 Mobile Digital Home ICH7 Ultra Mobile Yes Yes No NOTES: 1. Feature capability can be read in D31:F0:Offset E4h. 50 Intel (R) ICH7 Family Datasheet Signal Description 2 Signal Description This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. Figure 2-1 shows the interface signals for the Intel(R) 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH. Figure 2-2 shows the interface signals for the 82801GBM ICH7-M and 82801GHM ICH7-M DH. Figure 2-3 shows the interface signals for the 82801GU ICH7U. The "#" symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present, the signal is asserted when at the high voltage level. The "Type" for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted in Section 3.3 or Section 3.4, a signal is considered to be in the functional operating mode after RTCRST# for signals in the RTC well, RSMRST# for signals in the suspend well, after PWROK for signals in the core well, and after LAN_RST# for signals in the LAN well. The following notations are used to describe the signal type: I O OD O I/OD I/O OC Input Pin Output Pin Open Drain Output Pin. Bi-directional Input/Open Drain Output Pin. Bi-directional Input / Output Pin. Open Collector Output Pin. Intel (R) ICH7 Family Datasheet 51 Signal Description Figure 2-1. Interface Signals Block Diagram (Desktop Only) AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[3:0]# REQ[4]# / GPIO[22] REQ[5]# / GPIO[1] GNT[3:0]# GNT[4]# / GPIO[48] GNT[5]# / GPIO[17] PCICLK PCIRST# PLOCK# SERR# PME# A20M# CPUSLP# FERR# IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD / GPIO[49] SPI_CS# SPI_MISO SPI_MOSI SPI_ARB SPI_CLK SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] IDEIRQ USBP[7:0]P USBP[7:0]N OC[4:0]# OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31] USBRBIAS# USBRBIAS RTCX1 RTCX2 CLK14 CLK48 SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN INTVRMEN SPKR RTCRST# TP0 TP[2:1] TP3 GPIO[39:38, 34:32, 28:26, 25:24, 20, 18, 16:12, 10:6] EE_SHCLK EE_DIN EE_DOUT EE_CS DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#) PETp[6:1], PETn[6:1] PERp[6:1], PERn[6:1] SATA[3:0]TXP, SATA[3:0]TXN SATA[3:0]RXP, SATA[3:0]RXN SATARBIAS SATARBIAS# SATA[3:0]GP/GPIO[37,36,21,19] SATALED# SATACLKREQ#/GPIO[35] THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD PLTRST# ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDOUT ACZ_SDIN[2:0] DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPIO[23] SMBDATA SMBCLK SMBALERT# / GPIO[11] INTRUDER# SMLINK[1:0] LINKALERT# LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC EL_RSVD / GPIO26 EL_STATE[1:0] / GPIO[28:27] Digital Home Only IDE Interface PCI Interface PCI Express* Interface Serial ATA Interface Processor Interface Power Mgnt. SPI AC '97/ (R) Intel High Definition Audio Direct Media Interface Interrupt Interface USB Firmware Hub RTC LPC Interface Clocks SMBus Interface Misc. Signals System Mgnt. Platform LAN Connect Intel(R) Quick Resume Technology General Purpose I/O EEPROM Interface 52 Intel (R) ICH7 Family Datasheet Signal Description Figure 2-2. Interface Signals Block Diagram (Mobile Only) AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[3:0]# REQ[4]# / GPIO[22] REQ[5]# / GPIO[1] GNT[3:0]# GNT[4]# / GPIO[48] GNT[5]# / GPIO[17] PME# CLKRUN# PCICLK PCIRST# PLOCK# SERR# SPI_CS# SPI_MISO SPI_MOSI SPI_ARB SPI_CLK IDE Interface DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#) PETp[6:1], PETn[6:1] PERp[6:1], PERn[6:1] SATA[2,0]TXP, SATA[2,0]TXN SATA[2,0]RXP, SATA[2,0]RXN SATARBIAS SATARBIAS# SATA[2,0]GP/GPIO[36,21] SATALED# SATACLKREQ# THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# DPRSTP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK LAN_RST# VRMPWRGD BMBUSY# / GPIO[0] STP_PCI# STP_CPU# BATLOW# DPRSLPVR PLTRST# ACZ_RST#, ACZ_SYNC, ACZ_SDOUT PCI Interface PCI Express* Interface Serial ATA Interface SPI A20M# FERR# IGNNE# INIT# INIT3_3# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD / GPIO[49] DPSLP# SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] IDEIRQ USBP[7:0]P USBP[7:0]N OC[4:0]# OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31] USBRBIAS USBRBIAS# RTCX1 RTCX2 CLK14 CLK48 SATA_CLKP, SATA_CLKN DMI_CLKP, DMI_CLKN INTVRMEN SPKR RTCRST# TP[3] GPIO[39:37,25:24,19,1 5:12,10:6] EE_SHCLK EE_DIN EE_DOUT EE_CS Processor Interface Power Mgnt. Interrupt Interface AC '97/ (R) Intel High Definition Audio USB Direct Media Interface Firmware Hub LPC Interface Clocks SMBus Interface Misc. Signals System Mgnt. Platform LAN Connect Digital Home ACZ_SDIN[2:0] ACZ_BIT_CLK AZ_DOCK_EN# / GPIO[33] AZ_DOCK_RST# / GPIO[34] DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ[0]# LDRQ[1]# / GPIO[23] SMBDATA SMBCLK SMBALERT# / GPIO[11] INTRUDER# SMLINK[1:0] LINKALERT# LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC El_RSVD / GPIO26 El_STATE[1:0] / GPIO[28:27 Digital Home Only ICH7_Signals_Mobile RTC General Purpose I/O EEPROM Interface Intel (R) ICH7 Family Datasheet 53 Signal Description Figure 2-3. Interface Signals Block Diagram (Ultra Mobile Only) AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ3# REQ4# / GPIO[22] REQ5# / GPIO[1] GNT3]# GNT4# / GPIO[48] GNT5# / GPIO[17] PME# CLKRUN# PCICLK PCIRST# PLOCK# SERR# A20M# FERR# IGNNE# INIT# INIT3_3# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD / GPIO[49] DPSLP# SERIRQ PIRQ[H:E]# / GPIO[5:2] IDEIRQ USBP[7:0]P USBP[7:0]N OC[4:0]# OC[5]# / GPIO[29] OC[6]# / GPIO[30] OC[7]# / GPIO[31] USBRBIAS USBRBIAS# RTCX1 RTCX2 CLK14 CLK48 DMI_CLKP, DMI_CLKN DCS1# DCS3# DA[2:0] DD[15:0] DDREQ DDACK# DIOR# (DWSTB / RDMARDY#) DIOW# (DSTOP) IORDY (DRSTB / WDMARDY#) THRM# THRMTRIP# SYS_RESET# RSMRST# MCH_SYNC# DPRSTP# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# WAKE# SUS_STAT# / LPCPD# SUSCLK VRMPWRGD BMBUSY# / GPIO[0] STP_PCI# STP_CPU# BATLOW# DPRSLPVR PLTRST# ACZ_RST#, ACZ_SYNC, ACZ_SDOUT ACZ_SDIN[2:0] ACZ_BIT_CLK DMI[1:0]TXP, DMI[1:0]TXN DMI[1:0]RXP, DMI[1:0]RXN DMI_ZCOMP DMI_IRCOMP FWH[3:0] / LAD[3:0] FWH[4] / LFRAME# LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] LDRQ0# LDRQ1# / GPIO[23] SMBDATA SMBCLK SMBALERT# / GPIO[11] INTRUDER# LINKALERT# IDE Interface PCI Interface Power Mgnt. Processor Interface Interrupt Interface Intel High Definition Audio Direct Media Interface (R) USB Firmware Hub LPC Interface RTC SMBus Interface Clocks System Mgnt. SPKR RTCRST# TP3 GPIO[39:37,25:24,19,1 5:12,10:6] Misc. Signals General Purpose I/O ICH7 Signals Ultra Mobile 54 Intel (R) ICH7 Family Datasheet Signal Description 2.1 Table 2-1. Direct Media Interface (DMI) to Host Controller Direct Media Interface Signals Name DMI[0:1]TXP, DMI[0:1]TXN DMI[2:3]TXP, DMI[2:3]TXN (Desktop and Mobile Only) DMI[0:1]RXP, DMI[0:1]RXN DMI[2:3]RXP, DMI[2:3]RXN (Desktop and Mobile Only) DMI_ZCOMP DMI_IRCOMP I Direct Media Interface Differential Receive Pair 0:3 O Direct Media Interface Differential Transmit Pair 0:3 Type Description I O Impedance Compensation Input: Determines DMI input impedance. Impedance/Current Compensation Output: Determines DMI output impedance and bias current. 2.2 Table 2-2. PCI Express* (Desktop and Mobile Only) PCI Express* Signals Name PETp[1:4], PETn[1:4] PERp[1:4], PERn[1:4] PETp[5:6], PETn[5:6] (Intel(R) ICH7R/ ICH7DH/ICH7-M DH Only) PERp[1:4], PERn[5:6] (ICH7R/ICH7DH/ ICH7-M DH Only) O Type O I Description PCI Express* Differential Transmit Pair 1:4 PCI Express Differential Receive Pair 1:4 PCI Express* Differential Transmit Pair 5:6 Reserved: ICH7/ICH7-M I PCI Express Differential Receive Pair 5:6 Reserved: ICH7/ICH7-M Intel (R) ICH7 Family Datasheet 55 Signal Description 2.3 Platform LAN Connect Interface (Desktop and Mobile Only) Platform LAN Connect Interface Signals Name LAN_CLK Type I Description LAN I/F Clock: This signal is driven by the Platform LAN Connect component. The frequency range is 5 MHz to 50 MHz. Received Data: The Platform LAN Connect component uses these signals to transfer data and control information to the integrated LAN controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN controller uses these signals to transfer data and control information to the Platform LAN Connect component. LAN Reset/Sync: The Platform LAN Connect component's Reset and Sync signals are multiplexed onto this pin. Table 2-3. LAN_RXD[2:0] I LAN_TXD[2:0] O LAN_RSTSYNC O 2.4 Table 2-4. EEPROM Interface (Desktop and Mobile Only) EEPROM Interface Signals Name EE_SHCLK EE_DIN EE_DOUT EE_CS Type O I O O Description EEPROM Shift Clock: This signal is the serial shift clock output to the EEPROM. EEPROM Data In: This signal transfers data from the EEPROM to the Intel(R) ICH7. This signal has an integrated pull-up resistor. EEPROM Data Out: This signal transfers data from the ICH7 to the EEPROM. EEPROM Chip Select: This is the chip select signal to the EEPROM. 2.5 Firmware Hub Interface (Desktop and Mobile Only) Firmware Hub Interface Signals Name FWH[3:0] / LAD[3:0] FWH4 / LFRAME# Type I/O O Description Firmware Hub Signals: These signals are multiplexed with the LPC address signals. Firmware Hub Signals: This signal is multiplexed with the LPC LFRAME# signal. Table 2-5. 56 Intel (R) ICH7 Family Datasheet Signal Description 2.6 Table 2-6. PCI Interface PCI Interface Signals (Sheet 1 of 3) Name Type Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel(R) ICH7 will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# 0000b 0001b 0010b 0011b C/BE[3:0]# I/O 0110b 0111b 1010b 1011b 1100b 1110b 1111b Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate AD[31:0] I/O All command encodings not shown are reserved. The ICH7 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Device Select: The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH7 address or an address destined DMI (main memory or graphics). As an input, DEVSEL# indicates the response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tristated by the ICH7 until driven by a target device. Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH7 when the ICH7 is the target, and FRAME# is an output from the ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the ICH7 until driven by an initiator. Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH7 has valid data present on AD[31:0]. During a read, it indicates the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 when the ICH7 is the target and an output from the ICH7 when the ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until driven by an initiator. DEVSEL# I/O FRAME# I/O IRDY# I/O Intel (R) ICH7 Family Datasheet 57 Signal Description Table 2-6. PCI Interface Signals (Sheet 2 of 3) Name Type Description Target Ready: TRDY# indicates the Intel(R) ICH7's ability as a target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH7, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the ICH7, as a target is prepared to latch data. TRDY# is an input to the ICH7 when the ICH7 is the initiator and an output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the ICH7 until driven by a target. Stop: STOP# indicates that the ICH7, as a target, is requesting the initiator to stop the current transaction. STOP# causes the ICH7, as an initiator, to stop the current transaction. STOP# is an output when the ICH7 is a target and an input when the ICH7 is an initiator. Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the ICH7 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH7 calculates PAR on 36 bits regardless of the valid byte enables. The ICH7 generates PAR for address and data phases and only ensures PAR to be valid one PCI clock after the corresponding address or data phase. The ICH7 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH7 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH7 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH7 is the initiator of a PCI write transaction, and when it is the target of a read transaction. ICH7 checks parity when it is the target of a PCI write transaction. If a parity error is detected, the ICH7 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH7 drives PERR# when it detects a parity error. The ICH7 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The ICH7 supports up to 6 masters on the PCI bus. The REQ4# and REQ5# pins can instead be used as a GPIO. NOTE: REQ[2:0]# are not on Ultra Mobile. PCI Grants: The ICH7 supports up to 6 masters on the PCI bus. The GNT4# and GNT5# pins can instead be used as a GPIO. O Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up. NOTE: GNT[2:0]# are not on Ultra Mobile. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. PCICLK I NOTE: (Mobile/Ultra Mobile Only) This clock does not stop based on STP_PCI# signal. PCI Clock only stops based on SLP_S3#. PCIRST# O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). TRDY# I/O STOP# I/O PAR I/O PERR# I/O REQ[3:0]# REQ4# / GPIO22 REQ5# / GPIO1 GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17# I 58 Intel (R) ICH7 Family Datasheet Signal Description Table 2-6. PCI Interface Signals (Sheet 3 of 3) Name Type Description PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. The ICH7 asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus in desktop configurations. Devices on the PCI bus (other than the ICH7) are not permitted to assert the PLOCK# signal in mobile/Ultra Mobile configurations. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH7 has the ability to generate an NMI, SMI#, or interrupt. PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1-S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH7 may drive PME# active due to an internal wake event. The ICH7 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PLOCK# I/O SERR# I/OD PME# I/OD 2.7 Table 2-7. Serial ATA Interface (Desktop and Mobile Only) Serial ATA Interface Signals (Sheet 1 of 2) Name SATA0TXP SATA0TXN SATA0RXP SATA0RXN SATA1TXP SATA1TXN (Desktop Only) SATA1RXP SATA1RXN (Desktop Only) SATA2TXP SATA2TXN SATA2RXP SATA2RXN SATA3TXP SATA3TXN (Desktop Only) SATA3RXP SATA3RXN (Desktop Only) SATARBIAS SATARBIAS# I O I O Type O I Description Serial ATA 0 Differential Transmit Pair: These are outbound high-speed differential signals to Port 0. Serial ATA 0 Differential Receive Pair: These are inbound highspeed differential signals from Port 0. Serial ATA 1 Differential Transmit Pair: These are outbound high-speed differential signals to Port 1. (Desktop Only) Serial ATA 1 Differential Receive Pair: These are inbound highspeed differential signals from Port 1. (Desktop Only) Serial ATA 2 Differential Transmit Pair: These are outbound high-speed differential signals to Port 2. Serial ATA 2 Differential Receive Pair: These are inbound highspeed differential signals from Port 2. Serial ATA 3 Differential Transmit Pair: These are outbound high-speed differential signals to Port 3. (Desktop Only) Serial ATA 3 Differential Receive Pair: These are inbound highspeed differential signals from Port 3. (Desktop Only) Serial ATA Resistor Bias: These are analog connection points for an external resistor to ground. Serial ATA Resistor Bias Complement: These are analog connection points for an external resistor to ground. O I O I Intel (R) ICH7 Family Datasheet 59 Signal Description Table 2-7. Serial ATA Interface Signals (Sheet 2 of 2) Name Type Description Serial ATA 0 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0. When used as an interlock switch status indication, this signal should be drive to `0' to indicate that the switch is closed and to `1' to indicate that the switch is open. If interlock switches are not required, this pin can be configured as GPIO21. SATA1GP (Desktop Only) / GPIO19 Serial ATA 1 General Purpose: Same function as SATA0GP, except for SATA Port 1. If interlock switches are not required, this pin can be configured as GPIO19. Serial ATA 2 General Purpose: Same function as SATA0GP, except for SATA Port 2. If interlock switches are not required, this pin can be configured as GPIO36. Serial ATA 3 General Purpose: Same function as SATA0GP, except for SATA Port 3. If interlock switches are not required, this pin can be configured as GPIO37. Serial ATA LED: This is an open-collector output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required. NOTE: An internal pull-up is enabled only during PLTRST# assertion. SATA0GP / GPIO21 I I SATA2GP / GPIO36 I SATA3GP (Desktop Only) / GPIO37 I SATALED# OC Serial ATA Clock Request: This is an open-drain output pin when OD configured as SATACLKREQ#. It is to connect to the system clock SATACLKREQ#/ (Native) chip. When active, request for SATA Clock running is asserted. When / GPIO35 tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An I/O (GP) external pull-up resistor is required. 2.8 Table 2-8. IDE Interface IDE Interface Signals (Sheet 1 of 2) Name DCS1# Type O Description IDE Device Chip Selects for 100 Range: For ATA command register block. This output signal is connected to the corresponding signal on the IDE connector. IDE Device Chip Select for 300 Range: For ATA control register block. This output signal is connected to the corresponding signal on the IDE connector. IDE Device Address: These output signals are connected to the corresponding signals on the IDE connector. They are used to indicate which byte in either the ATA command block or control block is being addressed. IDE Device Data: These signals directly drive the corresponding signals on the IDE connector. There is a weak internal pull-down resistor on DD7. DCS3# O DA[2:0] O DD[15:0] I/O 60 Intel (R) ICH7 Family Datasheet Signal Description Table 2-8. IDE Interface Signals (Sheet 2 of 2) Name Type Description IDE Device DMA Request: This input signal is directly driven from the DRQ signal on the IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on this signal. IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the IDE connector. DDACK# is asserted by the Intel(R) ICH7 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data onto the DD lines. Data is latched by the ICH7 on the deassertion edge of DIOR#. The IDE device is selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#). O Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH7 drives valid data on rising and falling edges of DWSTB. Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH7 deasserts RDMARDY# to pause burst data transfers. Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the DD lines. Data is latched by the IDE device on the deassertion edge of DIOW#. The IDE device is selected either by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge (DDAK#). Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst. I/O Channel Ready (PIO): This signal will keep the strobe active (DIOR# on reads, DIOW# on writes) longer than the minimum width. It adds wait-states to PIO transfers. I Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, ICH7 latches data on rising and falling edges of this signal from the disk. Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de-asserted by the disk to pause burst data transfers. DDREQ I DDACK# O DIOR# / (DWSTB / RDMARDY#) DIOW# / (DSTOP) O IORDY / (DRSTB / WDMARDY#) Intel (R) ICH7 Family Datasheet 61 Signal Description 2.9 Table 2-9. LPC Interface LPC Interface Signals Name LAD[3:0] / FWH[3:0] LFRAME# / FWH4 LDRQ0# LDRQ1# / GPIO23 (Desktop and Mobile only) I Type I/O O Description LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pullups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ1# may optionally be used as GPIO. 2.10 Interrupt Interface Table 2-10. Interrupt Signals Name SERIRQ Type I/O Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts. PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control register. I/OD In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. IDE Interrupt Request: This interrupt input is connected to the IDE drive. PIRQ[D:A]# (Desktop and Mobile only) I/OD PIRQ[H:E]# / GPIO[5:2] IDEIRQ I 62 Intel (R) ICH7 Family Datasheet Signal Description 2.11 USB Interface Table 2-11. USB Interface Signals Name Type Description Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI controller #1 or the EHCI controller. I/O NOTE: No external resistors are required on these signals. The Intel(R) ICH7 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to UHCI controller #2 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH7 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 4 and 5. These ports can be routed to UHCI controller #3 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH7 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 6 and 7. These ports can be routed to UHCI controller #4 or the EHCI controller. NOTE: No external resistors are required on these signals. The ICH7 integrates 15 k pull-downs and provides an output driver impedance of 45 which requires no external series resistor Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. OC[7:5]# may optionally be used as GPIOs. NOTE: OC[7:0]# are not 5 V tolerant. O USB Resistor Bias: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USB Resistor Bias Complement: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N I/O USBP4P, USBP4N, USBP5P, USBP5N I/O USBP6P, USBP6N, USBP7P, USBP7N I/O OC[4:0]# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31 USBRBIAS I USBRBIAS# I Intel (R) ICH7 Family Datasheet 63 Signal Description 2.12 Power Management Interface Table 2-12. Power Management Interface Signals (Sheet 1 of 3) Name Type Description Platform Reset: The Intel(R) ICH7 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The ICH7 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH7 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h). NOTE: PLTRST# is in the VccSus3_3 well. THRM# I Thermal Alarm: THRM# is an active low signal generated by external hardware to generate an SMI# or SCI. Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the ICH7 will immediately transition to a S5 state. The ICH7 will not wait for the processor stop grant cycle since the processor has overheated. S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. SLP_S4# O NOTE: This pin must be used to control the DRAM power to use the ICH7's DRAM power-cycling feature. Refer to Chapter 5.14.11.2 for details. SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. Power OK: When asserted, PWROK is an indication to the ICH7 that core power has been stable for 99 ms and that PCICLK has been stable for 1 ms. An exception to this rule is if the system is in S3HOT, in which PWROK may or may not stay asserted even though PCICLK may be inactive. PWROK can be driven asynchronously. When PWROK is negated, the ICH7 asserts PLTRST#. NOTE: PWROK must deassert for a minimum of three RTC clock periods for the ICH7 to fully reset the power and properly generate the PLTRST# output. Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. PLTRST# O THRMTRIP# I SLP_S3# O PWROK I PWRBTN# I RI# (Desktop and Mobile Only) I 64 Intel (R) ICH7 Family Datasheet Signal Description Table 2-12. Power Management Interface Signals (Sheet 2 of 3) Name Type Description System Reset: This pin forces an internal reset after being debounced. The ICH7 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms 2 ms for the SMBus to idle before forcing a reset on the system. Resume Well Reset: This signal is used for resetting the resume power plane logic. LAN Reset: When asserted, the internal LAN controller will be put into reset. This signal must be asserted for at least 10 ms after the resume well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in mobile) is valid. When deasserted, this signal is an indication that the resume (LAN for mobile) well power is stable. NOTE: LAN_RST# should be tied to RSMRST#. WAKE# MCH_SYNC# I I PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by components requesting wake up. MCH SYNC: This input is internally ANDed with the PWROK input. Connect to the ICH_SYNC# output of (G)MCH. Suspend Status: This signal is asserted by the ICH7 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface. Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock. VRM Power Good: This should be connected to be the processor's VRM Power Good signifying the VRM is stable. This signal is internally ANDed with the PWROK input. Bus Master Busy: This signal supports the C3 state. It provides an indication that a bus master device is busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes active in a C3 state, it is treated as a break event. I NOTE: This signal is internally synchronized using the PCICLK and a two-stage synchronizer. It does not need to meet any particular setup or hold time. NOTE: In desktop configurations, this signal pin is a GPIO. PCI Clock Run: This clock supports the PCI CLKRUN protocol. It connects to peripherals that need to request clock restart or prevention of clock stopping. Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is not needed, this signal can be configured as a GPIO. NOTE: Refered to as STPPCI# on Ultra Mobile. SYS_RESET# I RSMRST# I LAN_RST# (Desktop and Mobile Only) I SUS_STAT# / LPCPD# O SUSCLK O VRMPWRGD I BM_BUSY# (Mobile/Ultra Mobile Only) / GPIO0 (Desktop Only) CLKRUN# (Mobile/Ultra Mobile Only)/ GPIO32 (Desktop Only) STP_PCI# (Mobile/Ultra Mobile Only) / GPIO18 (Desktop Only) I/O O Intel (R) ICH7 Family Datasheet 65 Signal Description Table 2-12. Power Management Interface Signals (Sheet 3 of 3) Name STP_CPU# (Mobile/Ultra Mobile Only) / GPIO20 (Desktop Only) BATLOW# (Mobile/Ultra Mobile Only) / TP0 (Desktop Only) DPRSLPVR (Mobile/Ultra Mobile Only) / GPIO16 (Desktop Only) DPRSTP# (Mobile/Ultra Mobile Only) / TP1 (Desktop Only) Type Description Stop CPU Clock: This signal is an output to the external clock generator for it to turn off the processor clock. It is used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPIO. NOTE: Refered to as STPCPU# on Ultra Mobile. Battery Low: This signal is an input from battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3-S5 state. This signal can also be enabled to cause an SMI# when asserted. Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during the C4 state. When the signal is high, the voltage regulator outputs the lower "Deeper Sleep" voltage. When low (default), the voltage regulator outputs the higher "Normal" voltage. O I O O Deeper Stop: This is a copy of the DPRSLPVR and it is active low. 2.13 Processor Interface Table 2-13. Processor Interface Signals (Sheet 1 of 3) Name A20M# Type O Description Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The Intel(R) ICH7 can optionally assert the CPUSLP# signal when going to the S1 state. (Desktop Only) Reserved. (Mobile/Ultra Mobile Only) Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH7 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1). If FERR# is asserted, the ICH7 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. NOTE: FERR# can be used in some states for notification by the processor of pending interrupt events. This functionality is independent of the OIC register bit setting. CPUSLP# O FERR# I 66 Intel (R) ICH7 Family Datasheet Signal Description Table 2-13. Processor Interface Signals (Sheet 2 of 3) Name Type Description Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH7 coprocessor error reporting function is enabled in the OIC.CEN register (Chipset Config Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error register (I/O register F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error register is written, the IGNNE# signal is not asserted. Initialization: INIT# is asserted by the ICH7 for 16 PCI clocks to reset the processor. ICH7 can be configured to support processor Built In Self Test (BIST). Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended for Firmware Hub. CPU Interrupt: INTR is asserted by the ICH7 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH7 can generate an NMI when either SERR# is asserted or IOCHK# goes active via the SERIRQ# stream. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control register (I/O Register 61h). System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH7 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH7 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH7's other sources of INIT#. When the ICH7 detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The ICH7 will ignore RCIN# assertion during transitions to the S1, S3, S4, and S5 states. IGNNE# O INIT# INIT3_3V# (Desktop and Mobile Only) INTR O O O NMI O SMI# O STPCLK# O RCIN# I Intel (R) ICH7 Family Datasheet 67 Signal Description Table 2-13. Processor Interface Signals (Sheet 3 of 3) Name A20GATE Type I Description A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other chipsets. CPU Power Good: This signal should be connected to the processor's PWRGOOD input to indicate when the CPU power is valid. This is an output signal that represents a logical AND of the ICH7's PWROK and VRMPWRGD signals. This signal may optionally be configured as a GPIO. DPSLP# (Mobile/Ultra Mobile Only) / TP2 (Desktop Only) Deeper Sleep: DPSLP# is asserted by the ICH7 to the processor. When the signal is low, the processor enters the deep sleep state by gating off the processor core clock inside the processor. When the signal is high (default), the processor is not in the deep sleep state. CPUPWRGD / GPIO49 O O 2.14 SMBus Interface Table 2-14. SM Bus Interface Signals Name SMBDATA SMBCLK SMBALERT# / GPIO11 Type I/OD I/OD I Description SMBus Data: External pull-up resistor is required. SMBus Clock: External pull-up resistor is required. SMBus Alert: This signal is used to wake the system or generate SMI#. If not used for SMBALERT#, it can be used as a GPIO. 2.15 System Management Interface Table 2-15. System Management Interface Signals Name INTRUDER# SMLINK[1:0] (Desktop and Mobile Only) LINKALERT# (Desktop and Mobile Only) Type I Description Intruder Detect: This signal can be set to disable the system if the chasis is detected open. This signal's status is readable, so it can be used like a GPIO if the Intruder Detection is not needed. System Management Link: These signals provide a SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK0 corresponds to an SMBus clock signal, and SMLINK1 corresponds to an SMBus Data signal. SMLink Alert: This signal is an output of the integrated LAN and input to either the integrated ASF or an external management controller in order for the LAN's SMLINK slave to be serviced. I/OD I/OD 68 Intel (R) ICH7 Family Datasheet Signal Description 2.16 Real Time Clock Interface Name RTCX1 RTCX2 Type Special Special Description Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, RTCX2 should be left floating. Table 2-16. Real Time Clock Interface 2.17 Other Clocks Name CLK14 Type I Description Oscillator Clock: This clock signal is used for the 8254 timers. It runs at 14.31818 MHz. This clock is permitted to stop during S3 (or lower) states. 48 MHz Clock: This clock signal is used to run the USB controller. It runs at 48.000 MHz. This clock is permitted to stop during S3 (or lower) states. 100 MHz Differential Clock: These signals are used to run the SATA controller at 100 MHz. This clock is permitted to stop during S3/S4/S5 states. 100 MHz Differential Clock: These signals are used to run the Direct Media Interface. They run at 100 MHz. Table 2-17. Other Clocks CLK48 SATA_CLKP SATA_CLKN (Desktop and Mobile Only) DMI_CLKP, DMI_CLKN I I I Intel (R) ICH7 Family Datasheet 69 Signal Description 2.18 Miscellaneous Signals Name INTVRMEN (Desktop and Mobile Only) Type I Description Internal Voltage Regulator Enable: This signal enables the internal 1.05 V Suspend regulator when connected to VccRTC. When connected to Vss, the internal regulator is disabled Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See Section 2.24.1 for more details. There is a weak integrated pull-down resistor on SPKR pin. RTC Reset: When asserted, this signal resets register bits in the RTC well. RTCRST# (Desktop and Mobile Only) NOTES: 1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin. Table 2-18. Miscellaneous Signals SPKR O I TP0 (Desktop Only) / BATLOW# (Mobile/Ultra Mobile Only) TP1 (Desktop Only) / DPRSTP# (Mobile/Ultra Mobile Only) TP2 (Desktop Only) / DPSLP# (Mobile/Ultra Mobile Only) TP3 I Test Point 0: This signal must have an external pull-up to VccSus3_3. O Test Point 1: Route signal to a test point. O Test Point 2: Route signal to a test point. I/O Test Point 3: Route signal to a test point. 70 Intel (R) ICH7 Family Datasheet Signal Description 2.19 Note: AC '97/Intel(R) High Definition Audio Link AC `97 is not supported on Ultra Mobile. Table 2-19. AC '97/Intel(R) High Definition Audio Link Signals Name1,2 ACZ_RST# ACZ_SYNC Type O O (R) Description AC '97/Intel High Definition Audio Reset: This signal is the master hardware reset to external codec(s). AC '97/Intel High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync to the codec(s). It is also used to encode the stream number. AC '97 Bit Clock Input: This signal is a 12.288 MHz serial data clock generated by the external codec(s). This signal has an integrated pull-down resistor (see Note below). ACZ_BIT_CLK I/O Intel High Definition Audio Bit Clock Output: This signal is a 24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the Intel(R) ICH7). This signal has an integrated pulldown resistor so that ACZ_BIT_CLK doesn't float when an Intel High Definition Audio codec (or no codec) is connected but the signals are temporarily configured as AC '97. AC '97/Intel High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio. NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a functional strap. See Section 2.24.1 for more details. There is a weak integrated pull-down resistor on the ACZ_SDOUT pin. AC '97/Intel High Definition Audio Serial Data In [2:0]: These signals are serial TDM data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel(R) High Definition Audio. These signals have integrated pull-down resistors that are always enabled. High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active low signal. When deasserted, the external docking switch is in isolate mode. When asserted, the external docking switch electrically connects the Intel HD Audio dock signals to the corresponding Intel(R) ICH7 signals. This signal is shared with GPIO33. This signal defaults to GPIO33 mode after PLTRST# reset and will be in the high state after PLTRST# reset. BIOS is responsible for configuring GPIO33 to AZ_DOCK_EN# mode. High Definition Audio Dock Reset: This signal is a dedicated AZ_RST# signal for the codec(s) in the docking station. Aside from operating independently from the normal ACZ_RST# signal, it otherwise works similarly to the ACZ_RST# signal. This signal is shared with GPIO34. This signal defaults to GPIO34 mode after PLTRST# reset and will be in the low state after PLTRST# reset. BIOS is responsible for configuring GPIO34 to AZ_DOCK_RST# mode. ACZ_SDOUT O ACZ_SDIN[2:0] I AZ_DOCK_EN# (Mobile Only) / GPIO33 I/O AZ_DOCK_RST# (Mobile Only) / GPIO34 I/O 1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details. 2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode of the shared Intel High Definition Audio/AC `97 signals. When set to 0 AC `97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC `97 mode). NOTES: Intel (R) ICH7 Family Datasheet 71 Signal Description 2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) Table 2-20. Serial Peripheral Interface (SPI) Signals Name SPI_CS# SPI_MISO SPI_MOSI Type I/O I O Description SPI Chip Select: This chip select signal is also used as the SPI bus request signal. SPI Master IN Slave OUT: This signal is the data input pin for Intel(R) ICH7. SPI Master OUT Slave IN: This signal is the data output pin for ICH7. SPI Arbitration: SPI_ARB is the SPI arbitration signal used to arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet Controller when Shared Flash is implemented. SPI Clock: This signal is the SPI clock signal. During idle, the bus owner will drive the clock signal low. 17.86 MHz. SPI_ARB I SPI_CLK O 2.21 Intel(R) Quick Resume Technology (Intel(R) ICH7DH Only) Signal Name Type Description Intel(R) Quick Resume Technology Reserved: This signal is reserved and should be left as a no connect when Intel Quick Resume Technology is enabled. NOTE: This signal cannot be reused as a GPIO when Intel Quick Resume Technology is enabled. EL_STATE[1:0] / GPIO[28:27] I/O Intel Quick Resume Technology State: Intel Quick Resume Technology status signals that may optionally be used to drive front chassis indicators. See Section 5.26.3 for details. EL_RSVD / GPIO26 I/O 2.22 General Purpose I/O Signals Table 2-21. General Purpose I/O Signals (Sheet 1 of 3) Name1,2 GPIO49 GPIO48 GPIO[47:40] GPIO[39:38] (Desktop and Mobile Only) GPIO37 (Desktop and Mobile Only) Type I/O I/O N/A I/O Tolerance V_CPU_IO 3.3 V N/A 3.3 V Power Well V_CPU_IO Core N/A Core Default Native Native N/A GPI Description Multiplexed with CPUPWRGD Multiplexed with GNT4# Not implemented. Unmultiplexed. I/O 3.3 V Core GPI Multiplexed with SATA3GP. 72 Intel (R) ICH7 Family Datasheet Signal Description Table 2-21. General Purpose I/O Signals (Sheet 2 of 3) Name1,2 GPIO36 (Desktop and Mobile Only) GPIO35 (Desktop and Mobile Only) GPIO34 (Desktop and Mobile Only) GPIO33 (Desktop and Mobile Only) GPIO32 (Desktop Only) GPIO31 GPIO30 GPIO29 GPIO28 (Desktop and Mobile Only) GPIO27 (Desktop and Mobile Only) GPIO26 (Desktop and Mobile Only) GPIO25 (Desktop and Mobile Only) GPIO24 (Desktop and Mobile Only) GPIO23 (Desktop and Mobile Only) GPIO22 GPIO21 (Desktop and Mobile Only) GPIO20 (Desktop Only) Type Tolerance Power Well Core Default Description I/O 3.3 V GPI Multiplexed with SATA2GP. I/O 3.3 V Core GPO Multiplexed with SATACLKREQ#. Mobile Only: Multiplexed with AZ_DOCK_RST#. Desktop Only: Unmultiplexed. Mobile Only: Multiplexed with AZ_DOCK_EN#. Desktop Only: Unmultiplexed. Mobile/Ultra Mobile Only: this GPIO is not implemented and is used instead as CLKRUN#. Desktop Only: Unmultiplexed. Multiplexed with OC7# Multiplexed with OC6# Multiplexed with OC5# Intel(R) ICH7, ICH7R, and Mobile Only: Unmultiplexed. ICH7DH Only: Multiplexed with EL_STATE1 Intel(R) ICH7, ICH7R, and Mobile Only: Unmultiplexed. ICH7DH Only: Multiplexed with EL_STATE0 Intel(R) ICH7, ICH7R, and Mobile Only: Unmultiplexed. ICH7DH Only: Multiplexed with EL_RSVD Unmultiplexed. Unmultiplexed. Not cleared by CF9h reset event. Multiplexed with LDRQ1# Multiplexed with REQ4# Multiplexed with SATA0GP. Mobile/Ultra Mobile Only: GPIO is not implemented and is used instead as STP_CPU#. Desktop Only: Unmultiplexed. I/O 3.3 V Core GPO I/O 3.3 V Core GPO I/O I/O I/O I/O I/O 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Core Resume Resume Resume Resume GPO Native Native Native GPO I/O 3.3 V Resume GPO I/O 3.3 V Resume GPO I/O 3.3 V Resume GPO I/O 3.3 V Resume GPO I/O I/O I/O 3.3 V 3.3 V 3.3 V Core Core Core Native Native GPI I/O 3.3 V Core GPO Intel (R) ICH7 Family Datasheet 73 Signal Description Table 2-21. General Purpose I/O Signals (Sheet 3 of 3) Name1,2 GPIO19 (Desktop and Mobile Only) GPIO18 (Desktop Only) GPIO17 Type Tolerance Power Well Core Default Description I/O 3.3 V GPI Multiplexed with SATA1GP. Mobile/Ultra Mobile Only: GPIO is not implemented and is used instead as STP_PCI#. Desktop Only: Unmultiplexed. Multiplexed with GNT5#. Mobile/Ultra Mobile Only: Natively used as DPRSLPVR. Desktop Only: Unmultiplexed. Unmultiplexed. Multiplexed with SMBALERT# Unmultiplexed. Unmultiplexed. Multiplexed with PIRQ[H:E]#. Multiplexed with REQ5#. Mobile/Ultra Mobile Only: Multiplexed with BM_BUSY#. Desktop Only: Unmultiplexed I/O I/O 3.3 V 3.3 V Core Core GPO GPO Native (Mobile/ Ultra Mobile) / GPO (Desktop) GPI Native GPI GPI GPI GPI GPI GPIO16 I/O 3.3 V Core GPIO[15:12] GPIO11 GPIO[10:8] GPIO[7:6] GPIO[5:2] GPIO1 GPIO0 (Desktop Only) NOTES: I/O I/O I/O I/O I/OD I/O I/O 3.3 V 3.3 V 3.3 V 3.3 V 5V 5V 3.3 V Resume Resume Resume Core Core Core Core 1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. 2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down. 2.23 Power and Ground Table 2-22. Power and Ground Signals (Sheet 1 of 3) Name Vcc3_3 Vcc1_05 Vcc1_5_A Vcc1_5_B V5REF (Desktop and Mobile Only) Description These pins provide the 3.3 V supply for core well I/O buffers (22pins). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the 1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the reference for 5 V tolerance on core well inputs (2 pins). This power may be shut off in S3, S4, S5 or G3 states. 74 Intel (R) ICH7 Family Datasheet Signal Description Table 2-22. Power and Ground Signals (Sheet 2 of 3) Name V5REF1 (Ultra Mobile Only) V5REF2 (Ultra Mobile Only) Description These pins provide the reference for 5 V tolerance on core well inputs (1 pin). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the reference for 5 V tolerance on core well inputs (1 pin). This power may be shut off in S3, S4, S5 or G3 states. These pins provide the 3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations. These pins provide the 1.05 V supply for resume well logic (5 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations. This voltage may be generated internally (see Section 2.24.1 for strapping option). If generated internally, these pins should not be connected to an external supply. This pin provides the reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations. These pins provide the 3.3 V supply for LAN Connect interface buffers (4 pins). This is a separate power plane that may or may not be powered in S3-S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. NOTE: In Desktop mode these signals are added to the VccSus3_3 group. These pins provide the 1.05 V supply for LAN controller logic (2 pins). This is a separate power plane that may or may not be powered in S3-S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1. NOTE: This voltage will be generated internally if VccSus1_05 is generated internally (see Section 2.24.1 for strapping option). If generated internally, these pins should not be connected to an external supply. NOTE: In Desktop mode these signals are added to the VccSus1_05 group. This pin provides the suspend supply for Intel High Definition Audio (1 pins). This pin can be either 1.5 V or 3.3 V. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available in mobile/Ultra Mobile configurations. NOTE: In Desktop mode this signal is added to the VccSus3_3 group. VccHDA (Mobile/Ultra Mobile Only) This pin provides the core supply for Intel High Definition Audio (1 pin). This pin can be either 1.5 V or 3.3 V. This power may be shut off in S3, S4, S5 or G3 states. This plane must be on in S0 and S1. NOTE: In Desktop mode these signals are added to the Vcc3_3 group. VccSus3_3 VccSus1_05 V5REF_Sus VccLAN3_3 (Mobile Only) VccLAN1_05 (Mobile Only) VccSusHDA (Mobile/Ultra Mobile Only) Intel (R) ICH7 Family Datasheet 75 Signal Description Table 2-22. Power and Ground Signals (Sheet 3 of 3) Name Description This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not expected to be shut off unless the RTC battery is removed or completely drained. VccRTC NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an Intel(R) ICH7-based platform can be done by using a jumper on RTCRST# or GPI. VccUSBPLL (Desktop and Mobile Only) VccDMIPLL VccSATAPLL (Desktop and Mobile Only) V_CPU_IO Vss This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used. This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states. This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA not used. These pins are powered by the same supply as the processor I/O voltage (3 pins). This supply is used to drive the processor interface signals listed in Table 2-13. Grounds (194 pins). 2.24 2.24.1 Pin Straps Functional Straps The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled. Table 2-23. Functional Strap Definitions (Sheet 1 of 3) Signal Usage When Sampled Comment Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK. See Chapter 25 for XOR Chain functionality information. Rising Edge of PWROK When TP3 not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.34 for details. This signal has a weak internal pull-down. PCI Express Port Config bit 0 This signal has a weak internal pull-down. Rising Edge of PWROK Sets bit 0 of RPC.PC (Chipset Configuration Registers:Offset 224h). See Section 7.1.34 for details. This signal has a weak internal pull-down. NOTE: This signal should not be pulled high. ACZ_SDOUT XOR Chain Entrance / PCI Express* Port Config bit 1 ACZ_SYNC EE_CS (Desktop and Mobile Only) Reserved 76 Intel (R) ICH7 Family Datasheet Signal Description Table 2-23. Functional Strap Definitions (Sheet 2 of 3) Signal EE_DOUT (Desktop and Mobile Only) GNT2# Usage When Sampled Comment Reserved This signal has a weak internal pull-up. NOTE: This signal should not be pulled low. This signal has a weak internal pull-up. NOTE: This signal should not be pulled low. The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the "top-block swap" mode (Intel(R) ICH7 inverts A16 for all cycles targeting FWH BIOS space). The status of this strap is readable via the Top Swap bit (Chipset Configuration Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. This field determines the destination of accesses to the BIOS memory range. Signals have weak internal pull-ups. Also controllable via Boot BIOS Destination bit (Chipset Configuration Registers:Offset 3410h:bit 11:10) (GNT5# is MSB) 01 = SPI (Desktop and Mobile Only) 10 = PCI 11 = LPC Reserved GNT3# Top-Block Swap Override Rising Edge of PWROK GNT5# / GPIO17#, GNT4# / GPIO48 Boot BIOS Destination Selection Rising Edge of PWROK GPIO16 (Desktop Only) / DPRSLPVR (Mobile/Ultra Mobile Only) This signal has a weak internal pull-down. Reserved NOTE: This signal should not be pulled high. This signal has a weak internal pull-up.The internal pull-up is disabled within 100 ms after RSMRST# deasserts. DMI AC/DC Coupling Selection (Desktop Only) If the signal is sampled high, the DMI interface is strapped to operate in DC coupled mode (No coupling capacitors are required on DMI differential pairs). Rising Edge of RSMRST# If the signal is sampled low, the DMI interface is strapped to operate in AC coupled mode (Coupling capacitors are required on DMI differential pairs). NOTE: Board designer must ensure that DMI implementation matches the strap selection. NOTE: The signal must be held low at least 2 us after RSMRST# deassertion to enable AC coupled mode. GPIO25 INTVRMEN (Desktop and Mobile Only) Integrated VccSus1_05 VRM Enable/ Disable Always Enables integrated VccSus1_05 VRM when sampled high. Intel (R) ICH7 Family Datasheet 77 Signal Description Table 2-23. Functional Strap Definitions (Sheet 3 of 3) Signal LINKALERT# (Desktop and Mobile Only) REQ[4:1]# SATALED# (Desktop and Mobile Only) Reserved This signal requires an external pull-up resistor. Usage When Sampled Comment XOR Chain Selection Rising Edge of PWROK See Chapter 25 for functionality information. This signal has a weak internal pull-up enabled only when PLTRST# is asserted. NOTE: This signal should not be pulled low. The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (ICH7 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO REBOOT bit (Chipset Config Registers:Offset 3410h:bit 5). See Chapter 25 for functionality information. This signal has a weak internal pull-up. NOTE: This signal should not be pulled low unless using XOR Chain testing. Reserved SPKR No Reboot Rising Edge of PWROK TP3 XOR Chain Entrance Rising Edge of PWROK NOTE: See Section 3.1for full details on pull-up/pull-down resistors. 2.24.2 External RTC Circuitry To reduce RTC well power consumption, the ICH7 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-4 shows an example schematic recommended to ensure correct operation of the ICH7 RTC. Figure 2-4. Example External RTC Circuit VccSus3_3 Schottky Diodes 1 K 1 F (20% tolerance) VCCRTC RTCX2 20 K + - 32.768 kHz Xtal C1 15 pF (5% tolerance) R1 10 M RTCX1 C2 15 pF (5% tolerance) Vbatt 1 F (20% tolerance) RTCRST# NOTE: C1 and C2 depend on crystal load. 78 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States 3 3.1 Table 3-1. Intel(R) ICH7 Pin States Integrated Pull-Ups and Pull-Downs Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2) Signal ACZ_BIT_CLK, AC `97 (Desktop and Mobile Only) ACZ_RST#, AC `97 (Desktop and Mobile Only) ACZ_SDIN[2:0], AC `97 (Desktop and Mobile Only) ACZ_SDOUT, AC `97 (Desktop and Mobile Only) ACZ_SYNC, AC `97 (Desktop and Mobile Only) ACZ_BIT_CLK, Intel(R) High Definition Audio ACZ_RST#, Intel High Definition Audio ACZ_SDIN[2:0], Intel High Definition Audio ACZ_SDOUT, Intel High Definition Audio ACZ_SYNC, Intel High Definition Audio DD7 DDREQ DPRSLPVR / GPIO16 EE_CS (Desktop and Mobile Only) EE_DIN (Desktop and Mobile Only) EE_DOUT (Desktop and Mobile Only) GNT[1:0] GNT[3:2], GNT4# / GPIO48 GNT5# / GPIO17 GPIO25 LAD[3:0]# / FHW[3:0]# LAN_CLK (Desktop and Mobile Only) LAN_RXD[2:0] (Desktop and Mobile Only) LDRQ[0] LDRQ1 / GPIO23 PME# PWRBTN# SATALED# Resistor Pull-down Pull-down Pull-down Pull-down Pull-down Pull-Down None Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Nominal 20 k 20 k 20 k 20 k 20 k 20 k N/A 20 k 20 k 20 k 11.5 k 11.5 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k 100 k 20 k 20 k 20 k 20 k 20 k 15 k Notes 1, 2, 3 1, 2, 4 2, 4 2, 4, 5 2, 4, 5 2, 6, 7 2 2, 4 1, 2 2, 4 8 8 4, 9 10, 11 10 10 10, 12 10, 19 10, 13 10 14 15 10 10 10 10 16 Intel (R) ICH7 Family Datasheet 79 Intel(R) ICH7 Pin States Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2) Signal SPI_ARB (Desktop and Mobile Only) SPI_CLK (Desktop and Mobile Only) SPKR TP3 USB[7:0] [P,N] Resistor Pull-down Pull-down Pull-down Pull-up Pull-down Nominal 20 k 20 k 20 k 20 k 15 k Notes 10 10 4 17 18 NOTES: 1. The pull-down resistors on ACZ_BIT_CLK (AC `97) and ACZ_RST# are enabled when either: - The LSO bit (bit 3) in the AC '97 Global Control Register (D30:F2:2C) is set to 1, or - Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 2. The AC `97/Intel High Definition Audio Link signals may either all be configured to be an AC-Link or an Intel High Definition Audio Link. 3. Simulation data shows that these resistor values can range from 10 k to 20 k. 4. Simulation data shows that these resistor values can range from 9 k to 50 k. 5. The pull-down resistors on ACZ_SYNC (AC `97) and ACZ_SDOUT (AC `97) are enabled during reset and also enabled when either: - The LSO bit (bit 3) in the AC '97 Global Control Register (D30:F2:2C) is set to 1, or - Both Function 2 and Function 3 of Device 30 are disabled. Otherwise, the integrated Pull-down resistor is disabled. 6. Simulation data shows that these resistor values can range from 10 k to 40 k. 7. The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when in S3COLD. 8. Simulation data shows that these resistor values can range from 5.7 k to 28.3 k. 9. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. 10. Simulation data shows that these resistor values can range from 15 k to 35 k. 11. The pull-down on this signal is only enabled when LAN_RST# is asserted. 12. The internal pull-up is enabled only when the PCIRST# pin is driven low and the PWROK indication is high. 13. Internal pull-up is enabled during RSMRST# and is disabled within 100 ms after RSMRST# de-asserts. 14. Simulation data shows that these resistor values can range from 45 k to 170 k. 15. Simulation data shows that these resistor values can range from 15 k to 30 k. 16. Simulation data shows that these resistor values can range from 10 k to 20 k. The internal pull-up is only enabled only during PLTRST# assertion. 17. Simulation data shows that these resistor values can range from 10 kW to 30 kW. 18. Simulation data shows that these resistor values can range from 14.25 k to 24.8 k 19. The internal pull-up is enabled only when PCIRST# is low. 3.2 Table 3-2. IDE Integrated Series Termination Resistors Table 3-2 shows the ICH7 IDE signals that have integrated series termination resistors. IDE Series Termination Resistors Signal DD[15:0], DIOW#, DIOR#, DREQ, DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ Integrated Series Termination Resistor Value approximately 33 (See Note) NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 but can range from 21 to 75 . 80 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States 3.3 Output and I/O Signals Planes and States Table 3-3 and Table 3-4 show the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: "High-Z" "High" "Low" "Defined" "Undefined" "Running" "Off" Tri-state. ICH7 not driving the signal high or low. ICH7 is driving the signal to a logic 1 ICH7 is driving the signal to a logic 0 Driven to a level that is defined by the function (will be high or low) ICH7 is driving the signal, but the value is indeterminate. Clock is toggling or signal is transitioning because function not stopping The power plane is off, so ICH7 is not driving Note that the signal levels are the same in S4 and S5, except as noted. ICH7 suspend well signal states are indeterminate and undefined and may glitch, including input signals acting as outputs, prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. ICH7 core well signal states are indeterminate and undefined and may glitch, including input signals acting as outputs, prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion. Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet 1 of 5) Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S3COLD3 Signal Name S1 S4/S5 PCI Express* PETp[4:1], PETn[4:1] PETp[6:5], PETn[6:5] (Intel(R) ICH7R and ICH7DH Only) Core High High4 Defined Off Off DMI DMI[3:0]TXP, DMI[3:0]TXN Core High High4 Defined Off Off Intel (R) ICH7 Family Datasheet 81 Intel(R) ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet 2 of 5) Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 S3COLD3 Signal Name S1 S4/S5 PCI Bus AD[31:0] C/BE[3:0]# DEVSEL# FRAME# GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17 IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# Core Core Suspend Core Core Core Core Core Core Core Core Low Low High-Z High-Z High-Z with Internal Pullup High-Z Low Low High-Z High-Z High-Z Undefined Undefined High-Z High-Z High High-Z Undefined High High-Z High-Z High-Z Defined Defined High-Z High-Z High High-Z Defined High High-Z High-Z High-Z Off Off Off Off Off Off Off Low Off Off Off Off Off Off Off Off Off Off Low Off Off Off LPC Interface LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] Core Core High High High High High High Off Off Off Off LAN Connect and EEPROM Interface EE_CS EE_DOUT EE_SHCLK LAN_RSTSYNC LAN_TXD[2:0] Suspend Suspend Suspend Suspend Suspend Low High High-Z High Low Running High Running Low Low Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined IDE Interface DA[2:0] DCS1#, DCS3# DD[15:8], DD[6:0] DD[7] DDACK# DIOR#, DIOW# Core Core Core Core Core Core Undefined High High-Z Low High High Undefined High High-Z Low High High Undefined High High-Z Low High High Off Off Off Off Off Off Off Off Off Off Off Off SATA Interface SATA[3:0]TXP, SATA[3:0]TXN SATALED# Core Core High-Z High-Z High-Z High-Z Defined Defined Off Off Off Off 82 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet 3 of 5) Power Plane Core During PLTRST#1 / RSMRST#2 High-Z Immediately after PLTRST#1 / RSMRST#2 High-Z S3COLD3 Signal Name S1 S4/S5 SATARBIAS SATA3GP / GPIO37 SATA2GP / GPIO36 SATA1GP / GPIO19 SATA0GP / GPIO21 SATACLKREQ# / GPIO35 High-Z Off Off Core Input Input Driven Driven Driven Core Low Interrupts Low Defined Off Off PIRQ[A:D]#, PIRQ[H:E]# / GPIO[5:2] SERIRQ Core Core High-Z High-Z High-Z High-Z High-Z High-Z Off Off Off Off USB Interface USBP[7:0][P,N] USBRBIAS OC[7:5]# / GPIO[31:29] Suspend Suspend Suspend Low High-Z Input Low High-Z Input Low Defined Driven Low Defined Driven Low Defined Driven Power Management PLTRST# SLP_S3# SLP_S4# SLP_S5# SUS_STAT# SUSCLK Suspend Suspend Suspend Suspend Suspend Suspend Low Low Low Low Low Low Processor Interface A20M# CPUPWRGD / GPIO49 CPUSLP# IGNNE# INIT# INIT3_3V# INTR NMI SMI# Core Dependant on A20GATE Signal Defined High High High High See Note 6 See Note 6 High See Note 6 High7 High See Note 6 High High See Note 8 See Note 8 High High Off Off High High High High High High High High High High Running Low Low High High Low Low Low Low Low5 Low Core Core Core Core Core Core Core Core High Defined High High High Low Low High Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Intel (R) ICH7 Family Datasheet 83 Intel(R) ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet 4 of 5) Power Plane Core During PLTRST#1 / RSMRST#2 High Immediately after PLTRST#1 / RSMRST#2 High S3COLD3 Signal Name S1 S4/S5 STPCLK# Low Off Off SMBus Interface SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined System Management Interface SMLINK[1:0] LINKALERT# Suspend Suspend High-Z High-Z High-Z High-Z Defined Defined Defined Defined Defined Defined Miscellaneous Signals SPKR Core High-Z with Internal Pulldown Low Defined Off Off AC '97 Interface ACZ_RST# ACZ_SDOUT ACZ_SYNC Suspend Core Core Low Low Low Low Running Running Low Low Low Low Off Off Low Off Off Intel(R) High Definition Audio Interface ACZ_RST# ACZ_SDOUT Suspend Core Low High-Z with Internal Pulldown High-Z with Internal Pulldown High-Z with Internal Pulldown Low9 Running Running Low Low Off Low Off ACZ_SYNC Core Running Low Off Off ACZ_BIT_CLK Core Low9 Low Off Off Unmultiplexed GPIO Signals GPIO[7:6, 0] GPIO[15:12,10:8] GPIO16 GPIO18 GPIO20 GPIO24 GPIO25 GPIO[28:26] GPIO[33:32] GPIO34 Core Suspend Core Core Core Suspend Suspend Suspend Core Core Input Input Low High High No Change High Low High Low Input Input Low See Note 10 High No Change High11 Low High Low Driven Driven Defined Defined Defined Defined Defined Defined Defined Defined Off Driven Off Off Off Defined Defined Defined Off Off Off Driven Off Off Off Defined Defined Defined Off Off 84 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only Configurations (Sheet 5 of 5) Power Plane Core During PLTRST#1 / RSMRST#2 Input Immediately after PLTRST#1 / RSMRST#2 Input S3COLD3 Signal Name S1 S4/S5 GPIO[39:38] Driven Off Off SPI Interface SPI_CS# SPI_MOSI SPI_CLK Suspend Suspend Suspend High High Low High High Low High High Low High High Low High High Low Intel(R) Quick Resume Technology Interface (ICH7DH Only) EL_RSVD / GPIO26 EL_STATE[1:0] / GPIO[28:27] Suspend Suspend Low Low Low Low Defined Defined Defined Defined Defined Defined NOTES: 1. The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after PLTRST#. 2. The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately after RSMRST#. 3. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the ICH7 is in the S3HOT state. 4. On the ICH7, PETp/n[4:1] are high until port is enabled by software. On the ICH7R and ICH7DH, PETp/n[6:1] are high until port is enabled by software. 5. SLP_S5# signals will be high in the S4 state. 6. ICH7 drives these signals High after the processor Reset. 7. CPUPWRGD represents a logical AND of the ICH7's VRMPWRGD and PWROK signals, and thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 8. ICH7 drives these signals Low before PWROK rising and Low after the processor Reset. 9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. 10. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset 11. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the deassertion of the RSMRST# pin. Intel (R) ICH7 Family Datasheet 85 Intel(R) ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet 1 of 4) Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 C3/C4 S1 S3COLD3 S4/ S5 Signal Name PCI Express* (Mobile Only) PETp[6:1], PETn[6:1] Core High High4 DMI DMI[3:0]TXP, DMI[3:0]TXN Core High High4 PCI Bus AD[31:0] C/BE[3:0]# CLKRUN# DEVSEL# FRAME# GNT[3:0]# GNT4# / GPIO48 GNT5# / GPIO17 IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# Core Core Suspend Core Core Core Core Core Core Core Core Core Low Low Low High-Z High-Z High with Internal Pullups High-Z Low Low High-Z High-Z High-Z Undefined Undefined Low High-Z High-Z High High-Z Undefined High High-Z High-Z High-Z LPC Interface LAD[3:0] / FWH[3:0] LFRAME# / FWH[4] Core Core High High High High High High High High Off Off Off Off Defined Defined Defined High-Z High-Z High High-Z Defined High High-Z High-Z High-Z High-Z High-Z High High-Z Defined High High-Z High-Z High-Z Defined Defined Off Off Off Off Off Off Off Off Low Off Off Off Off Off Off Off Off Off Off Off Low Off Off Off Defined Defined Off Off Defined Defined Off Off LAN Connect and EEPROM Interface (Mobile Only) EE_CS EE_DOUT EE_SHCLK LAN_RSTSYNC LAN_TXD[2:0] LAN LAN LAN LAN LAN Low High High-Z High Low Running High Running Low Low IDE Interface DA[2:0] DCS1#, DCS3# DD[15:8], DD[6:0] Core Core Core Undefined High High-Z Undefined High High-Z Undefine d High Defined Undefine d High High-Z Off Off Off Off Off Off Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 86 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet 2 of 4) Power Plane Core Core Core During PLTRST#1 / RSMRST#2 Low High High Immediately after PLTRST#1 / RSMRST#2 Low High High C3/C4 S1 S3COLD3 Off Off Off S4/ S5 Off Off Off Signal Name DD[7] DDACK# DIOR#, DIOW# Defined High High Low High High SATA Interface (Mobile Only) SATA[0]TXP, SATA[0]TXN SATA[2]TXP, SATA[2]TXN SATALED# SATARBIAS SATA2GP / GPIO36 SATA0GP / GPIO21 SATACLKREQ# / GPIO35 Core High-Z High-Z Defined Defined Off Off Core Core Core Core High-Z High-Z Input Low High-Z High-Z Input Low Interrupts Defined Defined Driven Defined Defined Defined Driven Defined Off Off Driven Off Off Off Off PIRQ[A:D]#, PIRQ[H:E]# / GPIO[5:2] SERIRQ Core Core High-Z High-Z High-Z High-Z USB Interface USBP[7:0][P,N] USBRBIAS OC[7:5]# / GPIO[31:29] Suspend Suspend Suspend Low High-Z Input Low High-Z Input Low Defined Driven Low Defined Driven Low Defined Driven Low Define d Driven Defined Running High-Z High-Z Off Off Off Off Power Management PLTRST# SLP_S3# SLP_S4# SLP_S5# STP_PCI# STP_CPU# SUS_STAT# DPRSLPVR DPRSTP# SUSCLK Suspend Suspend Suspend Suspend Core Core Suspend Core Core Suspend Low Low Low Low High High Low Low High Low High High High High High High High Low High High High High High Defined Low High Low/ High7 Low/ High7 High High High High High High High High High Running Low Low High High Low Low Low Off Off Low Low Low Low6 Low Low Low Off Off Intel (R) ICH7 Family Datasheet 87 Intel(R) ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet 3 of 4) Power Plane During PLTRST#1 / RSMRST#2 Immediately after PLTRST#1 / RSMRST#2 C3/C4 S1 S3COLD3 S4/ S5 Signal Name Processor Interface A20M# CPUPWRGD / GPIO49 IGNNE# INIT# INIT3_3V# INTR NMI SMI# STPCLK# DPSLP# Core Core Core Core Core Core Core Core Core Core Dependant on A20GATE Signal See Note 9 High High High See Note 10 See Note 10 High High High See Note 8 High See Note 8 High High See Note 10 See Note 10 High High High SMBus Interface SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined Define d Defined High High High High Defined Defined Defined Low High/Low High High High High High Low Low High Low High Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off System Management Interface SMLINK[1:0] LINKALERT# Suspend Suspend High-Z High-Z High-Z High-Z Defined Defined Defined Defined Defined Defined Define d Define d Miscellaneous Signals SPKR Core High-Z with Internal Pulldown Low Defined Defined Off Off AC '97 Interface (Mobile Only) ACZ_RST# ACZ_SDOUT ACZ_SYNC Suspend Core Core Low Low Low Low Running Running High Running Running Cold Reset Bit (High) Low Low Low Off Off Low Off Off Intel(R) High Definition Audio Interface ACZ_RST# ACZ_SDOUT Suspend Core Low High-Z with Internal Pulldown High-Z with Internal Pulldown Low11 Running High Running TBD Low Low Off Low Off ACZ_SYNC Core Running Running Low Off Off 88 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only Configurations (Sheet 4 of 4) Power Plane During PLTRST#1 / RSMRST#2 High-Z with Internal Pulldown Low High Immediately after PLTRST#1 / RSMRST#2 Low11 Low11 High C3/C4 S1 S3COLD3 S4/ S5 Signal Name ACZ_BIT_CLK AZ_DOCK_RST# / GPIO34 AZ_DOCK_EN# / GPIO33 Core Core Core Running Defined Defined Low Defined Defined Off Off Off Off Off Off Unmultiplexed GPIO Signals GPIO[7:6] GPIO[15:12,10:8] GPIO18 GPIO19 GPIO24 GPIO25 GPIO[28:26] GPIO[39:37] Core Suspend Core Core Suspend Suspend Suspend Core Input Input High Input No Change High Low Input Input Input See Note 12 Input No Change High13 Low Input Driven Driven Driven Driven Defined Defined Defined Driven Driven Driven Driven Driven Defined Defined Defined Driven Off Driven Off Off Defined Defined Defined Off Off Driven Off Off Define d Define d Define d Off SPI Interface (Mobile Only) SPI_CS# SPI_MOSI SPI_ARB SPI_CLK Suspend Suspend Suspend Suspend High High Low Low High High Low Low High High Low Low High High Low Low High High Low Low High High Low Low NOTES: 1. The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#. 2. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#. 3. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the Intel(R) ICH7 is in the S3HOT state. 4. PETp/n[6:1] high until port is enabled by software. 5. LAN Connect and EEPROM signals will either be "Defined" or "Off" in S3-S5 states depending upon whether or not the LAN power planes are active. 6. SLP_S5# signals will be high in the S4 state. 7. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is disabled. 8. ICH7 drives these signals High after the processor Reset. 9. CPUPWRGD is an output that represents a logical AND of the Intel(R) ICH7's VRMPWRGD and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High. 10. IICH7 drives these signals Low before PWROK rising and Low after the processor Reset. Intel (R) ICH7 Family Datasheet 89 Intel(R) ICH7 Pin States 11. 12. 13. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be Running. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset GPIO25 transitions from pulled high internally to actively driven within 100 ms of the deassertion of the RSMRST# pin. 3.4 Power Planes for Input Signals Table 3-5 and Table 3-6 show the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks ICH7 suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion. ICH7 core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion. Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3) Signal Name A20GATE ACZ_BIT_CLK (AC `97 Mode) ACZ_SDIN[2:0] (AC `97 Mode) ACZ_SDIN[2:0] (Intel(R) High Definition Audio Mode) CLK14 CLK48 DDREQ DMI_CLKP, DMI_CLKN EE_DIN FERR# PERp[4:1], PERn[4:1] PERp[6:5], PERn[6:5] (Intel(R) ICH7R and ICH7DH Only) DMI[3:0]RXP, DMI[3:0]RXN IDEIRQ INTRUDER# Core PCI Express* Device Driven Driven Driven Power Well Core Core Suspend Suspend Core Core Core Core Suspend Core Driver During Reset External Microcontroller AC '97 Codec AC '97 Codec Intel(R) High Definition Audio Codec Clock Generator Clock Generator IDE Device Clock Generator EEPROM Component Processor S1 Static Low Low Low Running Running Static Running Driven Static S3COLD1 Low Low Low Low Low Low Low Low Driven Low S4/S5 Low Low Low Low Low Low Low Low Driven Low Core Core RTC (G)MCH IDE External Switch Driven Static Driven Low Low Driven Low Low Driven 90 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 2 of 3) Signal Name INTVRMEN IORDY LAN_CLK LAN_RST# LAN_RXD[2:0] LDRQ0# LDRQ1# / GPIO232 MCH_SYNC# OC[7:0]# PCICLK PME# PWRBTN# PWROK RCIN# REQ[3:0]#, REQ4# / GPIO222 REQ5# / GPIO122 RI# RSMRST# RTCRST# SATA_CLKP, SATA_CLKN SATA[3:0]RXP, SATA[3:0]RXN SATARBIAS# SATA[3:0]GP / GPIO[31:29,26]2 SERR# SMBALERT# / GPIO11 SYS_RESET# THRM# THRMTRIP# TP0 TP3 USBRBIAS# VRMPWRGD 2 Power Well RTC Core Suspend Suspend Suspend Core Core Core Suspend Core Suspend Suspend RTC Core Core Suspend RTC RTC Core Core Core Core Core Suspend Suspend Core Core Suspend Suspend Suspend Core Driver During Reset External Pull-up or Pull-down IDE Device LAN Connect Component External RC Circuit LAN Connect Component LPC Devices LPC Devices (G)MCH External Pull-ups Clock Generator Internal Pull-up Internal Pull-up System Power Supply External Microcontroller PCI Master Serial Port Buffer External RC Circuit External RC Circuit Clock Generator SATA Drive External Pull-down External Device or External Pull-up/Pulldown PCI Bus Peripherals External Pull-up External Circuit Thermal Sensor Thermal Sensor External Pull-up Internal Pull-up External Pull-down Processor Voltage Regulator S1 Driven Static Driven High Driven High High Driven Driven Running Driven Driven Driven High Driven Driven High High Running Driven Driven Driven High Driven Driven Driven Driven High High Driven High S3COLD1 Driven Low Driven High Driven Low Low Low Driven Low Driven Driven Low Low Low Driven High High Low Driven Driven Driven Low Driven Driven Low Low High High Driven Low S4/S5 Driven Low Driven High Driven Low Low Low Driven Low Driven Driven Low Low Low Driven High High Low Driven Driven Driven Low Driven Driven Low Low High High Driven Low Intel (R) ICH7 Family Datasheet 91 Intel(R) ICH7 Pin States Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 3 of 3) Signal Name WAKE# SPI_MISO SPI_ARB Power Well Suspend Suspend Suspend Driver During Reset External Pull-up External Pull-up Internal Pull-down S1 Driven Driven Low S3COLD1 Driven Driven Low S4/S5 Driven Driven Low NOTES: 1. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the ICH7 is in the S3HOT state. 2. These signals can be configured as outputs in GPIO mode. Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations (Sheet 1 of 3) Signal Name A20GATE ACZ_BIT_CLK (AC `97 mode) (Mobile Only) ACZ_SDIN[2:0] (AC `97 mode) (Mobile Only) Power Well Core Driver During Reset External Microcontroller AC '97 Codec C3/C4 Static S1 Static S3COLD1 Low S4/S5 Low Core Driven Low Low Low Suspend AC '97 Codec Driven Low Low Low ACZ_SDIN[2:0] (Intel(R) High Definition Audio Mode) BM_BUSY# / GPIO01 BATLOW# CLK14 CLK48 DDREQ DMI_CLKP DMI_CLKN EE_DIN (Mobile Only) FERR# PERp[6:1], PERn[6:1] (Mobile Only) DMI[3:0]RXP, DMI[3:0]RXN IDEIRQ INTRUDER# INTVRMEN (Mobile Only) Suspend Intel(R) High Definition Audio Codec Graphics Component [(G)MCH] Power Supply Clock Generator Clock Generator IDE Device Clock Generator EEPROM Component Processor PCI Express* Device Driven Low Low Low Core Suspend Core Core Core Core LAN Core Core Driven High Running Running Driven Running Driven Static Driven High High Running Running Static Running Driven Static Driven Low High Low Low Low Low Note 2 Low Driven Low High Low Low Low Low Note 2 Low Driven Core Core RTC RTC (G)MCH IDE External Switch External Pull-up or Pulldown Driven Driven Driven Driven Driven Static Driven Driven Low Low Driven Driven Low Low Driven Driven 92 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 Pin States Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations (Sheet 2 of 3) Signal Name IORDY LAN_CLK (Mobile Only) LAN_RST# (Mobile Only) LAN_RXD[2:0] (Mobile Only) LDRQ0# LDRQ1# / GPIO233 MCH_SYNC# OC[7:0]# PCICLK PME# PWRBTN# PWROK RCIN# REQ[3:0]#, Power Well Core LAN Suspend LAN Core Core Core Suspend Core Suspend Suspend RTC Core Driver During Reset IDE Device LAN Connect Component Power Supply LAN Connect Component LPC Devices LPC Devices (G)MCH External Pull-ups Clock Generator Internal Pull-up Internal Pull-up System Power Supply External Microcontroller PCI Master Serial Port Buffer External RC Circuit External RC Circuit Clock Generator C3/C4 Static Driven High Driven Driven Driven Driven Driven Running Driven Driven Driven High S1 Static Driven High Driven High High Driven Driven Running Driven Driven Driven High S3COLD1 Low Note 2 Static Note 2 Low Low Low Driven Low Driven Driven Low Low S4/S5 Low Note 2 Static Note 2 Low Low Low Driven Low Driven Driven Low Low REQ4# / GPIO223 REQ5# / GPIO13 RI# RSMRST# RTCRST# SATA_CLKP, SATA_CLKN (Mobile Only) SATA[0]RXP, SATA[0]RXN SATA[2]RXP, SATA[2]RXN (Mobile Only) SATARBIAS# (Mobile Only) SATA[2,0]GP (Mobile Only) SERR# SMBALERT# / GPIO113 SYS_RESET# THRM# Core Suspend RTC RTC Core Driven Driven High High Running Driven Driven High High Running Low Driven High High Low Low Driven High High Low Core SATA Drive Driven Driven Driven Driven Core External Pull-Down External Device or External Pull-up/Pulldown PCI Bus Peripherals External Pull-up External Circuit Thermal Sensor Driven Driven Driven Driven Core Core Suspend Suspend Core Driven Driven Driven Driven Driven Driven High Driven Driven Driven Driven Low Driven Driven Low Driven Low Driven Driven Low Intel (R) ICH7 Family Datasheet 93 Intel(R) ICH7 Pin States Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations (Sheet 3 of 3) Signal Name THRMTRIP# TP3 USBRBIAS# VRMPWRGD WAKE# SPI_MISO (Mobile Only) SPI_ARB (Mobile Only) Power Well Core Suspend Suspend Core Suspend Suspend Suspend Driver During Reset Thermal Sensor Internal Pull-up External Pull-down Processor Voltage Regulator External Pull-up External Pull-up Internal Pull-down C3/C4 Driven High Driven Driven Driven Driven Low S1 Driven High Driven Driven Driven Driven Low S3COLD1 Low High Driven Low Driven Driven Low S4/S5 Low High Driven Low Driven Driven Low NOTES: 1. In S3HOT, signal states are platform implementation specific, as some external components and interfaces may be powered when the Intel(R) ICH7 is in the S3HOT state. 2. LAN Connect and EEPROM signals will either be "Driven" or "Low" in S3-S5 states depending upon whether or not the LAN power planes are active. 3. These signals can be configured as outputs in GPIO mode. 94 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 and System Clock Domains 4 Intel(R) ICH7 and System Clock Domains Table 4-1 shows the system clock domains. Figure 4-1 and Figure 4-2 show the assumed connection of the various system components, including the clock generator in desktop and mobile/ultra mobile systems. For complete details of the system clocking solution, refer to the system's clock generator component specification. Table 4-1. Intel(R) ICH7 and System Clock Domains Clock Domain Intel(R) ICH7 SATA_CLKP, SATA_CLKN (Desktop and Mobile only) ICH7 DMI_CLKP, DMI_CLKN Frequency Source Usage 100 MHz Main Clock Generator Differential clock pair used for SATA. 100 MHz Main Clock Generator Differential clock pair used for DMI. Free-running PCI Clock to ICH7. This clock remains on during S0 and S1 (in desktop) state, and is expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ultra mobile configurations. PCI Bus, LPC I/F. These only go to external PCI and LPC devices. Will stop based on CLKRUN# (and STP_PCI#) in mobile/ultra mobile configurations. Super I/O, USB controllers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ultra mobile configurations. Used for ACPI timer and Multimedia Timers. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile/ ultra mobile configurations. AC-link. Generated by AC '97 Codec. Can be shut by codec in D3. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. NOTE: For use only in AC `97 mode. Generated by the LAN Connect component. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. Generated by the LAN Connect component. Expected to be shut off during S3 or below in desktop configurations or S1 or below in mobile configurations. ICH7 PCICLK 33 MHz Main Clock Generator System PCI 33 MHz Main Clock Generator ICH7 CLK48 48.000 MHz Main Clock Generator ICH7 CLK14 14.31818 MHz Main Clock Generator ICH7 ACZ_BIT_CLK (Desktop and Mobile only) LAN_CLK (Desktop and Mobile only) SPI_CLK (Desktop and Mobile Only) 12.288 MHz AC '97 Codec 5 to 50 MHz LAN Connect Component 17.86 MHz ICH Intel (R) ICH7 Family Datasheet 95 Intel(R) ICH7 and System Clock Domains Figure 4-1. Desktop Only Conceptual System Clock Diagram PCI Clocks (33 MHz) 14.31818 MHz 48.000 MHz 100 MHz Diff.Pair SATA 100 MHzDiff. Pair DMI 100 MHz Diff. Pair 50 MHz 12.288 MHz 24 MHz 32 kHz XTAL SUSCLK# (32 kHz) 1 to 6 Differential ClockFan OutDev ice 33 MHz 14.31818 MHz 48.000 MHz Clock Gen. Intel (R) ICH7 PCI Express 100 MHz Diff. Pairs LAN Connect AC '97 Codec(s) HighDefinitionAudioCodec(s) Figure 4-2. Mobile Only Conceptual Clock Diagram 33 MHz 14.31818 MHz 48.000 MHz STP_CPU# STP_PCI# 100 MHz Diff. Pair Clock Gen. PCI Clocks (33 MHz) 14.31818 MHz 48 MHz Intel(R) ICH7-M SATA 100 MHz Diff. Pair DMI 100 MHz Diff. Pair 50 MHz 12.288 MHz 32 kHz XTAL SUSCLK# (32 kHz) 1 to 6 Differential Clock Fan Out Device PCI Express 100 MHz Diff. Pairs LAN Connect AC '97 Codec(s) High Definition Audio Codec(s) 24 MHz 96 Intel (R) ICH7 Family Datasheet Intel(R) ICH7 and System Clock Domains Figure 4-3. Ultra Mobile Only Conceptual Clock Diagram 33 MHz 14.31818 MHz 48.000 MHz STP_CPU# Intel(R) ICH7-U STP_PCI# Clock Generator PCI Clocks (33 MHz) 14.31818 MHz 48 MHz DMI 100 MHz Diff Pair 24 MHz High Definition Audio Codec(s) 32 kHz XTAL SUSCLK# (32 kHz) Intel (R) ICH7 Family Datasheet 97 Intel(R) ICH7 and System Clock Domains 98 Intel (R) ICH7 Family Datasheet Functional Description 5 5.1 Functional Description This chapter describes the functions and interfaces of the ICH7 family. PCI-to-PCI Bridge (D30:F0) The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ICH7 implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed. Direct Media Interface (DMI) is the chip-to-chip connection between the Memory Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (i.e., the ICH7 and (G)MCH). Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Config Registers (Section 7). 5.1.1 PCI Bus Interface The ICH7 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH7 requests. 5.1.2 PCI Bridge As an Initiator The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the following cycle types: Table 5-1. PCI Bridge Initiator Cycle Types Command I/O Read/Write Memory Read/Write Configuration Read/Write Special Cycles C/BE# 2h/3h 6h/7h Ah/Bh 1h Notes Non-posted Writes are posted Non-posted Posted 5.1.2.1 Memory Reads and Writes The bridge bursts memory writes on PCI that are received as a single packet from DMI. Intel (R) ICH7 Family Datasheet 99 Functional Description 5.1.2.2 I/O Reads and Writes The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.3 Configuration Reads and Writes The bridge generates single DW configuration read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.4 Locked Cycles The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked. If a locked read results in a target or master abort, the lock is not established (as per the PCI Local Bus Specification). Agents north of the ICH7 must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion. 5.1.2.5 Target / Master Aborts When a cycle initiated by the bridge is master/target aborted, the bridge will not reattempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort. 5.1.2.6 Secondary Master Latency Timer The bridge implements a Master Latency Timer via the SLT register which, upon expiration, causes the de-assertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus. 5.1.2.7 Dual Address Cycle (DAC) The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB. 100 Intel (R) ICH7 Family Datasheet Functional Description 5.1.2.8 Memory and I/O Decode to PCI The PCI bridge in the ICH7 is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface: * The PCI bridge will positively decode any memory/IO address within its window registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows. * The PCI bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set. * The PCI bridge will subtractively decode any 16-bit I/O address not claimed by another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set * If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively forward from primary to secondary called out ranges in the IO window per PCI Local Bus Specification (I/O transactions addressing the last 768 bytes in each, 1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively assuming the above rules. * If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively forward from primary to secondary I/O and memory ranges as called out in the PCI Bridge Specification, assuming the above rules are met. 5.1.3 Parity Error Detection and Generation PCI parity errors can be detected and reported. The following behavioral rules apply: * When a parity error is detected on PCI, the bridge sets the SECSTS.DPE (D30:F0:Offset 1Eh:bit 15). * If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD (D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#. -- During a write cycle, the PERR# signal is active, or -- A data parity error is detected while performing a read cycle * If an address or command parity error is detected on PCI and PCICMD.SEE (D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1) are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and generate an internal SERR#. * If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is set, the bridge will generate an internal SERR# * When bad parity is detected from DMI, bad parity will be driven on all data the bridge. * When an address parity error is detected on PCI, the PCI bridge will not claim the cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction. 5.1.4 PCIRST# The PCIRST# pin is generated under two conditions: * PLTRST# active * BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but not other agents in the system. Intel (R) ICH7 Family Datasheet 101 Functional Description 5.1.5 Peer Cycles The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and configuration cycle types. Peer cycles are only allowed through VC0, and are enabled with the following bits: * BPC.PDE (D30:F0:Offset 4Ch:bit 2) - Memory and IO cycles * BPC.CDE (D30:F0:Offset 4Ch:bit 1) - Configuration cycles When enabled for peer for one of the above cycle types, the PCI bridge will perform a peer decode to see if a peer agent can receive the cycle. When not enabled, memory cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles are not claimed. Configuration cycles have special considerations. Under the PCI Local Bus Specification, these cycles are not allowed to be forwarded upstream through a bridge. However, to enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are allowed into the part. The address format of the type 1 cycle is slightly different from a standard PCI configuration cycle to allow addressing of extended PCI space. The format is as follows: Table 5-2. Type 1 Address Format Bits 31:27 26:24 23:16 15:11 10:8 7:2 1 0 Definition Reserved (same as the PCI Local Bus Specification) Extended Configuration Address - allows addressing of up to 4K. These bits are combined with bits 7:2 to get the full register. Bus Number (same as the PCI Local Bus Specification) Device Number (same as the PCI Local Bus Specification) Function Number (same as the PCI Local Bus Specification) Register (same as the PCI Local Bus Specification) 0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded. Note: The ICH7's AC '97, IDE and USB controllers cannot perform peer-to-peer traffic. 5.1.6 PCI-to-PCI Bridge Model From a software perspective, the ICH7 contains a PCI-to-PCI bridge. This bridge connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH7 can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics aperture ranges in the Host controller. Note: All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure to do so may cause undefined results. 102 Intel (R) ICH7 Family Datasheet Functional Description 5.1.7 IDSEL to Device Number Mapping When addressing devices on the external PCI bus (with the PCI slots), the ICH7 asserts one address signal as an IDSEL. When accessing device 0, the ICH7 asserts AD16. When accessing Device 1, the ICH7 asserts AD17. This mapping continues all the way up to device 15 where the ICH7 asserts AD31. Note that the ICH7's internal functions (AC '97 on Desktop/Mobile, Intel High Definition Audio, IDE, USB, SATA on Desktop/ Mobile and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus. The integrated LAN controller (Desktop and Mobile Only) is Device 8 on the ICH7's PCI bus, and hence it uses AD24 for IDSEL. 5.1.8 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based "configuration space" that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the ICH7. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration space, Mechanism 1 and Mechanism 2. The ICH7 only supports Mechanism 1. Warning: Configuration writes to internal devices, when the devices are disabled, are invalid and may cause undefined results. 5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) There are four root ports available in ICH7, with select ICH7 components (ICH7R, ICH7DH, and ICH7-M DH) having six root ports adding port 5 and port 6 (see Section 1.2). These all reside in device 28, and take function 0 - 5. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and port 6 is function 5. Optionally, PCI Express ports 1-4 can be configured as a single one x4 port identified as port 1. This is accomplished by placing external pull-up resistors on ACZ_SDOUT and ACZ_SYNC. When these signals are sampled high on PWROK assertion, this will be registered in the Port Configuration field of the Root Port Configuration Register and the corresponding ports will be configured as one x4 port. 5.2.1 Interrupt Generation The root port generates interrupts on behalf of Hot-Plug and power management events, when enabled. These interrupts can either be pin based, or can be MSIs, when enabled. When an interrupt is generated via the legacy pin, the pin is internally routed to the ICH7 interrupt controllers. The pin that is driven is based upon the setting of the chipset configuration registers. Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers. Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table "bits" refers to the Hot-Plug and PME interrupt bits. Intel (R) ICH7 Family Datasheet 103 Functional Description Table 5-3. MSI vs. PCI IRQ Actions Interrupt Register All bits 0 One or more bits set to 1 One or more bits set to 1, new bit gets set to 1 One or more bits set to 1, software clears some (but not all) bits One or more bits set to 1, software clears all bits Software clears one or more bits, and one or more bits are set on the same clock WireMode Action Wire inactive Wire active Wire active Wire active Wire inactive Wire active MSI Action No action Send message Send message Send message No action Send message 5.2.2 5.2.2.1 Power Management S3/S4/S5 Support Software initiates the transition to S3/S4/S5 by performing an IO write to the Power Management Control register in the ICH7. After the IO write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on it's downstream link. The device attached to the link will eventually respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the ICH7 root ports links are in the L2/L3 Ready state, the ICH7 power management control logic will proceed with the entry into S3/S4/S5. Prior to entering S3, software is required to put each device into D3HOT. When a device is put into D3HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1 DLLP. Thus, under normal operating conditions when the root ports sends the PME_Turn_Off message, the link will be in state L1. However, when the root port is instructed to send the PME_Turn_Off message, it will send it whether or not the link was in L1. Endpoints attached to the ICH7 can make no assumptions about the state of the link prior to receiving a PME_Turn_Off message. 5.2.2.2 Resuming from Suspended State The root port contains enough circuitry in the resume well to detect a wake event thru the WAKE# signal and to wake the system. When WAKE# is detected asserted, an internal signal is sent to the power management controller of the ICH7 to cause the system to wake up. This internal message is not logged in any register, nor is an interrupt/GPE generated due to it. 5.2.2.3 Device Initiated PM_PME Message When the system has returned to a working state from a previous low power state, a device requesting service will send a PM_PME message continuously, until acknowledge by the root port. The root port will take different actions depending upon whether this is the first PM_PME has been received, or whether a previous message has been received but not yet serviced by the operating system. If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via 104 Intel (R) ICH7 Family Datasheet Functional Description RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/ F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation. If this is a subsequent message received (RSTS.PS is already set), the root port will set RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID from the message in a hidden register. No other action will be taken. When the first PME event is cleared by software clearing RSTS.PS, the root port will set RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into RSTS.RID. If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 5.2.2.4 SMI/SCI Generation Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/ F5:Offset DCh:bit 31) to be set. Additionally, BIOS workarounds for power management can be supported by setting MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0), and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI is enabled. The SMI# may occur concurrently with an interrupt or SCI. 5.2.3 SERR# Generation SERR# may be generated via two paths - through PCI mechanisms involving bits in the PCI header, or through PCI Express mechanisms involving bits in the PCI Express capability structure. Figure 5-1. Generation of SERR# to Platform Secondary Parity Error PCI Primary Parity Error Secondary SERR# PCICMD.SEE Correctable SERR# PCI Express Fatal SERR# Non-Fatal SERR# PSTS.SSE SERR# Intel (R) ICH7 Family Datasheet 105 Functional Description 5.2.4 Hot-Plug Each root port implements a Hot-Plug controller which performs the following: * Messages to turn on / off / blink LEDs * Presence and attention button detection * Interrupt generation The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector based Hot-Plug is not supported. 5.2.4.1 Presence Detection When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/ F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3F4/ F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. When a module is removed (via the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt. 5.2.4.2 Message Generation When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 9:8), the root port will send a message down the link to change the state of LEDs on the module. Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When receiving one of these writes, the root port performs the following: * Changes the state in the register. * Generates a completion into the upstream queue * Formulates a message for the downstream port if the field is written to regardless of if the field changed. * Generates the message on the downstream port * When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/ F2/F3F4/F5:Offset 58h:bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up writing to the indicators, power controller fields; Hence, any write to the Slot Control Register is considered a command and if enabled, will result in a command complete interrupt. The only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. A single write to the Slot Control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register. 106 Intel (R) ICH7 Family Datasheet Functional Description 5.2.4.3 Attention Button Detection When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express message "Attention_Button_Pressed" from the device. Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/ F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated. 5.2.4.4 SMI/SCI Generation Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set. Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are: * Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3) * Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 1) * Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 2) * Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 4) When any of these bits are set, SMI # will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. Intel (R) ICH7 Family Datasheet 107 Functional Description 5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) The ICH7's integrated LAN controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each, help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The ICH7 integrated LAN controller can operate in either full-duplex or half-duplex mode. In full- duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for hardware and software configuration parameters. From a software perspective, the integrated LAN controller appears to reside on the secondary side of the ICH7's virtual PCI-to-PCI bridge (see Section 5.1.6). This is typically Bus 1, but may be assigned a different number, depending upon system configuration. The following summarizes the ICH7 LAN controller features: * Compliance with Advanced Configuration and Power Interface and PCI Power Management standards * Support for wake-up on interesting packets and link status change * Support for remote power-up using Wake on LAN* (WOL) technology * Deep power-down mode support * Backward compatible software with 82550, 82557, 82558 and 82559 * TCP/UDP checksum off load capabilities * Support for Intel's Adaptive Technology 5.3.1 LAN Controller PCI Bus Interface As a Fast Ethernet controller, the role of the ICH7 integrated LAN controller is to access transmitted data or deposit received data. The LAN controller, as a bus master device, initiates memory cycles via the PCI bus to fetch or deposit the required data. To perform these actions, the LAN controller is controlled and examined by the processor via its control and status structures and registers. Some of these control and status structures reside in the LAN controller and some reside in system memory. For access to the LAN controller's Control/Status Registers (CSR), the LAN controller acts as a slave (in other words, a target device). The LAN controller serves as a slave also while the processor accesses the EEPROM. 108 Intel (R) ICH7 Family Datasheet Functional Description 5.3.1.1 Bus Slave Operation The ICH7 integrated LAN controller serves as a target device in one of the following cases: * Processor accesses to the LAN controller System Control Block (SCB) Control/ Status Registers (CSR) * Processor accesses to the EEPROM through its CSR * Processor accesses to the LAN controller PORT address via the CSR * Processor accesses to the MDI control register in the CSR The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the I/O space. The LAN controller treats accesses to these memory spaces differently. Control/Status Register (CSR) Accesses The integrated LAN controller supports zero wait-state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses either memory or I/O mapping to access these registers. The LAN controller provides four valid KB of CSR space that include the following elements: * System Control Block (SCB) registers * PORT register * EEPROM control register * MDI control register * Flow control registers In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN controller is the target. Retry Premature Accesses The LAN controller responds with a Retry to any configuration cycle accessing the LAN controller before the completion of the automatic read of the EEPROM. The LAN controller may continue to Retry any configuration accesses until the EEPROM read is complete. The LAN controller does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. Any master access to the LAN controller after the completion of the EEPROM read is honored. Error Handling Data Parity Errors: The LAN controller checks for data parity errors while it is the target of the transaction. If an error was detected, the LAN controller sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15. The LAN controller also asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command register, bit 6). The LAN controller does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The LAN controller prematurely terminate a cycle in the following cases: * After accesses to its CSR * After accesses to the configuration space Intel (R) ICH7 Family Datasheet 109 Functional Description System Error: The LAN controller reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit are not set, the LAN controller only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the LAN controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock. The LAN controller, when detecting system error, claims the cycle if it was the target of the transaction and continues the transaction as if the address was correct. Note: The LAN controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction. 5.3.1.2 CLKRUN# Signal (Mobile Only) The Intel(R) ICH7 receives a free-running 33 MHz clock. It does not stop based on the CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH7 makes sure that the STP_PCI# signal is high indicating that the PCI clock will be running. This is to make sure that any PCI tracker does not get confused by transactions on the PCI bus with its PCI clock stopped. 5.3.1.3 PCI Power Management Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.3, is provided in the ICH7 integrated LAN controller. The LAN controller supports a large set of wake-up packets and the capability to wake the system from a low power state on a link status change. The LAN controller enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the LAN controller wakes the host system. The following sections describe these events, the LAN controller power states, and estimated power consumption at each power state. The LAN controller contains power management registers for PCI, and implements four power states, D0 through D3, which vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the LAN controller's PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3COLD state, the LAN controller can provide wake-up capabilities. Wake-up indications from the LAN controller are provided by the Power Management Event (PME#) signal. 5.3.1.4 PCI Reset Signal The PCIRST# signal may be activated in one of the following cases: * During S3-S5 states * Due to a CF9h reset If PME is enabled (in the PCI power management registers), PCIRST# assertion does not affect any PME related circuits (in other words, PCI power management registers and the wake-up packet would not be affected). While PCIRST# is active, the LAN controller ignores other PCI signals. The configuration of the LAN controller registers associated with ACPI wake events is not affected by PCIRST#. The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller PCI Configuration Space, MAC configuration, and memory structure are initialized while preserving the PME# signal and its context. 110 Intel (R) ICH7 Family Datasheet Functional Description 5.3.1.5 Wake-Up Events There are two types of wake-up events: "Interesting" Packets and Link Status Change. These two events are detailed below. Note: If the Wake on LAN bit in the EEPROM is not set, wake-up events are supported only if the PME Enable bit in the Power Management Control/Status Register (PMCSR) is set. However, if the Wake on LAN bit in the EEPROM is set, and Wake on Magic Packet* or Wake on Link Status Change are enabled, the Power Management Enable bit is ignored with respect to these events. In the latter case, PME# would be asserted by these events. "Interesting" Packet Event In the power-down state, the LAN controller is capable of recognizing "interesting" packets. The LAN controller supports predefined and programmable packets that can be defined as any of the following: * ARP Packets (with Multiple IP addresses) * Direct Packets (with or without type qualification) * Magic Packet * Neighbor Discovery Multicast Address Packet (`ARP' in IPv6 environment) * NetBIOS over TCP/IP (NBT) Query Packet (under IPv4) * Internetwork Package Exchange* (IPX) Diagnostic Packet This allows the LAN controller to handle various packet types. In general, the LAN controller supports programmable filtering of any packet in the first 128 bytes. When the LAN controller is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for the entire frame. The LAN controller classifies the incoming packets as one of the following categories: * No Match: The LAN controller discards the packet and continues to process the incoming packets. * TCO Packet: The LAN controller implements perfect filtering of TCO packets. After a TCO packet is processed, the LAN controller is ready for the next incoming packet. TCO packets are treated as any other wake-up packet and may assert the PME# signal if configured to do so. * Wake-up Packet: The LAN controller is capable of recognizing and storing the first 128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the LAN controller. After the system is fully powered-up, software has the ability to determine the cause of the wake-up event via the PMDR and dump the stored data to the host memory. Magic Packets are an exception. The Magic Packets may cause a power management event and set an indication bit in the PMDR; however, it is not stored by the LAN controller for use by the system when it is woken up. Link Status Change Event The LAN controller link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The LAN controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. Intel (R) ICH7 Family Datasheet 111 Functional Description 5.3.1.6 Wake on LAN* (Preboot Wake-Up) The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM is set. At this point, the LAN controller is in the D0u state. When the LAN controller is in Wake on LAN mode: * The LAN controller scans incoming packets for a Magic Packet and asserts the PME# signal for 52 ms when a 1 is detected in Wake on LAN mode. * The Activity LED changes its functionality to indicates that the received frame passed Individual Address (IA) filtering or broadcast filtering. * The PCI Configuration registers are accessible to the host. The LAN controller switches from Wake on LAN mode to the D0a power state following a setup of the Memory or I/O Base Address Registers in the PCI configuration space. 5.3.2 Serial EEPROM Interface The serial EEPROM stores configuration data for the ICH7 integrated LAN controller and is a serial in/serial out device. The LAN controller supports a 64-register or 256-register size EEPROM and automatically detects the EEPROM's size. The EEPROM should operate at a frequency of at least 1 MHz. All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64-register EEPROM or eight bits for a 256register EEPROM. The end of the address field is indicated by a dummy 0 bit from the EEPROM that indicates the entire address field has been transferred to the device. An EEPROM read instruction waveform is shown in Figure 5-2. Figure 5-2. 64-Word EEPROM Read Instruction Waveform EE_SHCLKK EE_CS A5 EE_DIN READ OP code A4 A3 A2 A10 A A0 D15 EE_DOUT D0 The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch, and Dh) of the EEPROM after the deassertion of Reset. 112 Intel (R) ICH7 Family Datasheet Functional Description 5.3.3 CSMA/CD Unit The ICH7 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, etc.). The LAN controller CSMA/CD unit interfaces to the 82562ET/EM/EZ/EX 10/100 Mbps Ethernet through the ICH7's LAN Connect interface signals. 5.3.3.1 Full Duplex When operating in full-duplex mode, the LAN controller can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the platform LAN Connect component detects a valid frame on its receive differential pair. The ICH7 integrated LAN controller also supports the IEEE 802.3x flow control standard, when in full-duplex mode. The LAN controller operates in either half-duplex mode or full-duplex mode. For proper operation, both the LAN controller CSMA/CD module and the discrete platform LAN Connect component must be set to the same duplex mode. The CSMA duplex mode is set by the LAN Controller Configure command or forced by automatically tracking the mode in the platform LAN Connect component. Following reset, the CSMA defaults to automatically track the platform LAN Connect component duplex mode. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and LAN Connect. 5.3.3.2 Flow Control The LAN controller supports IEEE 802.3x frame-based flow control frames only in both full duplex and half duplex switched environments. The LAN controller flow control feature is not intended to be used in shared media environments. Flow control is optional in full-duplex mode and is selected through software configuration. There are three modes of flow control that can be selected: frame-based transmit flow control, frame-based receive flow control, and none. 5.3.3.3 VLAN Support The LAN controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be implemented by software. The LAN controller supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command. Otherwise, "long" frames are discarded. 5.3.4 Media Management Interface The management interface allows the processor to control the platform LAN Connect component via a control register in the ICH7 integrated LAN controller. This allows the software driver to place the platform LAN Connect in specific modes (e.g., full duplex, loopback, power down, etc.) without the need for specific hardware pins to select the desired mode. This structure allows the LAN controller to query the platform LAN Connect component for status of the link. This register is the MDI Control Register and resides at offset 10h in the LAN controller CSR. The MDI registers reside within the platform LAN Connect component, and are described in detail in the platform LAN Connect component's datasheet. The processor writes commands to this register and the LAN controller reads or writes the control/status parameters to the platform LAN Connect component through the MDI register. Intel (R) ICH7 Family Datasheet 113 Functional Description 5.3.5 TCO Functionality The ICH7 integrated LAN controller supports management communication to reduce Total Cost of Ownership (TCO). The SMBus is used as an interface between the ASF controller and the integrated TCO host controller. There are two different types of TCO operation that are supported (only one supported at a time), they are 1) Integrated ASF Control or 2) external TCO controller support. The SMLink is a dedicated bus between the LAN controller and the integrated ASF controller (if enabled) or an external management controller. An EEPROM of 256 words is required to support the heartbeat command. 5.3.5.1 Advanced TCO Mode The Advanced TCO functionalities through the SMLink are listed in Table 5-4. Table 5-4. Advanced TCO Functionality Power State TCO Controller Functionality Transmit Set Receive TCO Packets D0 nominal Receive TCO Packets Read Intel(R) ICH7 status (PM & Link state) Force TCO Mode Dx (x>0) D0 functionality plus: Read PHY registers Dx functionality plus: Force TCO Mode Configuration commands Read/Write PHY registers Note: For a complete description on various commands, see the Total Cost of Ownership (TCO) System Management Bus Interface Application Note (AP-430). Transmit Command during Normal Operation To serve a transmit request from the TCO controller, the ICH7 LAN controller first completes the current transmit DMA, sets the TCO request bit in the PMDR register (see Section 8.2), and then responds to the TCO controller's transmit request. Following the completion of the TCO transmit DMA, the LAN controller increments the Transmit TCO statistic counter (described in Section 8.2.14). Following the completion of the transmit operation, the ICH7 increments the nominal transmit statistic counters, clears the TCO request bit in the PMDR register, and resumes its normal transmit flow. The receive flow is not affected during this entire period of time. Receive TCO The ICH7 LAN controller supports receive flow towards the TCO controller. The ICH7 can transfer only TCO packets, or all packets that passed MAC address filtering according to its configuration and mode of operation as detailed below. While configured to transfer only TCO packets, it supports Ethernet type II packets with optional VLAN tagging. Force TCO Mode: While the ICH7 is in the force TCO mode, it may receive packets (TCO or all) directly from the TCO controller. Receiving TCO packets and filtering level is controlled by the set Receive enable command from the TCO controller. Following a reception of a TCO packet, the ICH7 increments its nominal Receive statistic counters as well as the Receive TCO counter. 114 Intel (R) ICH7 Family Datasheet Functional Description Dx>0 Power State: While the ICH7 is in a powerdown state, it may receive TCO packets or all directly to the TCO controller. Receiving TCO packets is enabled by the set Receive enable command from the TCO controller. Although TCO packet might match one of the other wake up filters, once it is transferred to the TCO controller, no further matching is searched for and PME is not issued. While receive to TCO is not enabled, a TCO packet may cause a PME if configured to do so (setting TCO to 1 in the filter type). D0 Power State: At D0 power state, the ICH7 may transfer TCO packets to the TCO controller. At this state, TCO packets are posted first to the host memory, then read by the ICH7, and then posted back to the TCO controller. After the packet is posted to TCO, the receive memory structure (that is occupied by the TCO packet) is reclaimed. Other than providing the necessary receive resources, there is no required device driver intervention with this process. Eventually, the ICH7 increments the receive TCO static counter, clears the TCO request bit, and resumes normal control. Read Intel(R) ICH7 Status (PM and Link State) The TCO controller is capable of reading the ICH7 power state and link status. Following a status change, the ICH7 asserts LINKALERT# and then the TCO can read its new power state. Set Force TCO Mode The TCO controller put the ICH7 into the Force TCO mode. The ICH7 is set back to the nominal operation following a PCIRST#. Following the transition from nominal mode to a TCO mode, the ICH7 aborts transmission and reception and loses its memory structures. The TCO may configure the ICH7 before it starts transmission and reception if required. Warning: The Force TCO is a destructive command. It causes the ICH7 to lose its memory structures, and during the Force TCO mode the ICH7 ignores any PCI accesses. Therefore, it is highly recommended to use this command by the TCO controller at system emergency only. 5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) The ASF controller collects information from various components in the system (including the processor, chipset, BIOS, and sensors on the motherboard) and sends this information via the LAN controller to a remote server running a management console. The controller also accepts commands back from the management console and drives the execution of those commands on the local system. The ASF controller is responsible for monitoring sensor devices and sending packets through the LAN controller SMBus (System Management Bus) interface. These ASF controller alerting capabilities include system health information such as BIOS messages, POST alerts, operating system failure notifications, and heartbeat signals to indicate the system is accessible to the server. Also included are environmental notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that something is wrong with the hardware. The packets are used as Alert (S.O.S.) packets or as "heartbeat" status packets. In addition, asset security is provided by messages (e.g., "cover tamper" and "CPU missing") that notify of potential system break-ins and processor or memory theft. The ASF controller is also responsible for receiving and responding to RMCP (Remote Management and Control Protocol) packets. RMCP packets are used to perform various system APM commands (e.g., reset, power-up, power-cycle, and power-down). RMCP can also be used to ping the system to ensure that it is on the network and running Intel (R) ICH7 Family Datasheet 115 Functional Description correctly and for capability reporting. A major advantage of ASF is that it provides these services during the time that software is unable to do so (e.g., during a lowpower state, during boot-up, or during an operating system hang) but are not precluded from running in the working state. The ASF controller communicates to the system and the LAN controller logic through the SMBus connections. The first SMBus connects to the host SMBus controller (within the ICH7) and any SMBus platform sensors. The SMBus host is accessible by the system software, including software running on the operating system and the BIOS. Note that the host side bus may require isolation if there are non-auxiliary devices that can pull down the bus when un-powered. The second SMBus connects to the LAN controller. This second SMBus is used to provide a transmit/receive network interface. The stimulus for causing the ASF controller to send packets can be either internal or external to the ASF controller. External stimuli are link status changes or polling data from SMBus sensor devices; internal events come from, among others, a set of timers or an event caused by software. The ASF controller provides three local configuration protocols via the host SMBus. The first one is the SMBus ARP interface that is used to identify the SMBus device and allow dynamic SMBus address assignment. The second protocol is the ASF controller command set that allows software to manage an ASF controller compliant interface for retrieving info, sending alerts, and controlling timers. ICH7 provides an input and an output EEPROM interface. The EEPROM contains the LAN controller configuration and the ASF controller configuration/packet information. 5.4.1 ASF Management Solution Features/Capabilities * Alerting -- Transmit SOS packets from S0-S5 states -- System Health Heartbeats -- SOS Hardware Events - System Boot Failure (Watchdog Expires on boot) - LAN Link Loss - Entity Presence (on ASF power-up) - SMBus Hung - Maximum of eight Legacy Sensors - Maximum of 128 ASF Sensor events -- Watchdog Timer for operating system lockup/System Hang/Failure to Boot -- General Push support for BIOS (POST messages) * Remote Control -- Presence Ping Response -- Configurable Boot Options -- Capabilities Reporting -- Auto-ARP Support -- System Remote Control - Power-Down - Power-Up - Power Cycle - System Reset -- State-Based Security - Conditional Action on WatchDog Expire 116 Intel (R) ICH7 Family Datasheet Functional Description * ASF Compliance -- Compliant with the Alert Standard Format (ASF) Specification, Version 1.03 - PET Compliant Packets - RMCP - Legacy Sensor Polling - ASF Sensor Polling - Remote Control Sensor Support * Advanced Features / Miscellaneous -- SMBus 2.0 compliant -- Optional reset extension logic (for use with a power-on reset) 5.4.2 Note: ASF Hardware Support ASF requires additional hardware to make a complete solution. If an ASF compatible device is externally connected and properly configured, the internal ICH7 ASF controller will be disabled. The external ASF device will have access to the SMBus controller. 5.4.2.1 Intel(R) 82562EM/EX The 82562EM/EX Ethernet LAN controller is necessary. This LAN controller provides the means of transmitting and receiving data on the network, as well as adding the Ethernet CRC to the data from the ASF. 5.4.2.2 EEPROM (256x16, 1 MHz) To support the ICH7 ASF solution, a larger, 256x16 1 MHz, EEPROM is necessary to configure defaults on reset and on hard power losses (software un-initiated). The ASF controller shares this EEPROM with the LAN controller and provides a pass through interface to achieve this. The ASF controller expects to have exclusive access to words 40h through F7h. The LAN controller can use the other EEPROM words. The ASF controller will default to safe defaults if the EEPROM is not present or not configured properly (both cause an invalid CRC). 5.4.2.3 Legacy Sensor SMBus Devices The ASF controller is capable of monitoring up to eight sensor devices on the main SMBus. These sensors are expected to be compliant with the Legacy Sensor Characteristics defined in the Alert Standard Format (ASF) Specification, Version 1.03. 5.4.2.4 Remote Control SMBus Devices The ASF controller is capable of causing remote control actions to Remote Control devices via SMBus. These remote control actions include Power-Up, Power-Down, Power-Cycle, and Reset. The ASF controller supports devices that conform to the Alert Standard Format (ASF) Specification, Version 1.03, Remote Control Devices. 5.4.2.5 ASF Sensor SMBus Devices The ASF controller is capable of monitoring up to 128 ASF sensor devices on the main SMBus. However, ASF is restricted by the number of total events which may reduce the number of SMBus devices supported. The maximum number of events supported by ASF is 128. The ASF sensors are expected to operate as defined in the Alert Standard Format (ASF) Specification, Version 1.03. Intel (R) ICH7 Family Datasheet 117 Functional Description 5.4.3 ASF Software Support ASF requires software support to make a complete solution. The following software is used as part of the complete solution. * ASF Configuration driver / application * Network Driver * BIOS Support for SMBIOS, SMBus ARP, ACPI * Sensor Configuration driver / application Note: Contact your Intel Field Representative for the Client ASF Software Development Kit (SDK) that includes additional documentation and a copy of the client ASF software drivers. Intel also provides an ASF Console SDK to add ASF support to a management console. 5.5 Note: LPC Bridge (w/ System and Management Functions) (D31:F0) LPC DMA is not supported on the Ultra Mobile component (ICH7-U). The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA (Desktop and Mobile only), Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are described in their respective sections. 5.5.1 LPC Interface The ICH7 implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the ICH7 is shown in Figure 5-3. Note that the ICH7 implements all of the signals that are shown as optional, but peripherals are not required to do so. Figure 5-3. LPC Interface Diagram P IB s Cu PI C CK L PI C RT S# PI C SR Q E IR PI C PE M# In l(R)IC 7 te H L D[3 ] A :0 L R M# FAE LR# DQ (o tio a p n l) L CD v e P e ic S SS A # U_ TT GI P L CD PP# (o tio a p n l) LM S I# (o tio a p n l) 118 Intel (R) ICH7 Family Datasheet Functional Description 5.5.1.1 LPC Cycle Types The ICH7 implements the following cycle types as described in Table 5-5 Table 5-5. LPC Cycle Types Supported Cycle Type I/O Read I/O Write DMA Read (Desktop and Mobile Only) DMA Write (Desktop and Mobile Only) Bus Master Read Bus Master Write (R) Comment 1 byte only. Intel ICH7 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. 1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. Can be 1, or 2 bytes Can be 1, or 2 bytes Can be 1, 2, or 4 bytes. (See Note 1 below) Can be 1, 2, or 4 bytes. (See Note 1 below) NOTES: 1. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an address where A0=0). A dword transfer must be dword-aligned (i.e., with an address where A1 and A0 are both 0) 5.5.1.2 Table 5-6. Start Field Definition Start Field Bit Definitions Bits[3:0] Encoding 0000 0010 0011 1111 Definition Start of cycle for a generic target Grant for bus master 0 Grant for bus master 1 Stop/Abort: End of a cycle for a target. NOTE: All other encodings are RESERVED. Intel (R) ICH7 Family Datasheet 119 Functional Description 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit 0 to 0. Table 5-7 shows the valid bit encodings. Table 5-7. Cycle Type Bit Definitions Bits[3:2] 00 00 10 10 11 Bit1 0 1 0 1 x I/O Read I/O Write Desktop and Mobile: DMA Read Ultra Mobile: Reserved Desktop and Mobile: DMA Write Ultra Mobile: Reserved Reserved. If a peripheral performing a bus master cycle generates this value, the Intel(R) ICH7 aborts the cycle. Definition NOTE: All other encodings are RESERVED. 5.5.1.4 SIZE Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits. Bits[1:0] are encoded as listed in Table 5-8. Table 5-8. Transfer Size Bit Definition Bits[1:0] 00 01 10 11 8-bit transfer (1 byte) 16-bit transfer (2 bytes) Reserved. The Intel(R) ICH7 does not drive this combination. If a peripheral running a bus master cycle drives this combination, the ICH7 may abort the transfer. 32-bit transfer (4 bytes) Size 120 Intel (R) ICH7 Family Datasheet Functional Description 5.5.1.5 SYNC Valid values for the SYNC field are shown in Table 5-9. Table 5-9. SYNC Bit Definition Bits[3:0]1,2 0000 Indication Ready: SYNC achieved with no error. For DMA transfers on desktop and mobile components, this also indicates DMA request deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel(R) ICH7 does not use this encoding. Instead, the ICH7 uses the Long Wait encoding (see next encoding below). Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the ICH7 for bus master cycles, rather than the Short Wait (0101). Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers and is not allowed for any other type of cycle. Ultra Mobile: Reserved Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer. For DMA transfers on desktop and mobile components, this not only indicates an error, but also indicates DMA request deassertion and no more transfers desired for that channel. 0101 0110 1001 1010 NOTES: 1. All other combinations are RESERVED. 2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC. 5.5.1.6 SYNC Time-Out There are several error cases that can occur on the LPC interface. The ICH7 responds as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions; however, these are not handled by the ICH7. 5.5.1.7 SYNC Error Indication The ICH7 responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1. Upon recognizing the SYNC field indicating an error, the ICH7 treats this as an SERR by reporting this into the Device 31 Error Reporting Logic. Intel (R) ICH7 Family Datasheet 121 Functional Description 5.5.1.8 LFRAME# Usage The ICH7 follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH7 performs an abort for the following cases (possible failure cases): * ICH7 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks. * ICH7 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern. * A peripheral drives an invalid address when performing bus master cycles. * A peripheral drives an invalid value. 5.5.1.9 I/O Cycles For I/O cycles targeting registers specified in the ICH7's decode ranges, the ICH7 performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the ICH7 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH7 returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds. 5.5.1.10 Bus Master Cycles The ICH7 supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin Count Interface Specification, Revision 1.1. The ICH7 has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b). Note: The ICH7 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles. 5.5.1.11 LPC Power Management CLKRUN# Protocol (Mobile/Ultra Mobile Only) The CLKRUN# protocol is same as in the PCI Local Bus Specification. Stopping the PCI clock stops the LPC clock. LPCPD# Protocol Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ# low or tri-state it. ICH7 shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the ICH7 drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 s from LPCPD# assertion to LRST# assertion. This specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. The ICH7 asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. 122 Intel (R) ICH7 Family Datasheet Functional Description 5.5.1.12 Configuration and Intel(R) ICH7 Implications LPC Interface Decoders To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH7 includes several decoders. During configuration, the ICH7 must be programmed with the same decode ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space. Note: The ICH7 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a "Retry Read" feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the ICH7 that supports two LPC bus masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master. 5.5.2 SERR# Generation Several internal and external sources of the LPC Bridge can cause SERR#, as described below. The first class of errors is parity errors related to the backbone. The LPC Bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on the backbone cycles where the bridge was the master and parity error response is enabled. If either of these two conditions is met, and with SERR# enable (PCICMD.SERR_EN) set, SERR# will be captured. Additionally, if the LPC Bridge receives an error SYNC on LPC bus, an SERR# will also be generated. Figure 5-4. LPC Bridge SERR# Generation PCISTS.DPE (D31:F0:06h, bit15) PCISTS.DPED (D31:F0:06h, bit 8) LPC Error Sync Received PCICMD.SERR_EN (D31:F0:04h, bit 8) PCISTS.SSE (D31:F0:06h, bit 14) SERR# Intel (R) ICH7 Family Datasheet 123 Functional Description 5.6 Note: DMA Operation (D31:F0) For ICH7-U Ultra Mobile, LPC DMA is not supported. The ICH7 supports LPC DMA using the ICH7's DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA. The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently programmable channels (Figure 5-5). DMA controller 1 (DMA-1) corresponds to DMA channels 0-3 and DMA controller 2 (DMA-2) corresponds to channels 5-7. DMA channel 4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1. Figure 5-5. Intel(R) ICH7 DMA Controller Channel 0 Channel 1 DMA-1 Channel 2 Channel 3 Channel 6 Channel 7 Channel 4 Channel 5 DMA-2 Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ICH7 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. The DMA controller also features refresh address generation, and autoinitialization following a DMA termination. 5.6.1 Channel Priority For priority resolution, the DMA consists of two logical channel groups: channels 0-3 and channels 4-7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a software request for DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in Section 10.2. 124 Intel (R) ICH7 Family Datasheet Functional Description 5.6.1.1 Fixed Priority The initial fixed priority structure is as follows: High priority 0, 1, 2, 3 Low priority 5, 6, 7 The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7. 5.6.1.2 Rotating Priority Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0-3, 5-7). Channels 0-3 rotate as a group of 4. They are placed between channel 5 and channel 7 in the priority list. Channel 5-7 rotate as part of a group of 4. That is, channels (5-7) form the first three positions in the rotation, while channel group (0-3) comprises the fourth position in the arbitration. 5.6.2 Address Compatibility Mode When the DMA is operating, the addresses do not increment or decrement through the High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still do not increment or decrement through the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h, not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. 5.6.3 Summary of DMA Transfer Sizes Table 5-10 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word Count Register" indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled "Current Address Increment/Decrement" indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented. Intel (R) ICH7 Family Datasheet 125 Functional Description 5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words Table 5-10. DMA Transfer Size DMA Device Date Size And Word Count 8-Bit I/O, Count By Bytes 16-Bit I/O, Count By Words (Address Shifted) Current Byte/Word Count Register Bytes Words Current Address Increment/ Decrement 1 1 The ICH7 maintains compatibility with the implementation of the DMA in the PC AT that used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address Register (when the DMA channel is in this mode), the Current Address must be programmed to an even address with the address value shifted right by one bit. The address shifting is shown in Table 5-11. Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers Output Address A0 A[16:1] A[23:17] 8-Bit I/O Programmed Address (Ch 0-3) A0 A[16:1] A[23:17] 16-Bit I/O Programmed Address (Ch 5-7) (Shifted) 0 A[15:0] A[23:17] NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode. 5.6.4 Autoinitialize By programming a bit in the DMA Channel Mode Register, a channel may be set up as an autoinitialize channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously with the Current Registers by the microprocessor when the DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. 5.6.5 Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: * Clear Byte Pointer Flip-Flop * Master Clear * Clear Mask Register They do not depend on any specific bit pattern on the data bus. 126 Intel (R) ICH7 Family Datasheet Functional Description 5.7 LPC DMA (Desktop and Mobile Only) DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0-3 are 8 bit channels. Channels 5-7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. 5.7.1 Asserting DMA Requests Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The ICH7 has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral uses the following serial encoding sequence: * Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions. * The next three bits contain the encoded DMA channel number (MSB first). * The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. The case where ACT is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. * After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal can be brought low to the next encoding sequence. If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to selfarbitrate before sending the message. Figure 5-6. DMA Request Assertion through LDRQ# LCLK LDRQ# 5.7.2 Start MSB LSB ACT Start Abandoning DMA Requests DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ# message with the `ACT' bit set to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer. There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. Intel (R) ICH7 Family Datasheet 127 Functional Description In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH7, there is no assurance that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. This method of DMA deassertion should be prevented whenever possible, to limit boundary conditions both on the ICH7 and the peripheral. 5.7.3 General Flow of DMA Transfers Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. ICH7 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted. 2. ICH7 asserts `cycle type' of DMA, direction based on DMA transfer direction. 3. ICH7 asserts channel number and, if applicable, terminal count. 4. ICH7 indicates the size of the transfer: 8 or 16 bits. 5. If a DMA read... -- The ICH7 drives the first 8 bits of data and turns the bus around. -- The peripheral acknowledges the data with a valid SYNC. -- If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA write... -- The ICH7 turns the bus around and waits for data. -- The peripheral indicates data ready through SYNC and transfers the first byte. -- If a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 5.7.4 Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred. 5.7.5 Verify Mode Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory. 128 Intel (R) ICH7 Family Datasheet Functional Description 5.7.6 DMA Request Deassertion An end of transfer is communicated to the ICH7 through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand mode device) the ICH7 needs to know when to deassert the DMA request based on the data currently being transferred. The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the ICH7 whether this is the last byte of transfer or if more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or 1010b (ready with error). These encodings tell the ICH7 that this is the last piece of data transferred on a DMA read (ICH7 to peripheral), or the byte that follows is the last piece of data transferred on a DMA write (peripheral to ICH7). When the ICH7 sees one of these two encodings, it ends the DMA transfer after this byte and deasserts the DMA request to the 8237. Therefore, if the ICH7 indicated a 16bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The ICH7 does not attempt to transfer the second byte, and deasserts the DMA request internally. If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size, then the ICH7 only deasserts the DMA request to the 8237 since it does not need to end the transfer. If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of 1001b (ready plus more data). This tells the 8237 that more data bytes are requested after the current byte has been transferred, so the ICH7 keeps the DMA request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC value of 1001b to the ICH7, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the ICH7 will then come back with another START-CYCTYPE-CHANNEL-SIZE etc. combination to initiate another transfer to the peripheral. The peripheral must not assume that the next START indication from the ICH7 is another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode DMA devices can be ensured that they will receive the next START indication from the ICH7. Note: Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237's address and decrementing its byte count. 5.7.7 SYNC Field / LDRQ# Rules Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a deassertion is indicated through the SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. Intel (R) ICH7 Family Datasheet 129 Functional Description Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no "plug-n-play" registry is required. The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 5.8 8254 Timers (D31:F0) The ICH7 contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value 1 counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0. Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. Counter 2, Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports). 130 Intel (R) ICH7 Family Datasheet Functional Description 5.8.1 Timer Programming The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16-bit counter. 4. Repeat with other counters. Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters. Several commands are available: * Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD). * Counter Latch Command. Latches the current count so that it can be read by the system. The countdown process continues. * Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 5-12 lists the six operating modes for the interval counters. Table 5-12. Counter Operating Modes Mode 0 1 2 Function Out signal on end of count (=0) Hardware retriggerable one-shot Rate generator (divide by n counter) Square wave output Description Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. Output is 0. When count goes to 0, output goes to 1 for one clock time. Output is 1. Output goes to 0 for one clock time, then back to 1 and counter is reloaded. Output is 1. Output goes to 0 when counter rolls over, and counter is reloaded. Output goes to 1 when counter rolls over, and counter is reloaded, etc. Output is 1. Output goes to 0 when count expires for one clock time. Output is 1. Output goes to 0 when count expires for one clock time. 3 4 5 Software triggered strobe Hardware triggered strobe Intel (R) ICH7 Family Datasheet 131 Functional Description 5.8.2 Reading from the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. 5.8.2.1 Simple Read The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of counter 2, the count can be stopped by writing to the GATE bit in port 61h. 5.8.2.2 Counter Latch Command The Counter Latch command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter's Count register as was programmed by the Control register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read is the count at the time the first Counter Latch command was issued. 5.8.2.3 Read Back Command The Read Back command, written to port 43h, latches the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then be read by I/O access to the counter address. The Read Back command may be used to latch multiple counter outputs at one time. This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched until they are read. If multiple count Read Back commands are issued to the same counter without reading the count, all but the first are ignored. The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored. 132 Intel (R) ICH7 Family Datasheet Functional Description Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored. If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 5.9 8259 Interrupt Controllers (PIC) (D31:F0) The ICH7 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0-7. Table 5-13 shows how the cores are connected. . Table 5-13. Interrupt Controller Core Connections 8259 8259 Input 0 1 2 Master 3 4 5 6 7 0 1 2 3 4 Slave 5 Typical Interrupt Source Internal Keyboard Internal Serial Port A Serial Port B Parallel Port / Generic Floppy Disk Parallel Port / Generic Internal Real Time Clock Generic Generic Generic PS/2 Mouse Internal Connected Pin / Function Internal Timer / Counter 0 output / HPET #0 IRQ1 via SERIRQ Slave controller INTR output IRQ3 via SERIRQ, PIRQ# IRQ4 via SERIRQ, PIRQ# IRQ5 via SERIRQ, PIRQ# IRQ6 via SERIRQ, PIRQ# IRQ7 via SERIRQ, PIRQ# Internal RTC / HPET #1 IRQ9 via SERIRQ, SCI, TCO, or PIRQ# IRQ10 via SERIRQ, SCI, TCO, or PIRQ# IRQ11 via SERIRQ, SCI, TCO, or PIRQ# IRQ12 via SERIRQ, SCI, TCO, or PIRQ# State Machine output based on processor FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed. IDEIRQ (legacy mode, non-combined or combined mapped as primary), SATA Primary (legacy mode), or via SERIRQ or PIRQ# IDEIRQ (legacy mode -- combined, mapped as secondary), SATA Secondary (legacy mode) or via SERIRQ or PIRQ# 6 IDE cable, SATA 7 IDE cable, SATA The ICH7 cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the ICH7 PIC. Intel (R) ICH7 Family Datasheet 133 Functional Description Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH7. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. Therefore, the term "high" indicates "active," which means "low" on an originating PIRQ#. 5.9.1 5.9.1.1 Interrupt Handling Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR. Table 5-14. Interrupt Status Registers Bit IRR Description Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will not generate INTR. Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR. ISR IMR 5.9.1.2 Acknowledging Interrupts The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a PCI Interrupt Acknowledge Cycle to the ICH7. The PIC translates this command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt within that controller. Table 5-15. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 ICW2[7:3] Bits [7:3] Bits [2:0] 111 110 101 100 011 010 001 000 134 Intel (R) ICH7 Family Datasheet Functional Description 5.9.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the ICH7. 4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH7 converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. 5.9.2 Initialization Command Words (ICWx) Before operation can begin, each 8259 must be initialized. In the ICH7, this is a four byte sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the master controller, and A0h for the slave controller. 5.9.2.1 ICW1 An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the ICH7 PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR. Intel (R) ICH7 Family Datasheet 135 Functional Description 5.9.2.2 ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.9.2.3 ICW3 The third write in the sequence (ICW3) has a different meaning for each controller. * For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller. Within the ICH7, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s. * For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.9.2.4 ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system. 5.9.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. * OCW1 masks and unmasks interrupt lines. * OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function. * OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/disables polled interrupt mode. 5.9.4 5.9.4.1 Modes of Operation Fully Nested Mode In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or if in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. Interrupt priorities can be changed in the rotating priority mode. 136 Intel (R) ICH7 Family Datasheet Functional Description 5.9.4.2 Special Fully-Nested Mode This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions: * When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. In the normal-nested mode, a slave is masked out when its request is in service. * When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a NonSpecific EOI command to the slave and then reading its ISR. If it is 0, a nonspecific EOI can also be sent to the master. 5.9.4.3 Automatic Rotation Mode (Equal Priority Devices) In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0). 5.9.4.4 Specific Rotation Mode (Specific Priority) Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority device. In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO-L2=IRQ level to receive bottom priority. 5.9.4.5 Poll Mode Poll mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. Poll mode can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. Intel (R) ICH7 Family Datasheet 137 Functional Description 5.9.4.6 Cascade Mode The PIC in the ICH7 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the slaves through a three bit internal bus. In the ICH7, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. An EOI command must be issued twice: once for the master and once for the slave. 5.9.4.7 Edge and Level Triggered Mode In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the ICH7, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned. 5.9.4.8 End of Interrupt (EOI) Operations An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to 1. 5.9.4.9 Normal End of Interrupt In normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the ICH7, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller. 5.9.4.10 Automatic End of Interrupt Mode In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 138 Intel (R) ICH7 Family Datasheet Functional Description 5.9.5 5.9.5.1 Masking Interrupts Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller. 5.9.5.2 Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0. 5.9.6 Steering PCI Interrupts The ICH7 can be programmed to allow PIRQA#-PIRQH# (PIRQE#-PIRQH# on Ultra Mobile) to be internally routed to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable through the through the PIRQx Route Control registers, located at 60- 63h and 68-6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH7 internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer be used by an active high device (through SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH7 receives the PIRQ input, like all of the other external sources, and routes it accordingly. Intel (R) ICH7 Family Datasheet 139 Functional Description 5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH7 incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multiprocessor system. 5.10.1 Interrupt Handling The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are: * Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. * Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 can be given a higher priority than interrupt 3. * More Interrupts. The I/O APIC in the ICH7 supports a total of 24 interrupts. * Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC devices in the system with their own interrupt vectors. 5.10.2 Interrupt Mapping The I/O APIC within the ICH7 supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows, and match "Config 6" of the Multi-Processor Specification. Table 5-16. APIC Interrupt Mapping (Sheet 1 of 2) IRQ #1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Via SERIRQ No Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes Direct from Pin No No No No No No No No No No No No No No Yes3 Yes Via PCI Message No Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes FERR# logic IDEIRQ (legacy mode, non-combined or combined mapped as primary), SATA Primary (legacy mode) IDEIRQ (legacy mode -- combined, mapped as secondary), SATA Secondary (legacy mode) RTC, HPET #1 (legacy mode) Option for SCI, TCO Option for SCI, TCO HPET #2, Option for SCI, TCO2 8254 Counter 0, HPET #0 (legacy mode) Internal Modules Cascade from 8259 #1 140 Intel (R) ICH7 Family Datasheet Functional Description Table 5-16. APIC Interrupt Mapping (Sheet 2 of 2) IRQ #1 16 17 18 19 20 21 22 23 Via SERIRQ PIRQA# PIRQB# PIRQC# PIRQD# N/A N/A N/A N/A Direct from Pin PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# Yes Yes NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Option for SCI, TCO, HPET #0,1,2. Other internal devices are routable; see Section 7.1.41 through Section 7.1.50. Via PCI Message Internal Modules Internal devices are routable; see Section 7.1.41 though Section 7.1.50. NOTES: 1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. ICH7 hardware does not prevent sharing of IRQ 11. 3. IDEIRQ can only be driven directly from the pin when in legacy IDE mode. 5.10.3 PCI / PCI Express* Message-Based Interrupts When external devices through PCI / PCI Express wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 1.0a for generating INTA# - INTD#. These will be translated internal assertions/de-assertions of INTA# - INTD#. 5.10.4 Front Side Bus Interrupt Delivery For processors that support Front Side Bus (FSB) interrupt delivery, the ICH7 requires that the I/O APIC deliver interrupt messages to the processor in a parallel manner, rather than using the I/O APIC serial scheme. This is done by the ICH7 writing (via DMI) to a memory location that is snooped by the processor(s). The processor(s) snoop the cycle to know which interrupt goes active. The following sequence is used: 1. When the ICH7 detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt. 2. Internally, the ICH7 requests to use the bus in a way that automatically flushes upstream buffers. This can be internally implemented similar to a DMA device request. 3. The ICH7 then delivers the message by performing a write cycle to the appropriate address with the appropriate data. The address and data formats are described below in Section 5.10.4.4. Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not the ICH7. Intel (R) ICH7 Family Datasheet 141 Functional Description 5.10.4.1 Edge-Triggered Operation In this case, the "Assert Message" is sent when there is an inactive-to-active edge on the interrupt. 5.10.4.2 Level-Triggered Operation In this case, the "Assert Message" is sent when there is an inactive-to-active edge on the interrupt. If after the EOI the interrupt is still active, then another "Assert Message" is sent to indicate that the interrupt is still active. 5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery Capabilities Indication: The capability to support Front Side Bus interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI configuration software. 5.10.4.4 Interrupt Message Format The ICH7 writes the message to PCI (and to the Host controller) as a 32-bit memory write cycle. It uses the formats shown in Table 5-17 and Table 5-18 for the address and data. The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus messages as a SMI in which case the processor treats the incoming interrupt as a SMI instead of as an interrupt. This does not mean that the ICH7 has any way to have a SMI source from ICH7 power management logic cause the I/O APIC to send an SMI message (there is no way to do this). The ICH7's I/O APIC can only send interrupts due to interrupts which do not include SMI, NMI or INIT. This means that in IA32/IA64 based platforms, Front Side Bus interrupt message format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used and is not supported. Only the hardware pin connection is supported by ICH7. : Table 5-17. Interrupt Message Address Format Bit 31:20 19:12 11:4 Will allways be FEEh Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for the interrupt associated with this message. Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection Table entry for the interrupt associated with this message. Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be redirected. 3 0 = The message will be delivered to the agent (processor) listed in bits 19:12. 1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from bits 10:8 in the Data Field (see below). The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit will be 0 Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. Will always be 00. Description 2 1:0 142 Intel (R) ICH7 Family Datasheet Functional Description Table 5-18. Interrupt Message Data Format Bit 31:16 15 14 13:12 11 Will always be 0000h. Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for that interrupt. Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit is always 1. Will always be 00 Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O Redirection Table for that interrupt. Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. 10:8 000 = Fixed 100 = NMI 001 = Lowest Priority 101 = INIT 010 = SMI/PMI 110 = Reserved 011 = Reserved 111 = ExtINT 7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. Description 5.11 Serial Interrupt (D31:F0) The ICH7 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the ICH7, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the following fashion: * S - Sample Phase. Signal driven low * R - Recovery Phase. Signal driven high * T - Turn-around Phase. Signal released The ICH7 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0-1, 2-15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20-23). Note: When the IDE controller is enabled or the SATA controller (Desktop and Mobile Only) is configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA legacy interrupts, which cannot be shared, i.e. through the Serial Interrupt pin. If IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior may occur. For example, IRQ14/15 may not be detected by ICH7's interrupt controller. 5.11.1 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH7 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. Intel (R) ICH7 Family Datasheet 143 Functional Description The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the ICH7 asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The ICH7 senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the ICH7 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation. 5.11.2 Data Frames Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each: * Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0-1 and IRQ2-15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low interrupt is being requested. * Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase. * Turn-around Phase. The device tri-states the SERIRQ line 5.11.3 Stop Frame After all data frames, a Stop Frame is driven by the ICH7. The SERIRQ signal is driven low by the ICH7 for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode: Table 5-19. Stop Frame Explanation Stop Frame Width 2 PCI clocks 3 PCI clocks Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (Intel(R) ICH7) may initiate a Start Frame 5.11.4 Specific Interrupts Not Supported via SERIRQ There are three interrupts seen through the serial stream that are not supported by the ICH7. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are: * IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0. * IRQ8#. RTC interrupt can only be generated internally. * IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The ICH7 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. 144 Intel (R) ICH7 Family Datasheet Functional Description 5.11.5 Data Frame Format Table 5-20 shows the format of the data frames. For the PCI interrupts (A-D), the output from the ICH7 is ANDed with the PCI input signal. This way, the interrupt can be signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are shared). Table 5-20. Data Frame Format Data Frame # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Interrupt Clocks Past Start Frame 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 Ignored. IRQ13 can only be generated from FERR# Not attached to PATA or SATA logic Not attached to PATA or SATA logic Same as ISA IOCHCK# going active. Drive PIRQA# Drive PIRQB# Drive PIRQC# Drive PIRQD# Ignored. IRQ8# can only be generated internally. Causes SMI# if low. Will set the SERIRQ_SMI_STS bit. Comment Ignored. IRQ0 can only be generated via the internal 8524 IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# PCI INTA# PCI INTB# PCI INTC# PCI INTD# Intel (R) ICH7 Family Datasheet 145 Functional Description 5.12 Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is available. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value of C0-FFh in the Alarm bytes to indicate a don't care situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. Any RAM writes under the same conditions are ignored. Note: The leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the current RTC implementation would incorrectly calculate the leap-year. The ICH7 does not implement month/year alarms. 5.12.1 Update Cycles An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 s after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 s to complete. The time and date RAM locations (0-9) are disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at least 488 s before the update cycle begins. Warning: The overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 146 Intel (R) ICH7 Family Datasheet Functional Description 5.12.2 Interrupts The real-time clock interrupt is internally routed within the ICH7 both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH7, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked. 5.12.3 Lockable RAM Ranges The RTC's battery-backed RAM supports two 8-byte ranges that can be locked via the configuration space. If the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will not return the location's actual value (resultant value is undefined). Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range. 5.12.4 Century Rollover The ICH7 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form 99 to 00. Upon detecting the rollover, the ICH7 sets the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update registers in the RTC RAM that are associated with century value. If the system is in a sleep state (S1-S5) when the century rollover occurs, the ICH7 also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM. 5.12.5 Clearing Battery-Backed RTC RAM Clearing CMOS RAM in an ICH7-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to Clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the RTC power well will be set to their default state. BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be pulled up through a weak pull-up resistor. Table 5-21 shows which bits are set to their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced--all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state. Intel (R) ICH7 Family Datasheet 147 Functional Description Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2) Bit Name Alarm Interrupt Enable (AIE) Register Register B (General Configuration) (RTC_REGB) Register C (Flag Register) (RTC_REGC) General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register GEN_PMCON_3 General PM Configuration 3 Register (GEN_PMCON_3) General PM Configuration 3 Register GEN_PMCON_3 Power Management 1 Status Register (PM1_STS) Power Management 1 Enable Register (PM1_EN) Power Management 1 Control (PM1_CNT) General Purpose Event 0 Enables Register (GPE0_EN) General Purpose Event 0 Enables Register (GPE0_EN) General Purpose Event 0 Enables Register (GPE0_EN) Location I/O space (RTC Index + 0Bh) I/O space (RTC Index + 0Ch) Bit(s) Default State X 5 Alarm Flag (AF) 5 X SWSMI_RATE_SEL D31:F0:A4h 7:6 0 SLP_S4# Minimum Assertion Width D31:F0:A4h 5:4 0 SLP_S4# Assertion Stretch Enable D31:F0:A4h 3 0 RTC Power Status (RTC_PWR_STS) D31:F0:A4h 2 0 Power Failure (PWR_FLR) D31:F0:A4h 1 0 AFTERG3_EN D31:F0:A4h 0 0 Power Button Override Status (PRBTNOR_STS) RTC Event Enable (RTC_EN) Sleep Type (SLP_TYP) PMBase + 00h 11 0 PMBase + 02h 10 0 PMBase + 04h 12:10 0 PME_EN BATLOW_EN (Mobile/Ultra Mobile Only) RI_EN PMBase + 2Ch 11 0 PMBase + 2Ch 10 0 PMBase + 2Ch 8 0 148 Intel (R) ICH7 Family Datasheet Functional Description Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2) Bit Name NEWCENTURY_STS Intruder Detect (INTRD_DET) Top Swap (TS) PATA Reset State (PRS) (Mobile/Ultra Mobile Only) Register TCO1 Status Register (TCO1_STS) TCO2 Status Register (TCO2_STS) Backed Up Control Register (BUC) Backed Up Control Register (BUC) Location TCOBase + 04h TCOBase + 06h Chipset Config Registers:Offset 3414h Chipset Config Registers:Offset 3414h Bit(s) 7 0 0 Default State 0 0 X 1 1 Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted with the jumper in new position, then powered back down. The jumper is replaced back to the normal position, then the system is rebooted again. Clearing CMOS, using a jumper on VccRTC, must not be implemented. Warning: 5.13 Processor Interface (D31:F0) The ICH7 interfaces to the processor with a variety of signals * Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP# (supported only on desktop platforms), CPUPWRGD * Standard Input from processor: FERR# * Intel SpeedStep(R) technology output to processor: CPUPWRGOOD (In mobile/Ultra Mobile configurations) Most ICH7 outputs to the processor use standard buffers. The ICH7 has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor. 5.13.1 Processor Interface Signals This section describes each of the signals that interface between the ICH7 and the processor(s). Note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.13.1.1 A20M# (Mask A20) The A20M# signal is active (low) when both of the following conditions are true: * The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0 * The A20GATE input signal is a 0 The A20GATE input signal is expected to be generated by the external microcontroller (KBC). Intel (R) ICH7 Family Datasheet 149 Functional Description 5.13.1.2 INIT# (Initialization) The INIT# signal is active (driven low) based on any one of several events described in Table 5-22. When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high. Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes inactive. This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V. Table 5-22. INIT# Going Active Cause of INIT# Going Active Shutdown special cycle from processor. PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1. PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit 2) transitions from 0 to 1. 0 to 1 transition on RCIN# must occur before the Intel(R) ICH7 will arm INIT# to be generated again. RCIN# input signal goes low. RCIN# is expected to be driven by the external microcontroller (KBC). NOTE: RCIN# signal is expected to be high during S3HOT and low during S3COLD, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT# signal to be generated to the processor. To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register. Comment CPU BIST 5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error) The ICH7 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset 31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register (I/O Register F0h), the ICH7 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is not driven active unless FERR# is active. 150 Intel (R) ICH7 Family Datasheet Functional Description Figure 5-7. Coprocessor Error Timing Diagram FERR# Internal IRQ13 I/O Write to F0h IGNNE# If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. 5.13.1.4 NMI (Non-Maskable Interrupt) Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-23. Table 5-23. NMI Sources Cause of NMI SERR# goes active (either internally, externally via SERR# signal, or via message from (G)MCH) IOCHK# goes active via SERIRQ# stream (ISA system Error) Comment Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). 5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) The ICH7 power management logic controls these active-low signals. Refer to Section 5.14 for more information on the functionality of these signals. Note: CPU Sleep (CPUSLP#) is supported only on desktop platforms. 5.13.1.6 CPU Power Good (CPUPWRGOOD) This signal is connected to the processor's PWRGOOD input. This signal represents a logical AND of the ICH7's PWROK and VRMPWRGD signals. 5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) This active-low signal controls the internal gating of the processor's core clock. This signal asserts before and deasserts after the STP_CPU# signal to effectively stop the processor's clock (internally) in the states in which STP_CPU# can be used to stop the processor's clock externally. Intel (R) ICH7 Family Datasheet 151 Functional Description 5.13.2 5.13.2.1 Dual-Processor Issues (Desktop Only) Signal Differences In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. Table 5-24. DP Signal Differences Signal A20M# / A20GATE STPCLK# FERR# / IGNNE# Difference Generally not used, but still supported by Intel(R) ICH7. Used for S1 State as well as preparation for entry to S3-S5 Also allows for THERM# based throttling (not via ACPI control methods). Should be connected to both processors. Generally not used, but still supported by ICH7. 5.13.2.2 Power Management For multiple-processor (or Multiple-core) configurations in which more than one Stop Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and only pass the last one through to the ICH7. This prevents the ICH7 from getting out of sync with the processor on multiple STPCLK# assertions. Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected to both processors. However, for ACPI implementations, the BIOS must indicate that the ICH7 only supports the C1 state for dual-processor designs. In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by the processors. The ICH7 also has the option to assert the processor's SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the transition to the S1 state), the processors will not be executing code that is likely to delay the Stop-Grant cycles. In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the processors will have their power restored. 152 Intel (R) ICH7 Family Datasheet Functional Description 5.14 5.14.1 Power Management (D31:F0) Features * Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI) providing power and thermal management -- ACPI 24-Bit Timer -- Software initiated throttling of processor performance for Thermal and Power Reduction -- Hardware Override to throttle processor performance if system too hot -- SCI and SMI# Generation * PCI PME# signal for Wake Up from Low-Power states * System Clock Control -- (Mobile/Ultra Mobile Only) ACPI C2 state: Stop Grant (using STPCLK# signal) halts processor's instruction stream -- (Mobile/Ultra Mobile Only) ACPI C3 State: Ability to halt processor clock (but not memory clock) -- (Mobile/Ultra Mobile Only) ACPI C4 State: Ability to lower processor voltage. -- (Mobile/Ultra Mobile Only) CLKRUN# Protocol for PCI Clock Starting/Stopping * System Sleep State Control -- ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor's instruction stream (only STPCLK# active, and CPUSLP# optional) -- ACPI S3 state -- Suspend to RAM (STR) -- ACPI S4 state -- Suspend-to-Disk (STD) -- ACPI G2/S5 state -- Soft Off (SOFF) -- Power Failure Detection and Recovery * Streamlined Legacy Power Management for APM-Based Systems 5.14.2 Intel(R) ICH7 and System Power States Table 5-25 shows the power states defined for ICH7-based platforms. The state names generally match the corresponding ACPI states. Table 5-25. General Power States for Systems Using Intel(R) ICH7 (Sheet 1 of 2) State/ Substates Legacy Name / Description Full On: Processor operating. Individual devices may be shut down to save power. The different processor operating levels are defined by Cx states, as shown in Table 5-26. Within the C0 state, the Intel(R) ICH7 can throttle the processor using the STPCLK# signal to reduce power consumption. The throttling can be initiated by software or by the operating system or BIOS. Auto-Halt: Processor has executed an AutoHalt instruction and is not executing code. The processor snoops the bus and maintains cache coherency. Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains cache coherency. G0/S0/C0 G0/S0/C1 G0/S0/C2 (Mobile/Ultra Mobile Only) Intel (R) ICH7 Family Datasheet 153 Functional Description Table 5-25. General Power States for Systems Using Intel(R) ICH7 (Sheet 2 of 2) State/ Substates Legacy Name / Description Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts its instruction stream. ICH7 then asserts DPSLP# followed by STP_CPU#, which forces the clock generator to stop the processor clock. This is also used for Intel SpeedStep(R) technology support. Accesses to memory (by graphics, PCI, or internal units) is not permitted while in a C3 state. Stop-Clock with Lower Processor Voltage: This closely resembles the G0/ S0/C3 state. However, after the ICH7 has asserted STP_CPU#, it then lowers the voltage to the processor. This reduces the leakage on the processor. Prior to exiting the C4 state, the ICH7 increases the voltage to the processor. Stop-Grant: Similar to G0/S0/C2 state. ICH7 also has the option to assert the CPUSLP# signal to further reduce processor power consumption (Desktop only). Note: The behavior for this state is slightly different when supporting iA64 processors. Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock. Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No "Wake" events are possible, because the system does not have any power. This state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the "waking" logic. When system power returns, transition will depends on the state just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-33 for more details. G0/S0/C3 (Mobile/Ultra Mobile Only) G0/S0/C4 (Mobile/Ultra Mobile Only) G1/S1 G1/S3 G1/S4 G2/S5 G3 Table 5-26 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/ C2 states. These intermediate transitions and states are not listed in the table. 154 Intel (R) ICH7 Family Datasheet Functional Description Table 5-26. State Transition Rules for Intel(R) ICH7 Present State * * * Transition Trigger Processor halt instruction Level 2 Read Level 3 Read (Mobile/Ultra Mobile Only) Level 4 Read (Mobile/Ultra Mobile Only) SLP_EN bit set Power Button Override Mechanical Off/Power Failure Any Enabled Break Event STPCLK# goes active Power Button Override Power Failure Any Enabled Break Event Power Button Override Power Failure Previously in C3/C4 and bus masters idle Any Enabled Break Event Any Bus Master Event Power Button Override Power Failure Previously in C4 and bus masters idle * * * Next State G0/S0/C1 G0/S0/C2 G0/S0/C2, G0/S0/C3 or G0/S0/C4 depending on C4onC3_EN bit (D31:F0:Offset A0h:bit 7) and BM_STS_ZERO_EN bit (D31:F0:Offset A9h:bit 2) (Mobile/Ultra Mobile Only) G1/Sx or G2/S5 state G2/S5 G3 G0/S0/C0 G0/S0/C2 G2/S5 G3 G0/S0/C0 G2/S5 G3 C3 or C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4) G0/S0/C0 G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0 G2/S5 G3 C4 - depending on PDME bit (D31:F0: Offset A9h: bit 4 G0/S0/C0 G0/S0/C2 - if PUME bit (D31:F0: Offset A9h: bit 3) is set, else G0/S0/C0 G2/S5 G3 G0/S0/C0 (See Note 2) G2/S5 G3 G0/S0/C0 (See Note 2) G3 Optional to go to S0/C0 (reboot) or G2/S5 (stay off until power button pressed or other wake event). (See Note 1 and 2) G0/S0/C0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * G0/S0/C1 G0/S0/C2 (Mobile/ Ultra Mobile Only) G0/S0/C3 (Mobile/ Ultra Mobile Only) G0/S0/C4 (Mobile/ Ultra Mobile Only) G1/S1, G1/S3, or G1/S4 G2/S5 G3 * * * * * * * * * * * * * * * Any Enabled Break Event Any Bus Master Event Power Button Override Power Failure Any Enabled Wake Event Power Button Override Power Failure Any Enabled Wake Event Power Failure Power Returns NOTES: 1. Some wake events can be preserved through power failure. 2. Transitions from the S1-S5 or G3 states to the S0 state are deferred until BATLOW# is inactive in mobile/Ultra Mobile configurations. Intel (R) ICH7 Family Datasheet 155 Functional Description 5.14.3 System Power Planes The system has several independent power planes, as described in Table 5-27. Note that when a particular power plane is shut off, it should go to a 0 V level. s Table 5-27. System Power Plane Plane Controlled By Description The SLP_S3# signal can be used to cut the power to the processor completely. For mobile/Ultra Mobile systems, the DPRSLPVR support allows lowering the processor's voltage during the C4 state. CPU SLP_S3# signal S3HOT: The new S3HOT state keeps more of the platform logic, including the Intel(R) ICH7 core well, powered to reduce the cost of external power plane logic. SLP_S3# is only used to remove power to the processor and to shut system clocks. This impacts the board design, but there is no specific ICH7 bit or strap needed to indicate which option is selected. S3COLD: When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut off when the Main power plane is shut, although there may be small subsections powered. S3HOT: SLP_S4# is used to cut the main power well, rather than using SLP_S3#. This impacts the board design, but there is no specific ICH7 bit or strap needed to indicate which option is selected. When the SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut. Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. SLP_S3# signal (S3COLD) MAIN or SLP_S4# signal (S3HOT) MEMORY SLP_S4# signal SLP_S5# signal DEVICE[n] GPIO 5.14.4 SMI#/SCI Generation On any SMI# event taking place, ICH7 asserts SMI# to the processor, which causes it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again. The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt. 156 Intel (R) ICH7 Family Datasheet Functional Description In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 10.1.14). The interrupt remains asserted until all SCI sources are removed. Table 5-28 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding enable and status bit. Table 5-28. Causes of SMI# and SCI (Sheet 1 of 2) Cause1-5 PME# PME_B0 (internal EHCI controller) PCI Express* PME Messages (Desktop and Mobile) PCI Express Hot Plug Message (Desktop and Mobile) Power Button Press Power Button Override ) RTC Alarm Ring Indicate AC '97 wakes (Desktop and Mobile) USB#1 wakes USB#2 wakes USB#3 wakes USB#4 wakes THRM# pin active ACPI Timer overflow (2.34 sec.) Any GPI7 TCO SCI Logic TCO SCI message from (G)MCH TCO SMI Logic TCO SMI -- Year 2000 Rollover TCO SMI -- TCO TIMEROUT TCO SMI -- OS writes to TCO_DAT_IN register TCO SMI -- Message from (G)MCH 6 SCI Yes Yes Yes SMI Yes Yes Yes Additional Enables PME_EN=1 PME_B0_EN=1 PCI_EXP_EN=1 (Not enabled for SMI) HOT_PLUG_EN=1 (Not enabled for SMI) PWRBTN_EN=1 None RTC_EN=1 RI_EN=1 AC97_EN=1 USB1_EN=1 USB2_EN=1 USB3_EN=1 USB4_EN=1 THRM_EN=1 TMROF_EN=1 GPI[x]_Route=10 (SCI) GPI[x]_Route=01 (SMI) GPE0[x]_EN=1 TCOSCI_EN=1 none TCO_EN=1 none none none none Where Reported PME_STS PME_B0_STS PCI_EXP_STS Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes HOT_PLUG_STS PWRBTN_STS PRBTNOR_STS RTC_STS RI_STS AC97_STS USB1_STS USB2_STS USB3_STS USB4_STS THRM_STS TMROF_STS GPI[x]_STS GPE0_STS TCOSCI_STS MCHSCI_STS TCO_STS NEWCENTURY_STS TIMEOUT OS_TCO_SMI MCHSMI_STS Yes Yes Yes No No No No No Yes No No Yes Yes Yes Yes Yes Intel (R) ICH7 Family Datasheet 157 Functional Description Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2) Cause1-5 TCO SMI -- NMI occurred (and NMIs mapped to SMI) TCO SMI -- INTRUDER# signal goes active TCO SMI -- Change of the BIOSWP bit from 0 to 1 TCO SMI -- Write attempted to BIOS BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message SMBus SMBALERT# signal active SMBus Host Notify message received (Mobile/Ultra Mobile Only) BATLOW# assertion Access microcontroller 62h/ 66h SLP_EN bit written to 1 SCI No No No No Yes No No No No No No No No No No No No No Yes No No SMI Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Additional Enables NMI2SMI_EN=1 INTRD_SEL=10 BLD=1 BIOSWP=1 GBL_EN=1 BIOS_EN=1 APMC_EN = 1 PERIODIC_EN=1 SWSMI_TMR_EN=1 LEGACY_USB2_EN = 1 INTEL_USB2_EN = 1 LEGACY_USB_EN=1 none none SMB_SMI_EN Host Controller Enabled none none HOST_NOTIFY_INTREN BATLOW_EN=1. MCSMI_EN SMI_ON_SLP_EN=1 Where Reported NMI2SMI_STS INTRD_DET BIOSWR_STS BIOSWR_STS GBL_STS BIOS_STS APM_STS PERIODIC_STS SWSMI_TMR_STS LEGACY_USB2_STS INTEL_USB2_STS LEGACY_USB_STS SERIRQ_SMI_STS DEVMON_STS, DEVACT_STS SMBus host status reg. SMBUS_SMI_STS SMBUS_SMI_STS SMBUS_SMI_STS HOST_NOTIFY_STS BATLOW_STS MCSMI_STS SMI_ON_SLP_EN_STS NOTES: 1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI. 2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode). 3. GBL_SMI_EN must be 1 to enable SMI. 4. EOS must be written to 1 to re-enable SMI for the next 1. 5. IICH7 must have SMI# fully enabled when ICH7 is also enabled to trap cycles. If SMI# is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. When a power button override first occurs, the system will transition immediately to S5. The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting SCI_EN. 7. Only GPI[15:0] may generate an SMI# or SCI. 158 Intel (R) ICH7 Family Datasheet Functional Description 5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, the ICH7 will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the ICH7 can cause an SCI via the GPE1_STS register. 5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1 register. It is also capable of generating an SMI. However, it is not capable of generating a wake event. 5.14.5 Dynamic Processor Clock Control The ICH7 has extensive control for dynamically starting and stopping system clocks. The clock control is used for transitions among the various S0/Cx states, and processor throttling. Each dynamic clock control method is described in this section. The various sleep states may also perform types of non-dynamic clock control. The ICH7 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3 and C4 (in mobile/Ultra Mobile) states. The Dynamic Processor Clock control is handled using the following signals: * STPCLK#: Used to halt processor instruction stream. * (Mobile/Ultra Mobile Only) STP_CPU#: Used to stop processor's clock * (Mobile/Ultra Mobile Only) DPSLP#: Used to force Deeper Sleep for processor. * (Mobile/Ultra Mobile Only) DPRSLPVR: Used to lower voltage of VRM during C4 state. * (Mobile/Ultra Mobile Only) DPRSTP#: Used to lower voltage of VRM during C4 state The C1 state is entered based on the processor performing an auto halt instruction. (Mobile/Ultra Mobile Only) The C2 state is entered based on the processor reading the Level 2 register in the ICH7. It can also be entered from C3 or C4 states if bus masters require snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set. (Mobile/Ultra Mobile Only) The C3 state is entered based on the processor reading the Level 3 register in the ICH7 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7). This state can also be entered after a temporary return to C2 from a prior C3 or C4 state. (Mobile/Ultra Mobile Only) The C4 state is entered based on the processor reading the Level 4 register in the ICH7, or by reading the Level 3 register when the C4onC3_EN bit is set. This state can also be entered after a temporary return to C2 from a prior C4 state. A C1 state in desktop only or a C1, C2, C3, or C4 state in mobile/Ultra Mobile only ends due to a Break event. Based on the break event, the ICH7 returns the system to C0 state. (Mobile/Ultra Mobile Only) Table 5-29 lists the possible break events from C2, C3, or C4. The break events from C1 are indicated in the processor's datasheet. Intel (R) ICH7 Family Datasheet 159 Functional Description Table 5-29. Break Events (Mobile/Ultra Mobile Only) Event Any unmasked interrupt goes active Any internal event that cause an NMI or SMI# Any internal event that cause INIT# to go active Any bus master request (internal, external or DMA, or BM_BUSY#) goes active and BM_RLD=1 (D31:F0:Offset PMBASE+04h: bit 1) Breaks from C2, C3, C4 Comment IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC. Since SCI is an interrupt, any SCI will also be a break event. Many possible sources Could be indicated by the keyboard controller via the RCIN input signal. Need to wake up processor so it can do snoops NOTE: If the PUME bit (D31:F0: Offset A9h: bit 3) is set, then bus master activity will NOT be treated as a break event. Instead, there will be a return only to the C2 state. Only available if FERR# enabled for break event indication (See FERR# Mux Enable in GCS, Chipset Config Registers:Offset 3410h:bit 6) C2, C3, C4 C2, C3, C4 C3, C4 Processor Pending Break Event Indication C2, C3, C4 5.14.5.1 Transition Rules among S0/Cx and Throttling States The following priority rules and assumptions apply among the various S0/Cx and throttling states: * Entry to any S0/Cx state is mutually exclusive with entry to any S1-S5 state. This is because the processor can only perform one register access at a time and Sleep states have higher priority than thermal throttling. * When the SLP_EN bit is set (system going to a S1-S5 sleep state), the THTL_EN and FORCE_THTL bits can be internally treated as being disabled (no throttling while going to sleep state). * (Mobile/Ultra Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3, or Level 4 read then occurs, the system should immediately go and stay in a C2, C3, or C4 state until a break event occurs. A Level 2, Level 3, or Level 4 read has higher priority than the software initiated throttling. * (Mobile/Ultra Mobile Only) After an exit from a C2, C3, or C4 state (due to a Break event), and if the THTL_EN or FORCE_THTL bits are still set the system will continue to throttle STPCLK#. Depending on the time of break event, the first transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI clocks = 30.72 s). * The Host controller must post Stop-Grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the ICH7 observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase. * (Mobile/Ultra Mobile Only) If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should return to the C1 state. 160 Intel (R) ICH7 Family Datasheet Functional Description 5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) Due to the new DMI protocol, if there is any bus master activity (other than true isoch), then the C0-to-C3 transition will pause at the C2 state. ICH7 will keep the processor in a C2 state until: * ICH7 does not detect bus master activity. * A break event occurs. In this case, the ICH7 will perform the C2 to C0 sequence. Note that bus master traffic is not a break event in this case. To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be set. This will cause the BM_STS bit to read as 0 even if some bus master activity is present. If this is not done, then the software may avoid even attempting to go to the C3 or C4 state if it sees the BM_STS bit as 1. If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH7 will treat bus master activity as a break event. When reaching the C2 state, if there is any bus master activity, the ICH7 will return the processor to a C0 state. 5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH7 enables a mode of operation where standard (non-isoch) bus master activity will not be treated as a full break event from the C3 or C4 states. Instead, these will be treated merely as bus master events and return the platform to a C2 state, and thus allow snoops to be performed. After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even if the ARB_DIS bit is set. 5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4) is set, the platform can return to a C3 or C4 state (depending on where it was prior to going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will keep the processor in a C2 state until: * Bus masters are no longer active. * A break event occurs. Note that bus master traffic is not a break event in this case. 5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only) The PCI clock can be dynamically controlled independent of any other low-power state. This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design Guide, and is transparent to software. The Dynamic PCI Clock control is handled using the following signals: * CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run * STP_PCI#: Used to stop the system PCI clock Note: The 33 MHz clock to the ICH7 is "free-running" and is not affected by the STP_PCI# signal. Intel (R) ICH7 Family Datasheet 161 Functional Description 5.14.6.1 Conditions for Checking the PCI Clock When there is a lack of PCI activity the ICH7 has the capability to stop the PCI clocks to conserve power. "PCI activity" is defined as any activity that would require the PCI clock to be running. Any of the following conditions will indicate that it is not okay to stop the PCI clock: * Cycles on PCI or LPC * Cycles of any internal device that would need to go on the PCI bus * SERIRQ activity Behavioral Description * When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH7 deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal. 5.14.6.2 Conditions for Maintaining the PCI Clock PCI masters or LPC devices that wish to maintain the PCI clock running will observe the CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks. * When the ICH7 has tri-stated the CLKRUN# signal after deasserting it, the ICH7 then checks to see if the signal has been re-asserted (externally). * After observing the CLKRUN# signal asserted for 1 clock, the ICH7 again starts asserting the signal. * If an internal device needs the PCI bus, the ICH7 asserts the CLKRUN# signal. 5.14.6.3 Conditions for Stopping the PCI Clock * If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks, the ICH7 stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer. 5.14.6.4 Conditions for Re-Starting the PCI Clock * A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started. * When the ICH7 observes the CLKRUN# signal asserted for 1 (free running) clock, the ICH7 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks. * Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH7 again starts driving CLKRUN# asserted. If an internal source requests the clock to be re-started, the ICH7 re-asserts CLKRUN#, and simultaneously deasserts the STP_PCI# signal. 5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA (Mobile only) or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles will not need to assert CLKRUN#, since the ICH7 asserts it on their behalf. The LDRQ# inputs are ignored by the ICH7 when the PCI clock is stopped to the LPC devices in order to avoid misinterpreting the request. The ICH7 assumes that only one more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#. Upon deassertion of STP_PCI#, the ICH7 assumes that the LPC device receives its first clock rising edge corresponding to the ICH7's second PCI clock rising edge after the deassertion. 162 Intel (R) ICH7 Family Datasheet Functional Description 5.14.7 5.14.7.1 Sleep States Sleep State Overview The ICH7 directly supports different sleep states (S1-S5) that are entered by setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several assumptions: * Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the processor can only perform one register access at a time. A request to Sleep has higher priority than throttling. * Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal throttling (since S1-S5 sleep state has higher priority). * The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power. 5.14.7.2 Initiating Sleep State Sleep states (S1-S5) are initiated by: * Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state. * Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock. Table 5-30. Sleep Types Sleep Type S1 Comment Intel(R) ICH7 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal (only supported on desktop platforms). This lowers the processor's power consumption. No snooping is possible in this state. ICH7 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory. ICH7 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. Same power state as S4. ICH7 asserts SLP_S3#, SLP_S4# and SLP_S5#. S3 S4 S5 5.14.7.3 Exiting Sleep States Sleep states (S1-S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state, and have to be enabled via a GPIO pin before it can be used. Upon exit from the ICH7-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-31. Note: (Mobile/Ultra Mobile Only) If the BATLOW# signal is asserted, ICH7 does not attempt to wake from an S1-S5 state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the ICH7, and the system wakes after BATLOW# is de-asserted. Intel (R) ICH7 Family Datasheet 163 Functional Description Table 5-31. Causes of Wake Events Cause RTC Alarm Power Button States Can Wake From1 S1-S52 S1-S5 How Enabled Set RTC_EN bit in PM1_EN register Always enabled as Wake event GPE0_EN register GPI[0:15] S1-S52 NOTE: GPIs that are in the core well are not capable of waking the system from sleep states where the core well is not powered. Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in GPE0_EN register Will use PME#. Wake enable set with LAN logic. Set RI_EN bit in GPE0_EN register Set AC97_EN bit in GPE0_EN register PME_B0_EN bit in GPE0_EN register Set PME_EN bit in GPE0_EN register. PCI_EXP_WAKE bit3 Classic USB LAN (Desktop and Mobile only) RI# AC `97 / Intel High Definition Audio Primary PME# Secondary PME# PCI_EXP_WAKE# (Desktop and Mobile only) PCI_EXP PME Message (Desktop and Mobile only) SMBALERT# SMBus Slave Message SMBus Host Notify message received (R) S1-S5 S1-S5 S1-S52 S1-S52 S1-S5 S1-S5 S1-S5 S1 S1-S5 S1-S5 Must use the PCI Express* WAKE# pin rather than messages for wake from S3,S4, or S5. Always enabled as Wake event Wake/SMI# command always enabled as a Wake event. Note: SMBus Slave Message can wake the system from S1- S5, as well as from S5 due to Power Button Override. HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. S1-S5 NOTES: 1. If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in Table 5-55), and Hard Reset System (See Command Type 4 in Table 5-55). 2. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits via software, or if there is a power failure. 3. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, the ICH7 will wake the platform. 164 Intel (R) ICH7 Family Datasheet Functional Description It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Also, only certain GPIs are "ACPI Compliant," meaning that their Status and Enable bits reside in ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events. Table 5-32. GPI Wake Events GPI GPI[12, 7:0] GPI[15:13,11:8] Power Well Core Resume Wake From S1 S1-S5 Notes ACPI Compliant ACPI Compliant The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH7 are insignificant. 5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (Desktop and Mobile only) PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register. PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages. When a PME message is received, ICH7 will set the PCI_EXP_STS bit. 5.14.7.5 Sx-G3-Sx, Handling Power Failures Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. The AFTER_G3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure. 1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state), the PWRBTN_STS bit is reset. When the ICH7 exits G3 after power returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCCstandby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0. 2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit is set and the system interprets that as a wake event. 3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. The ICH7 monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Intel (R) ICH7 Family Datasheet 165 Functional Description Table 5-33. Transitions Due to Power Failure State at Power Failure S0, S1, S3 S4 S5 AFTERG3_EN bit 1 0 1 0 1 0 Transition When Power Returns S5 S0 S4 S0 S5 S0 5.14.8 Thermal Management The ICH7 has mechanisms to assist with managing thermal problems in the system. 5.14.8.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going active, the ICH7 generates an SMI# or SCI (depending on SCI_EN). If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit will be set. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be generated (depending on the SCI_EN bit being set). The power management software (BIOS or ACPI) can then take measures to start reducing the temperature. Examples include shutting off unwanted subsystems, or halting the processor. By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to turn off the cooling methods. Note: THRM# assertion does not cause a TCO event message in S3 or S4. The level of the signal is not reported in the heartbeat message. 5.14.8.2 Processor Initiated Passive Cooling This mode is initiated by software setting the THTL_EN (PMBASE+10h:bit 4) or FORCE_THTL (PMBASE+10h:bit 8) bits. Software sets the THTL_DTY (PMBASE+10h:bits 3:1) or THRM_DTY (PMBASE+10h:bits 7:5) bits to select throttle ratio and THTL_EN or FORCE_THTL bits to enable the throttling. Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and cooling) of the processor depends on the instruction stream, because the processor is allowed to finish the current instruction. Furthermore, the ICH7 waits for the STOPGRANT cycle before starting the count of the time the STPCLK# signal is active. 166 Intel (R) ICH7 Family Datasheet Functional Description 5.14.8.3 THRM# Override Software Bit The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH7 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared the ICH7 stops throttling, unless the THTL_EN bit is set (indicating that ACPI software is attempting throttling). If both the THTL_EN and FORCE_THTL bits are set, then the ICH7 should use the duty cycle defined by the THRM_DTY field, not the THTL_DTY field. 5.14.8.4 Active Cooling Active cooling involves fans. The GPIO signals from the ICH7 can be used to turn on/off a fan. 5.14.9 Event Input Signals and Their Usage The ICH7 has various input signals that trigger specific events. This section describes those signals and how they should be used. 5.14.9.1 PWRBTN# (Power Button) The ICH7 PWRBTN# signal operates as a "Fixed Power Button" as described in the Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in Table 5-34. Note that the transitions start as soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power Button is released. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled), the Power Button is not a wake event. Refer to Power Button Override Function section below for further detail. Table 5-34. Transitions Due to Power Button Present State S0/Cx S1-S5 G3 S0-S4 Event PWRBTN# goes low PWRBTN# goes low PWRBTN# pressed PWRBTN# held low for at least 4 consecutive seconds Transition/Action SMI# or SCI generated (depending on SCI_EN) Wake Event. Transitions to S0 state None Unconditional transition to S5 state Comment Software typically initiates a Sleep state Standard wakeup No effect since no power Not latched nor detected No dependence on processor (e.g., Stop-Grant cycles) or any other subsystem Intel (R) ICH7 Family Datasheet 167 Functional Description Power Button Override Function If PWRBTN# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the G2/S5 state, regardless of present state (S0- S4), even if PWROK is not active. In this case, the transition to the G2/S5 state should not depend on any particular response from the processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the ICH7 is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1-S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4second timer starts. During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it is conceivable that the user will press and continue to hold the Power Button waiting for the system to awake. Since a 4-second press of the Power Button is already defined as an Unconditional Power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. Once the power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4# power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the Override condition to S5. Note: Sleep Button The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1-S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot. Although the ICH7 does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a "Control Method" Sleep Button. See the Advanced Configuration and Power Interface, Version 2.0b for implementation details. 5.14.9.2 RI# (Ring Indicator) The Ring Indicator can cause a wake event (if enabled) from the S1-S5 states. Table 5-35 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH7 generates an interrupt based on RI# active, and the interrupt will be set up as a Break event. Table 5-35. Transitions Due to RI# Signal Present State S0 S1-S5 Event RI# Active RI# Active RI_EN X 0 1 Event Ignored Ignored Wake Event Note: Filtering/Debounce on RI# will not be done in ICH7. It can be in modem or external. 168 Intel (R) ICH7 Family Datasheet Functional Description 5.14.9.3 PME# (PCI Power Management Event) The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect. 5.14.9.4 SYS_RESET# Signal When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH7 attempts to perform a "graceful" reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring. Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset. 5.14.9.5 THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH7 immediately transitions to an S5 state. However, since the processor has overheated, it does not respond to the ICH7's STPCLK# pin with a stop grant special cycle. Therefore, the ICH7 does not wait for one. Immediately upon seeing THRMTRIP# low, the ICH7 initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a power button override. It is extremely important that when a THRMTRIP# event occurs, the ICH7 power down immediately without following the normal S0 -> S5 path. This path may be taken in parallel, but ICH7 must immediately enter a power down state. It does this by driving SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP# active. If the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ICH7, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active, and the ICH7 is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. The ICH7 follows this flow for THRMTRIP#. 1. At boot (PLTRST# low), THRMTRIP# ignored. 2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts. 3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if THRMTRIP# is now inactive. This is the equivalent of "latching" the thermal trip event. 4. If S5 state reached, go to step #1, otherwise stay here. If the ICH7 does not reach S5, the ICH7 does not reboot until power is cycled. Intel (R) ICH7 Family Datasheet 169 Functional Description During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and PLTRST# are all `1'. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK = 0, or VRMPWRGD/VGATE = 0. Note: A thermal trip event will: * Set the AFTERG3_EN bit * Clear the PWRBTN_STS bit * Clear all the GPE0_EN register bits * Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert 5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) The BM_BUSY# signal is an input from a graphics component to indicate if it is busy. If prior to going to the C3 state, the BM_BUSY# signal is active, then the BM_STS bit will be set. If after going to the C3 state, the BM_BUSY# signal goes back active, the ICH7 will treat this as if one of the PCI REQ# signals went active. This is treated as a break event. 5.14.10 ALT Access Mode Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the ICH7 implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the ICH7 timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: 1. BIOS enters ALT access mode for reading the ICH7 timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the operating system. After getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. For example DOS and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*) reprogram the system timer and therefore do not encounter this problem. For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode. 170 Intel (R) ICH7 Family Datasheet Functional Description 5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode The registers described in Table 5-36 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port. Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2) Restore Data I/O Addr # of Rds Access 1 00h 2 2 1 01h 2 2 1 02h 2 2 1 03h 2 2 1 04h 2 2 1 05h 2 2 1 06h 2 2 1 07h 2 2 Data DMA Chan 0 base address low byte DMA Chan 0 base address high byte DMA Chan 0 base count low byte DMA Chan 0 base count high byte DMA Chan 1 base address low byte DMA Chan 1 base address high byte DMA Chan 1 base count low byte DMA Chan 1 base count high byte DMA Chan 2 base address low byte DMA Chan 2 base address high byte DMA Chan 2 base count low byte DMA Chan 2 base count high byte DMA Chan 3 base address low byte DMA Chan 3 base address high byte DMA Chan 3 base count low byte DMA Chan 3 base count high byte 41h 42h 70h 1 1 1 1 C4h 2 2 1 C6h 2 2 1 C8h 2 2 40h 7 I/O Addr # of Rds Restore Data Access 1 2 3 4 5 6 7 Data Timer Counter 0 status, bits [5:0] Timer Counter 0 base count low byte Timer Counter 0 base count high byte Timer Counter 1 base count low byte Timer Counter 1 base count high byte Timer Counter 2 base count low byte Timer Counter 2 base count high byte Timer Counter 1 status, bits [5:0] Timer Counter 2 status, bits [5:0] Bit 7 = NMI Enable, Bits [6:0] = RTC Address DMA Chan 5 base address low byte DMA Chan 5 base address high byte DMA Chan 5 base count low byte DMA Chan 5 base count high byte DMA Chan 6 base address low byte DMA Chan 6 base address high byte Intel (R) ICH7 Family Datasheet 171 Functional Description Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data I/O Addr # of Rds Access 1 2 3 08h 6 4 5 6 1 2 3 4 5 20h 12 6 7 8 9 10 11 12 Data DMA Chan 0-3 Command2 CAh DMA Chan 0-3 Request DMA Chan 0 Mode: Bits(1:0) = 00 DMA Chan 1 Mode: Bits(1:0) = 01 DMA Chan 2 Mode: Bits(1:0) = 10 DMA Chan 3 Mode: Bits(1:0) = 11. PIC ICW2 of Master controller PIC ICW3 of Master controller PIC ICW4 of Master controller PIC OCW1 of Master controller2 PIC OCW2 of Master controller PIC OCW3 of Master controller PIC ICW2 of Slave controller PIC ICW3 of Slave controller PIC ICW4 of Slave controller PIC OCW1 of Slave controller1 PIC OCW2 of Slave controller PIC OCW3 of Slave controller D0h 6 2 2 1 CCh 2 2 1 CEh 2 2 1 2 3 4 5 6 I/O Addr # of Rds Restore Data Access 1 Data DMA Chan 6 base count low byte DMA Chan 6 base count high byte DMA Chan 7 base address low byte DMA Chan 7 base address high byte DMA Chan 7 base count low byte DMA Chan 7 base count high byte DMA Chan 4-7 Command1 DMA Chan 4-7 Request DMA Chan 4 Mode: Bits(1:0) = 00 DMA Chan 5 Mode: Bits(1:0) = 01 DMA Chan 6 Mode: Bits(1:0) = 10 DMA Chan 7 Mode: Bits(1:0) = 11. NOTES: 1. Bits 5, 3, 1, and 0 return 0. 2. The OCW1 register must be read before entering ALT access mode. 172 Intel (R) ICH7 Family Datasheet Functional Description 5.14.10.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-37. Table 5-37. PIC Reserved Bits Return Values PIC Reserved Bits ICW2(2:0) ICW4(7:5) ICW4(3:2) ICW4(0) OCW2(4:3) OCW3(7) OCW3(5) OCW3(4:3) Value Returned 000 000 00 0 00 0 Reflects bit 6 01 5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode The registers described in Table 5-38 have write paths to them in ALT access mode. Software restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the base address/count register also writes to the current address/count register. Therefore, the base address/count must be written first, then the part is put into ALT access mode and the current address/count register is written. Table 5-38. Register Write Accesses in ALT Access Mode I/O Address 08h D0h Register Write Value DMA Status Register for channels 0-3. DMA Status Register for channels 4-7. 5.14.11 5.14.11.1 System Power Supplies, Planes, and Signals Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# The usage of SLP_S3# and SLP_S4# depends on whether the platform is configured for S3HOT and S3COLD. S3HOT The SLP_S3# output signal is used to cut power only to the processor and associated subsystems and to optionally stop system clocks. S3COLD The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH7 resume well, and to any other circuits that need to generate Wake signals from the STR state. Intel (R) ICH7 Family Datasheet 173 Functional Description Cutting power to the core may be done via the power supply, or by external FETs to the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs to the motherboard. The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#. SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply, or by external FETs to the motherboard. 5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the ICH7 provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time. Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal. 5.14.11.3 PWROK Signal The PWROK input should go active based on the core supply voltages becoming valid. PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached their nominal values. Note: 1. SYSRESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets, and avoids improperly reporting power failures. 2. If the PWROK input is used to implement the system reset button, the ICH7 does not provide any mechanism to limit the amount of time that the processor is held in reset. The platform must externally ensure that maximum reset assertion specifications are met. 3. If a design has an active-low reset button electrically AND'd with the PWROK signal from the power supply and the processor's voltage regulator module the ICH7 PWROK_FLR bit will be set. The ICH7 treats this internally as if the RSMRST# signal had gone active. However, it is not treated as a full power failure. If PWROK goes inactive and then active (but RSMRST# stays high), then the ICH7 reboots (regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this is a full power failure, and the reboot policy is controlled by the AFTERG3 bit. 4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH7. 5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD. 174 Intel (R) ICH7 Family Datasheet Functional Description 5.14.11.4 CPUPWRGD Signal This signal is connected to the processor's VRM via the VRMPWRGD signal and is internally AND'd with the PWROK signal that comes from the system power supply. 5.14.11.5 VRMPWRGD Signal VRMPWRGD is an input from the regulator indicating that all of the outputs from the regulator are on and within specification. VRMPWRGD may go active before or after the PWROK from the main power supply. ICH7 has no dependency on the order in which these two signals go active or inactive. 5.14.11.6 BATLOW# (Battery Low) (Mobile/Ultra Mobile Only) The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not sufficient power. It also causes an SMI# if the system is already in an S0 state. 5.14.11.7 Controlling Leakage and Power Consumption during Low-Power States To control leakage in the system, various signals tri-state or go low during some lowpower states. General principles: * All signals going to powered down planes (either internally or externally) must be either tri-stated or driven low. * Signals with pull-up resistors should not be low during low-power states. This is to avoid the power consumed in the pull-up resistor. * Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). Floating inputs can cause extra power consumption. Based on the above principles, the following measures are taken: * During S3 (STR), all signals attached to powered down planes are tri-stated or driven low. Intel (R) ICH7 Family Datasheet 175 Functional Description 5.14.12 Clock Generators The clock generator is expected to provide the frequencies shown in Table 5-39. Table 5-39. Intel(R) ICH7 Clock Inputs Clock Domain SATA_CLK (Desktop and Mobile Only) DMI_CLK Frequency 100 MHz Differential 100 MHz Differential Source Main Clock Generator Main Clock Generator Usage Used by SATA controller. Stopped in S3 ~ S5 based on SLP_S3# assertion. Used by DMI and PCI Express*. Stopped in S3 ~ S5 based on SLP_S3# assertion. Desktop Only: Free-running PCI Clock to Intel(R) ICH7. Stopped in S3 ~ S5 based on SLP_S3# assertion. PCICLK 33 MHz Main Clock Generator Mobile Only: Free-running (not affected by STP_PCI# PCI Clock to ICH7. This is not the system PCI clock. This clock must keep running in S0 while the system PCI clock may stop based on CLKRUN# protocol. Stopped in S3 ~ S5 based on SLP_S3# assertion. Used by USB controllers and Intel(R) High Definition Audio controller. Stopped in S3 ~ S5 based on SLP_S3# assertion. Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3# assertion. AC-link. Control policy is determined by the clock source. NOTE: Becomes clock output when Intel High Definition Audio is enabled. LAN Connect Interface. Control policy is determined by the clock source. CLK48 48.000 MHz 14.318 MHz Main Clock Generator Main Clock Generator CLK14 ACZ_BIT_CLK (Desktop and Mobile) LAN_CLK (Desktop and Mobile Only) 12.288 MHz AC '97 Codec 0.8 to 50 MHz LAN Connect 5.14.12.1 Clock Control Signals from Intel(R) ICH7 to Clock Synthesizer (Mobile/Ultra Mobile Only) The clock generator is assumed to have a direct connection from the following ICH7 signals: * STP_CPU#: Stops processor clocks in C3 and C4 states * STP_PCI#: Stops system PCI clocks (not the ICH7 free-running 33 MHz clock) due to CLKRUN# protocol * SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop clocks in S3HOT and on the way to S3COLD to S5. 176 Intel (R) ICH7 Family Datasheet Functional Description 5.14.13 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The ICH7 does not support burst modes. 5.14.13.1 APM Power Management (Desktop Only) The ICH7 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, generates an SMI# once per minute. The SMI handler can check for system activity by reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the SMI handler can then put the system into a lower power state. If there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by writing a 1 to the bit position. The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts. 5.14.13.2 Mobile APM Power Management (Mobile/Ultra Mobile Only) In mobile/ultra mobile systems, there are additional requirements associated with device power management. To handle this, the ICH7 has specific SMI# traps available. The following algorithm is used: 1. The periodic SMI# timer checks if a device is idle for the required time. If so, it puts the device into a low-power state and sets the associated SMI# trap. 2. When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle does not really go to the device and an SMI# is generated). 3. The SMI# handler turns on the device and turns off the trap The SMI# handler exits with an I/O restart. This allows the original software to continue. Intel (R) ICH7 Family Datasheet 177 Functional Description 5.15 System Management (D31:F0) The ICH7 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. In addition, ICH7 provides integrated ASF Management support. Features and functions can be augmented via external A/D converters and GPIO, as well as an external microcontroller. The following features and functions are supported by the ICH7: * Processor present detection -- Detects if processor fails to fetch the first instruction after reset * Various Error detection (such as ECC Errors) Indicated by host controller -- Can generate SMI#, SCI, SERR, NMI, or TCO interrupt * Intruder Detect input -- Can generate TCO interrupt or SMI# when the system cover is removed -- INTRUDER# allowed to go active in any power state, including G3 * Detection of bad Firmware Hub programming -- Detects if data on first read is FFh (indicates unprogrammed Firmware Hub) * Ability to hide a PCI device -- Allows software to hide a PCI device in terms of configuration space through the use of a device hide register (See Section 7.1.56) * Integrated ASF Management support (Desktop and Mobile Only) Note: Voltage ID from the processor can be read via GPI signals. 5.15.1 Theory of Operation The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller. 5.15.1.1 Detecting a System Lockup When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and the ICH7 asserts PLTRST#. 5.15.1.2 Handling an Intruder The ICH7 has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system's case being open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH7 to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit. The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. 178 Intel (R) ICH7 Family Datasheet Functional Description If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the ICH7's RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65 s) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set. If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit remains set and the SMI is generated again immediately. The SMI handler can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated. Note: 5.15.1.3 Detecting Improper Firmware Hub Programming The ICH7 can detect the case where the Firmware Hub is not programmed. This results in the first instruction fetched to have a value of FFh. If this occurs, the ICH7 sets the BAD_BIOS bit, which can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN* enabled LAN controller (See Section 5.15.2). 5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) The ICH7 integrated LAN controller supports ASF heartbeat and event reporting functionality when used with the 82562EM or 82562EX Platform LAN Connect component. This allows the integrated LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. All heartbeat and event messages are sent on the SMBus interface. This allows an external LAN controller to act upon these messages if the internal LAN controller is not used. The basic scheme is for the ICH7 integrated LAN controller to send a prepared Ethernet message to a network management console. The prepared message is stored in the non-volatile EEPROM that is connected to the ICH7. Messages are sent by the LAN controller either because a specific event has occurred, or they are sent periodically (also known as a heartbeat). The event and heartbeat messages have the exact same format. The event messages are sent based on events occurring. The heartbeat messages are sent every 30 to 32 seconds. When an event occurs, the ICH7 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment. Intel (R) ICH7 Family Datasheet 179 Functional Description The following rules/steps apply if the system is in a G0 state and the policy is for the ICH7 to reboot the system after a hardware lockup: 1. On detecting the lockup, the SECOND_TO_STS bit is set. The ICH7 may send up to 1 Event message to the LAN controller. The ICH7 then attempts to reboot the processor. 2. If the reboot at step 1 is successful then the BIOS should clear the SECOND_TO_STS bit. This prevents any further Heartbeats from being sent. The BIOS may then perform addition recovery/boot steps. (See note 2, below.) 3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time. At this point the system has locked up and was unsuccessful in rebooting. The ICH7 does not attempt to automatically reboot again. The ICH7 starts sending a message every heartbeat period (30-32 seconds). The heartbeats continue until some external intervention occurs (reset, power failure, etc.). 4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH7 continues sending the messages every heartbeat period. 5. After step 4 (power button override after unsuccessful reboot) if the user presses the Power Button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. If step 5 (power button press) is successful in waking the system, the ICH7 continues sending messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2) 7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7 continues sending a message every heartbeat period. The ICH7 does not attempt to automatically reboot again. The ICH7 starts sending a message every heartbeat period (30-32 seconds). The heartbeats continue until some external intervention occurs (reset, power failure, etc.). (See note 3) 8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to reset the system. 9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. The ICH7 continues sending a message every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2) 10. After step 8 (reset attempt), if the reset is unsuccessful, the ICH7 continues sending a message every heartbeat period. The ICH7 does not attempt to reboot the system again without external intervention. (See note 3) The following rules/steps apply if the system is in a G0 state and the policy is for the ICH7 to not reboot the system after a hardware lockup. 1. On detecting the lockup the SECOND_TO_STS bit is set. The ICH7 sends a message with the Watchdog (WD) Event status bit set (and any other bits that must also be set). This message is sent as soon as the lockup is detected, and is sent with the next (incremented) sequence number. 2. After step 1, the ICH7 sends a message every heartbeat period until some external intervention occurs. 3. Rules/steps 4-10 apply if no user intervention (resets, power button presses, SMBus reset messages) occur after a third timeout of the watchdog timer. If the intervention occurs before the third timeout, then jump to rule/step 11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH7 continues sending heartbeats at this point. 180 Intel (R) ICH7 Family Datasheet Functional Description 5. After step 4 (power button override), if the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 6. If step 5 (power button press) is successful in waking the system, the ICH7 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7 continues sending heartbeats. The ICH7 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (See note 3) 8. After step 3 (third timeout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to reset the system. 9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH7 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 10. If step 8 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats. The ICH7 does not attempt to reboot the system again without external intervention. Note: A system that has locked up and can not be restarted with power button press is probably broken (bad power supply, short circuit on some bus, etc.) 11. This and the following rules/steps apply if the user intervention (power button press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog timer. 12. After step 1 (second timeout), if the user does a Power Button Override, the system goes to an S5 state. The ICH7 continues sending heartbeats at this point. 13. After step 12 (power button override), if the user presses the power button again, the system should wake to an S0 state and the processor should start executing the BIOS. 14. If step 13 (power button press) is successful in waking the system, the ICH7 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 15. If step 13 (power button press) is unsuccessful in waking the system, the ICH7 continues sending heartbeats. The ICH7 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (See note 3) 16. After step 1 (second timeout), if a reset is attempted (using a button that pulses PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to reset the system. 17. If step 16 (reset attempt) is successful, the BIOS is run. The ICH7 continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2) 18. If step 16 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats. The ICH7 does not attempt to reboot the system again without external intervention. (See note 3) If the system is in a G1 (S1-S4) state, the ICH7 sends a heartbeat message every 30- 32 seconds. If an event occurs prior to the system being shutdown, the ICH7 immediately sends an event message with the next incremented sequence number. After the event message, the ICH7 resumes sending heartbeat messages. Intel (R) ICH7 Family Datasheet 181 Functional Description Note: Notes for previous two numbered lists. 1. Normally, the ICH7 does not send heartbeat messages while in the G0 state (except in the case of a lockup). However, if a hardware event (or heartbeat) occurs just as the system is transitioning into a G0 state, the hardware continues to send the message even though the system is in a G0 state (and the status bits may indicate this). These messages are sent via the SMBus. The ICH7 abides by the SMBus rules associated with collision detection. It delays starting a message until the bus is idle, and detects collisions. If a collision is detected the ICH7 waits until the bus is idle, and tries again. 2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the LAN device driver from working properly. The alerts reset part of the LAN controller and would prevent an operating system's device driver from sending or receiving some messages. 3. A system that has locked up and can not be restarted with power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond ICH7's recovery mechanisms. 4. A spurious alert could occur in the following sequence: -- The processor has initiated an alert using the SEND_NOW bit -- During the alert, the THRM#, INTRUDER# or GPIO11 changes state -- The system then goes to a non-S0 state. Once the system transitions to the non-S0 state, it may send a single alert with an incremental SEQUENCE number. 5. An inaccurate alert message can be generated in the following scenario -- The system successfully boots after a second watchdog Timeout occurs. -- PWROK goes low (typically due to a reset button press) or a power button override occurs (before the SECOND_TO_STS bit is cleared). -- An alert message indicating that the processor is missing or locked up is generated with a new sequence number. Table 5-40 shows the data included in the Alert on LAN messages. Table 5-40. Heartbeat Message Data (Sheet 1 of 2) Field Cover Tamper Status Temp Event Status Processor Missing Event Status TCO Timer Event Status Software Event Status Unprogrammed Firmware Hub Event Status GPIO Status Comment 1 = This bit is set if the intruder detect bit is set (INTRD_DET). 1 = This bit is set if the Intel(R) ICH7 THERM# input signal is asserted. 1 = This bit is set if the processor failed to fetch its first instruction. 1 = This bit is set when the TCO timer expires. 1 = This bit is set when software writes a 1 to the SEND_NOW bit. 1 = First BIOS fetch returned a value of FFh, indicating that the Firmware Hub has not yet been programmed (still erased). 1 = This bit is set when GPIO11 signal is high. 0 = This bit is cleared when GPIO11 signal is low. An event message is triggered on an transition of GPIO11. 182 Intel (R) ICH7 Family Datasheet Functional Description Table 5-40. Heartbeat Message Data (Sheet 2 of 2) Field SEQ[3:0] System Power State MESSAGE1 MESSAGE2 WDSTATUS Comment This is a sequence number. It initially is 0, and increments each time the ICH7 sends a new message. Upon reaching 1111, the sequence number rolls over to 0000. MSB (SEQ3) sent first. 00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first Will be the same as the MESSAGE1 Register. MSB sent first. Will be the same as the MESSAGE2 Register. MSB sent first. Will be the same as the WDSTATUS Register. MSB sent first. 5.16 IDE Controller (D31:F1) The ICH7 IDE controller features one sets of interface signals that can be enabled, tristated or driven low. The IDE interfaces of the ICH7 can support several types of data transfers: * Programmed I/O (PIO): Processor is in control of the data transfer. * 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not use the 8237 in the ICH7. This protocol off loads the processor from moving data. This allows higher transfer rate of up to 16 MB/s. * Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 33 MB/s. * Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 66 MB/s. * Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s. Note: ICH7-U Ultra Mobile only supports one IDE device. 5.16.1 PIO Transfers The ICH7 IDE controller includes both compatible and fast timing modes. The fast timing modes can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in single transaction mode with compatible timings. Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1); one device (connector drive 0) on ICH7-U Ultra Mobile. The IDE_TIMP and IDE_TIMS Registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector. The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are executed with the synchronous DMA timings. The PIO transfers are executed using compatible timings or fast timings if also enabled. Intel (R) ICH7 Family Datasheet 183 Functional Description 5.16.1.1 PIO IDE Timing Modes IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of the read and write strobes (DIOR# and DIOW#). Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery time is provided so that transactions may occur back-to-back on the IDE interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the IDE interface. The command strobe assertion width for the enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set to 1, 2, 3, or 4 PCI clocks. If IORDY is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. If IORDY is negated when the initial sample point is reached, additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least two additional PCI clocks are added. Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and DIOW#). Shutdown latency is two PCI clocks in duration. The IDE timings for various transaction types are shown in Table 5-41. Table 5-41. IDE Transaction Timings (PCI Clocks) IDE Transaction Type Non-Data Port Compatible Data Port Compatible Fast Timing Mode Startup Latency 4 3 2 IORDY Sample Point (ISP) 11 6 2-5 Recovery Time (RCT) 22 14 1-4 Shutdown Latency 2 2 2 5.16.1.2 IORDY Masking The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on a drive by drive basis via the IDETIM Register. 5.16.1.3 PIO 32-Bit IDE Data Port Accesses A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled for all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is incurred between the two, 16-bit halves of the IDE transaction. This ensures that the chip selects are deasserted for at least two PCI clocks between the two cycles. 184 Intel (R) ICH7 Family Datasheet Functional Description 5.16.1.4 PIO IDE Data Port Prefetching and Posting The ICH7 can be programmed via the IDETIM registers to allow data to be posted to and prefetched from the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to the IDE data ports and allows them to be performed back to back for the highest possible PIO data transfer rates. The first data port read of a sector is called the demand read. Subsequent data port reads from the sector are called prefetch reads. The demand read and all prefetch reads much be of the same size (16 or 32 bits) - software must not mix 32-bit and 16-bit reads. Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI bus after the data is received by the ICH7. The ICH7 then runs the IDE cycle to transfer the data to the drive. If the ICH7 write buffer is non-empty and an unrelated (non-data or opposite channel) IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. Only 16-bit buffer writes are supported. 5.16.2 Bus Master Function The ICH7 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master channel is provided for the IDE connector. By performing the IDE data transfer as a PCI Bus master, the ICH7 off-loads the processor and improves system performance in multitasking environments. For Desktop and Mobile, both devices attached to the connector can be programmed for bus master transfers, but only one device can be active at a time. 5.16.2.1 Physical Region Descriptor Format The physical memory region to be transferred is described by a Physical Region Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until all regions described by the PRDs in the table have been transferred. Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8 bytes in length. The first 4 bytes specify the byte address of a physical memory region. This memory region must be DWord-aligned and must not cross a 64-KB boundary. The next two bytes specify the size or transfer count of the region in bytes (64-KB limit per region). A value of 0 in these two bytes indicates 64-KB (thus the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in the Descriptor table. Bus master operation terminates when the last descriptor has been retired. When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of the Base Address is not masked and if set, will cause the lower Word byte enables to be deasserted for the first DWord transfer. The write to PCI typically consists of a 32-byte cache line. If valid data ends prior to end of the cache line, the byte enables will be deasserted for invalid data. The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater than the size of the disk transfer request. If greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. Intel (R) ICH7 Family Datasheet 185 Functional Description Figure 5-8. Physical Region Descriptor Table Entry Main Memory Memory Region Byte 3 Byte 2 Byte 1 Byte 0 o o Memory Region Physical Base Address [31:1] EOT Reserved Byte Count [15:1] 5.16.2.2 Bus Master IDE Timings The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster than its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI clock and no more transfers take place until DMA request is asserted again. 5.16.2.3 Interrupts The ICH7 can generate interrupts based upon a signal coming from the PATA device, or due to the completion of a PRD with the `I' bit set. The interrupt is edge triggered and active high. The PATA host controller generates IDEIRQ. When the ICH7 IDE controller is operating independently from the SATA controller (D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV (D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA controller in combined mode is emulating the logical primary channel (MAP.MV=2h), IDEIRQ will generate IRQ15. Note: Note: IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream. The combined mode is not supported on ICH7-U Ultra Mobile. ICH7-U does not contain a SATA controller. 186 Intel (R) ICH7 Family Datasheet Functional Description 5.16.2.4 Bus Master IDE Operation To initiate a bus master transfer between memory and an IDE device, the following steps are required: 1. Software prepares a PRD table in system memory. The PRD table must be DWordaligned and must not cross a 64-KB boundary. 2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer Register. The direction of the data transfer is specified by setting the Read/ Write Control bit. The interrupt bit and Error bit in the Status register are cleared. 3. Software issues the appropriate DMA transfer command to the disk device. 4. The bus master function is engaged by software writing a 1 to the Start bit in the Command Register. The first entry in the PRD table is fetched and loaded into two registers which are not visible by software, the Current Base and Current Count registers. These registers hold the current value of the address and byte count loaded from the PRD table. The value in these registers is only valid when there is an active command to an IDE device. 5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge. 6. The controller transfers data to/from memory responding to DMA requests from the IDE device. The IDE device and the host controller may or may not throttle the transfer several times. When the last data transfer for a region has been completed on the IDE interface, the next descriptor is fetched from the table. The descriptor contents are loaded into the Current Base and Current Count registers. 7. At the end of the transfer, the IDE device signals an interrupt. 8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the controller status followed by the drive status to determine if the transfer completed successfully. The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers terminate when the physical region described by the last PRD in the table has been completely transferred. The active bit in the Status Register is reset and the DDRQ signal is masked. The buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the EOL bit set and that region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. Table 5-42 describes how to interpret the Interrupt and Active bits in the Status Register after a DMA transfer has started. Intel (R) ICH7 Family Datasheet 187 Functional Description Table 5-42. Interrupt/Active Bit Interaction Definition Interrupt 0 Active 1 Description DMA transfer is in progress. No interrupt has been generated by the IDE device. The IDE device generated an interrupt. The controller exhausted the Physical Region Descriptors. This is the normal completion case where the size of the physical memory regions was equal to the IDE device transfer size. The IDE device generated an interrupt. The controller has not reached the end of the physical memory regions. This is a valid completion case where the size of the physical memory regions was larger than the IDE device transfer size. This bit combination signals an error condition. If the Error bit in the status register is set, then the controller has some problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size. 1 0 1 1 0 0 5.16.2.5 Error Conditions IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis; either a sector is transferred successfully or it is not. A sector is 512 bytes. If the IDE device does not complete the transfer due to a hardware or software error, the command will eventually be stopped by the driver setting Command Start bit to 0 when the driver times out the disk transaction. Information in the IDE device registers help isolate the cause of the problem. If the controller encounters an error while doing the bus master transfers it will stop the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in the Bus Master IDE Status register. The controller does not generate an interrupt when this happens. The device driver can use device specific information (PCI Configuration Space Status register and IDE Drive Register) to determine what caused the error. Whenever a requested transfer does not complete properly, information in the IDE device registers (Sector Count) can be used to determine how much of the transfer was completed and to construct a new PRD table to complete the requested operation. In most cases the existing PRD table can be used to complete the operation. 5.16.3 Ultra ATA/100/66/33 Protocol The ICH7 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to 33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and Ultra ATA/ 100 can achieve read transfer rates up to 100 MB/s and write transfer rates up to 88.9 MB/s. The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error checking protocol. 188 Intel (R) ICH7 Family Datasheet Functional Description 5.16.3.1 Operation Initial setup programming consists of enabling and performing the proper configuration of the ICH7 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH7, this consists of enabling synchronous DMA mode and setting up appropriate Synchronous DMA timings. When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is followed. Once programmed, the drive and ICH7 control the transfer of data via the Ultra ATA/100/66/33 protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the transfer, the ICH7 asserts DMACK# signal. When DMACK# signal is asserted, the host controller drives CS0# and CS1# inactive, DA0-DA2 low. For write cycles, the ICH7 deasserts STOP, waits for the IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the ICH7 tri-states the DD lines, deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word and STROBE. The data transfer phase continues the burst transfers with the data transmitter (ICH7 - writes, IDE device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH7 pauses a burst transaction to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. It may also pause a transaction if the current PRD byte count has expired, resuming once it has fetched the next PRD. The current burst can be terminated by either the transmitter or receiver. A burst termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH7 can stop a burst by asserting STOP, with the IDE device acknowledging by deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH7 acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a high level. The ICH7 then drives the CRC value onto the DD lines and deassert DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH7 terminates a burst transfer if it needs to service the opposite IDE channel, if a Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon transferring the last data from the final PRD. Intel (R) ICH7 Family Datasheet 189 Functional Description 5.16.4 Ultra ATA/33/66/100 Timing The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing register and the IDE Configuration register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each drive is selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous DMA Timing Register. The Cycle Time represents the minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock periods that the ICH7 waits from deassertion of DMARDY# to the assertion of STOP when it desires to stop a burst read transaction. Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT) must be set for three Base Clocks. The ICH7 thus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means that the ICH7 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the ATA/100 device, and the ICH7 supports reads at the maximum rate of 100 MB/s. 5.16.5 ATA Swap Bay To support PATA swap bay, the ICH7 allows the IDE output signals to be tri-stated and input buffers to be turned off. This should be done prior to the removal of the drive. The output signals can also be driven low. This can be used to remove charge built up on the signals. Configuration bits are included in the IDE I/O Configuration register, offset 54h in the IDE PCI configuration space. In a PATA swap bay operation, an IDE device is removed and a new one inserted while the IDE interface is powered down and the rest of the system is in a fully powered-on state (SO). During a PATA swap bay operation, if the operating system executes cycles to the IDE interface after it has been powered down it will cause the ICH7 to hang the system that is waiting for IORDY to be asserted from the drive. To correct this issue, the following BIOS procedures are required for performing an IDE swap: 1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low mode). 2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the ICH7 from waiting for IORDY assertion when the operating system accesses the IDE device after the IDE drive powers down, and ensures that 0s are always be returned for read cycles that occur during swap operation. Warning: Software should not attempt to control the outputs (either tri-state or driving low), while an IDE transfer is in progress. Unpredictable results could occur, including a system lockup. 5.16.6 SMI Trapping Device 31:Function 1: Offset C0h (see Section 15.1.26) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0- 1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the IDE controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating that a trap occurred. 190 Intel (R) ICH7 Family Datasheet Functional Description 5.17 SATA Host Controller (D31:F2) (Desktop and Mobile Only) The SATA function in the ICH7 has dual modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the ICH7 has separate PCI functions for serial and parallel ATA ("enhanced mode"). To support legacy operating systems, there is only one PCI function for both the serial and parallel ATA ports if functionality from both SATA and PATA devices is desired ("combined mode"). The MAP register, Section 12.1.33, provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used. The ICH7 SATA controller features four (desktop only) / two (mobile only) sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent DMA controller. The ICH7 SATA controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. Table 5-43 lists ICH7 SATA Feature support information. Table 5-44 contains descriptions for the SATA features listed in Table 5-43. Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus's maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS. Table 5-43. SATA Features Support in Intel(R) ICH7 Feature Native Command Queing (NCQ) Auto Activate for DMA Hot Plug Support Asynchronous Signal Recovery 3 Gb/s Transfer Rate ATAPI Asynchronous Notification Host Initiated Power Management Staggered Spin-Up Command Completion Coalescing Port Multiplier External SATA ICH7 & ICH7-M (AHCI/RAID Disabled) N/A N/A N/A N/A Supported (Desktop Only) N/A N/A Supported N/A N/A N/A ICH7 & ICH7-M (AHCI/RAID Enabled) Supported Supported Supported Supported Supported (Desktop Only) Supported Supported (Mobile Only) Supported N/A N/A N/A Intel (R) ICH7 Family Datasheet 191 Functional Description Table 5-44. SATA Feature Description Feature Native Command Queing (NCQ) Auto Activate for DMA Description Allows the device to reorder commands for more efficient data transfers Collapses a DMA Setup then DMA Activate sequence into a DMA Setup only Allows for device detection without power being applied and ability to connect and disconnect devices without prior notification to the system Provides a recovery from a loss of signal or establishing communication after hot plug Capable of data transfers up to 3Gb/s A mechanism for a device to send a notification to the host that the device requires attention Capability for the host controller to request Partial and Slumber interface power states Enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot Reduces interrupt and completion overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands A mechanism for one active host connection to communicate with multiple devices Technology that allows for an outside the box connection of up to 2 meters (when using the cable defined in SATA-IO) Hot Plug Support Asynchronous Signal Recovery 3 Gb/s Transfer Rate ATAPI Asynchronous Notification Host Initiated Power Management Staggered Spin-Up Command Completion Coalescing Port Multiplier External SATA 5.17.1 5.17.1.1 Theory of Operation Standard ATA Emulation The ICH7 contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The ICH7 will assert INTR when the master device completes the EDD command regardless of the command completion status of the slave device. If the master completes EDD first, an INTR is generated and BSY will remain '1' until the slave completes the command. If the slave completes EDD first, BSY will be '0' when the master completes the EDD command and asserts INTR. Software must wait for busy to clear (0) before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry standards. 5.17.1.2 48-Bit LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed via writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). 192 Intel (R) ICH7 Family Datasheet Functional Description If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO. 5.17.2 SATA Swap Bay Support Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller without special support from AHCI and the proper board hardware. However, the ICH7 does provide for basic SATA swap bay support using the PSC register configuration bits and power management flows. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. Note: This SATA swap bay operation requires board hardware (implementation specific), BIOS, and operating system support. 5.17.3 Intel(R) Matrix Storage Technology Configuration (Intel(R) ICH7R, ICH7DH, and ICH7-M DH Only) The Intel(R) Matrix Storage Technology offers several diverse options for RAID (redundant array of independent disks) to meet the needs of the end user. AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in ICH7. * RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing. * Data security is offered thru RAID Level 1, which performs mirroring. * RAID Level 10 (ICH7R/ICH7DH only) provides high levels of storage performance with data protection, combining the fault-tolerance of RAID Level 1 with the performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems that require both performance and fault-tolerance. RAID Level 10 requires 4 hard drives, and provides the capacity of two drives. * RAID Level 5 (ICH7R/ICH7DH only) provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance. By using the ICH7's built-in Intel Matrix Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. Intel Matrix Storage Technology is not available in all ICH7 components. ICH7-M DH supports RAID Level 0, 1. See Section 1.2. Intel Matrix Storage Technology functionality requires the following items: 1. ICH7 component enabled for Intel Matrix Storage Technology (see Section 1.2) 2. Intel(R) Matrix Storage Manager RAID Option ROM must be on the platform 3. Intel(R) Matrix Storage Manager drivers, most recent revision. 4. At least two SATA hard disk drives (minimum depends on RAID configuration). Intel Matrix Storage Technology is not available in the following configurations: 1. The SATA controller in compatible mode. Intel (R) ICH7 Family Datasheet 193 Functional Description 5.17.3.1 Intel(R) Matrix Storage Manager RAID Option ROM The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions: * Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & delete RAID volumes and select recovery options when problems occur. * Provides boot support when using a RAID volume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order. * At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I. 5.17.4 Power Management Operation Power management of the ICH7 SATA controller and ports will cover operations of the host controller and the SATA wire. 5.17.4.1 Power State Mappings The D0 PCI power management state for device is supported by the ICH7 SATA controller. SATA devices may also have multiple power states. From parallel ATA, three device states are supported through ACPI. They are: * D0 - Device is working and instantly available. * D1 - device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds * D3 - from the SATA device's perspective, no different than a D1 state, in that it is entered via the STANDBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller's D0 state. Finally, SATA defines three PHY layer power states, which have no equivalent mappings to parallel ATA. They are: * PHY READY - PHY logic and PLL are both on and active * Partial - PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns * Slumber - PHY logic is powered, but in a reduced state. Exit latency can be up to 10 ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state. 194 Intel (R) ICH7 Family Datasheet Functional Description Figure 5-9. SATA Power States Power Intel(R) ICH SATA Controller = D0 Device = D0 PHY = Ready PHY = Partial PHY = Slumber PHY = Off (port disabled) Device = D1 PHY = Slumber PHY = Off (port disabled) Device = D3 PHY = Slumber PHY = Off (port disabled) Resume Latency 5.17.4.2 5.17.4.2.1 Power State Transitions Partial and Slumber State Entry/Exit The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. The SATA controller defines PHY layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action. 5.17.4.2.2 Device D1, D3 States These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the "STANDBY IMMEDIATE" command. 5.17.4.2.3 Host Controller D3HOT State After the interface and device have been put into a low power state, the SATA host controller may be put into a low power state. This is performed via the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management. 1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort. 2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed. Intel (R) ICH7 Family Datasheet 195 Functional Description 5.17.4.2.4 Non-AHCI Mode PME# Generation When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (via the SATAGP pins). 5.17.4.3 SMI Trapping (APM) Device 31:Function2:Offset C0h (see Section 12.1.40) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0- 1F7h, 3F6h, 170-177h, and 376h). If the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Section 12.1.41) are updated indicating that a trap occurred. 5.17.5 SATA LED The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-collector output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 5.17.6 AHCI Operation (Intel(R) ICH7R, ICH7DH, and Mobile Only) The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers developed thru a joint industry effort (AHCI not available on all ICH7 components; see Section 1.2). AHCI defines transactions between the SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices--each device is treated as a master--and hardware assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. The ICH7 supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface Specification, Revision 1.0 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and Hot-Plug thru the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). Note: For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See Section 7.3.1 of the AHCI Specification for more information. When there are more than two PRD entries for a PIO data transfer that spans multiple DATA FISes, the ICH7 does not support intermediate PRD entries that are less than 144 Words in size when the ICH7 is operating in AHCI mode at 1.5 Gb/s. Note: 196 Intel (R) ICH7 Family Datasheet Functional Description 5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the system as a ground-terminated low-voltage differential signal pair driven by the system Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference Clock is not needed and may be stopped and tri-stated at the clock chip allowing system-level power reductions. The ICH7 uses the SATACLKREQ# output signal to communicate with the system Clock Chip to request either SATA clock running or to tell the system clock chip that it can stop the SATA Reference Clock. ICH7 drives this signal low to request clock running, and tristates the signal to indicate that the SATA Reference Clock may be stopped (the ICH7 does not drive the pin high). When the SATACLKREQ# is tristated by the ICH7, the clock chip may stop the SATA Reference Clock within 100 ns, anytime after 100 ns, or not at all. If the SATA Reference Clock is not already running, it will start within 100 ns after a SATACLKREQ# is driven low by the ICH7. To enable SATA Reference Clock Low Power Request: 1. Configure GPIO35 to native function 2. Set SATA Clock Request Enable (SCRE) bit to `1' (Dev 31:F2:Offset 94h:bit 28). Note: The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is running after system reset. 5.18 High Precision Event Timers This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. Each timer can be configured to cause a separate interrupt. ICH7 provides three timers. The three timers are implemented as a single counter each with its own comparator and value register. This counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system (See Section 6.4). It is not expected that the operating system will move the location of these timers once it is set by the BIOS. 5.18.1 Timer Accuracy 1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). Intel (R) ICH7 Family Datasheet 197 Functional Description The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter is as accurate as the 14.3818 MHz clock. 5.18.2 Interrupt Mapping Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-45. Table 5-45. Legacy Replacement Routing Timer 0 1 2 8259 Mapping IRQ0 IRQ8 Per IRQ Routing Field. APIC Mapping IRQ2 IRQ8 Per IRQ Routing Field Comment In this case, the 8254 timer will not cause any interrupts In this case, the RTC will not cause any interrupts. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23. 5.18.3 Periodic vs. Non-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode (See Section 20.1.5). All three timers support non-periodic mode. Consult Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this mode. Periodic Mode Timer 0 is the only timer that supports periodic mode. Consult Section 2.3.9.2.2 of the IA-PC HPET Specification for a description of this mode. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register 5. Software sets the ENABLE_CNF bit to enable interrupts. 198 Intel (R) ICH7 Family Datasheet Functional Description The Timer 0 Comparator Value register cannot be programmed reliably by a single 64bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. 4) Set the upper 32 bits of the Timer0 Comparator Value register 5.18.4 Enabling the Timers The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 04h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable 4. Set the comparator value 5.18.5 Interrupt Levels Interrupts directed to the internal 8259s are active high. See Section 5.10 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. This may be shared although it's unlikely for the operating system to attempt to do this. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to leveltriggered mode. Edge-triggered interrupts cannot be shared. 5.18.6 Handling Interrupts If each timer has a unique interrupt and the timer has been configured for edgetriggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. Independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. Intel (R) ICH7 Family Datasheet 199 Functional Description 5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. However, a 32-bit processor may not be able to directly read 64-bit timer. A race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that just after reading one half, the other half rolls over and changes the first half. If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0. 5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) The ICH7 contains four USB 2.0 full/low-speed host controllers that support the standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC) includes a root hub with two separate USB ports each, for a total of eight USB ports. * Overcurrent detection on all eight USB ports is supported. The overcurrent inputs are not 5 V tolerant, and can be used as GPIs if not needed. * The ICH7's UHCI host controllers are arbitrated differently than standard PCI devices to improve arbitration latency. * The UHCI controllers use the Analog Front End (AFE) embedded cell that allows support for USB full-speed signaling rates, instead of USB I/O buffers. 5.19.1 Data Structures in Main Memory Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1 details the data structures used to communicate control, status, and data between software and the ICH7. 5.19.2 Data Transfers to/from Main Memory Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1 describes the details on how HCD and the ICH7 communicate via the Schedule data structures. 5.19.3 Data Encoding and Bit Stuffing The ICH7 USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets. Full details on this implementation are given in the Universal Serial Bus Specification, Revision 2.0. 5.19.4 5.19.4.1 Bus Protocol Bit Ordering Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the most significant bit (MSb) last. 200 Intel (R) ICH7 Family Datasheet Functional Description 5.19.4.2 SYNC Field All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the binary string "KJKJKJKK," in its NRZI encoding. It is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. SYNC serves only as a synchronization mechanism and is not shown in the following packet diagrams. The last two bits in the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in the packet must be indexed from this point. 5.19.4.3 Packet Field Formats All packets have distinct start and end of packet delimiters. Full details are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1. 5.19.4.4 Address Fields Function endpoints are addressed using the function address field and the endpoint field. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.2. 5.19.4.5 Frame Number Field The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The frame number field rolls over upon reaching its maximum value of 7FFh, and is sent only for SOF tokens at the start of each frame. 5.19.4.6 Data Field The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits within each byte are shifted out LSB first. 5.19.4.7 Cyclic Redundancy Check (CRC) CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5. 5.19.5 Packet Formats The USB protocol calls out several packet types: token, data, and handshake packets. Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in section 8.4. 5.19.6 USB Interrupts There are two general groups of USB interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ICH7 operation error. All transaction-based sources can be masked by software through the ICH7's Interrupt Enable register. Additionally, individual transfer descriptors can be marked to generate an interrupt on completion. When the ICH7 drives an interrupt for USB, it internally drives the PIRQA# pin for USB function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB function #2, until all sources of the interrupt are cleared. In order to accommodate some operating systems, the Interrupt Pin register must contain a different value for each function of this new multi-function device. Intel (R) ICH7 Family Datasheet 201 Functional Description 5.19.6.1 Transaction-Based Interrupts These interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. This ensures that software can safely process through (Frame List Current Index -1) when it is servicing an interrupt. CRC Error / Time-Out A CRC/Time-Out error occurs when a packet transmitted from the ICH7 to a USB device or a packet transmitted from a USB device to the ICH7 generates a CRC error. The ICH7 is informed of this event by a time-out from the USB device or by the ICH7's CRC checker generating an error on reception of the packet. Additionally, a USB bus timeout occurs when USB devices do not respond to a transaction phase within 19-bit times of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement. When the C_ERR field decrements to 0, the following occurs: * The Active bit in the TD is cleared * The Stalled bit in the TD is set * The CRC/Time-out bit in the TD is set. * At the end of the frame, the USB Error Interrupt bit is set in the HC status register. If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt will be signaled to the system. Interrupt on Completion Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The completion of the transaction associated with that block causes the USB Interrupt bit in the HC Status Register to be set at the end of the frame in which the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is set to 0 (even if it was set to 0 when initially read). If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when the TD completes successfully or because of errors. If the completion is because of errors, the USB Error bit in the HC status register is also set. Short Packet Detect A transfer set is a collection of data which requires more than one USB transaction to completely move the data across the USB. An example might be a large print file which requires numerous TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than the endpoint's Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the frame in which this event occurs. This feature streamlines the processing of input on these transfer types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. 202 Intel (R) ICH7 Family Datasheet Functional Description Serial Bus Babble When a device transmits on the USB for a time greater than its assigned Max Length, it is said to be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits being set to 1. The C_ERR field is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware interrupt is signaled to the system. If an EOF babble was caused by the ICH7 (due to incorrect schedule for instance), the ICH7 forces a bit stuff error followed by an EOP and the start of the next frame. Stalled This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system. Data Buffer Error This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. This would generally be caused by the ICH7 not being able to access required data buffers in memory within necessary latency requirements. Either of these conditions causes the C_ERR field of the TD to be decremented. When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. Bit Stuff Error A bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. This causes the C_ERR field of the TD to be decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. 5.19.6.2 Non-Transaction Based Interrupts If an ICH7 process error or system error occur, the ICH7 halts and immediately issues a hardware interrupt to the system. Resume Received This event indicates that the ICH7 received a RESUME signal from a device on the USB bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware interrupt is signaled to the system allowing the USB to be brought out of the suspend state and returned to normal operation. ICH7 Process Error The HC monitors certain critical fields during operation to ensure that it does not process corrupted data structures. These include checking for a valid PID and verifying that the MaxLength field is less than 1280. If it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register and signals a hardware interrupt to the system. This interrupt cannot be disabled through the Interrupt Enable register. Intel (R) ICH7 Family Datasheet 203 Functional Description Host System Error The ICH7 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur. When this error occurs, the ICH7 clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable register. 5.19.7 USB Power Management The Host controller can be put into a suspended state and its power can be removed. This requires that certain bits of information are retained in the resume power plane of the ICH7 so that a device on a port may wake the system. Such a device may be a faxmodem, which will wake up the machine to receive a fax or take a voice message. The settings of the following bits in I/O space will be maintained when the ICH7 enters the S3, S4, or S5 states. Table 5-46. Bits Maintained in Low Power States Register Command Status Offset 00h 02h Bit 3 2 2 Port Status and Control 10h & 12h 6 8 12 Description Enter Global Suspend Mode (EGSM) Resume Detect Port Enabled/Disabled Resume Detect Low-speed Device Attached Suspend When the ICH7 detects a resume event on any of its ports, it sets the corresponding USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI generated. 5.19.8 USB Legacy Keyboard Operation When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and MS-DOS legacy software will not run, because the keyboard will not be identified. The ICH7 implements a series of trapping operations which will snoop accesses that go to the keyboard controller, and put the expected data from the USB keyboard into the keyboard controller. Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the LPC bus. This legacy operation is performed through SMM space. Figure 5-10 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits. Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes active) to ensure that the processor doesn't complete the cycle before the SMI is observed. This method is used on MPIIX and has been validated. The logic also needs to block the accesses to the 8042. If there is an external 8042, then this is simply accomplished by not activating the 8042 CS. This is simply done by logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go active. An additional term is required for the "passthrough" case. The state table for the diagram is shown in Table 5-47. 204 Intel (R) ICH7 Family Datasheet Functional Description Figure 5-10. USB Legacy Keyboard Flow Diagram To Individual "Caused By" "Bits" S D PCI Config Read, Write Comb. Decoder Clear SMI_60_R R AND SMI Same for 60W, 64R, 64W OR EN_SMI_ON_60R KBC Accesses 60 READ EN_PIRQD# AND To PIRQD# To "Caused By" Bit USB_IRQ Clear USB_IRQ S R D AND EN_SMI_ON_IRQ Table 5-47. USB Legacy Keyboard State Transitions (Sheet 1 of 2) Current State IDLE Action Data Value D1h Next State GateState1 Comment Standard D1 command. Cycle passed through to 8042. SMI# doesn't go active. PSTATE (offset C0, bit 6) goes to 1. Bit 3 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 2 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 1 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. Cycle passed through to 8042, even if trap enabled in Bit 1 in Config Register. No SMI# generated. PSTATE remains 1. If data value is not DFh or DDh then the 8042 may chose to ignore it. 64h / Write IDLE 64h / Write Not D1h IDLE IDLE 64h / Read N/A IDLE IDLE 60h / Write Don't Care IDLE IDLE 60h / Read N/A IDLE GateState1 60h / Write XXh GateState2 Intel (R) ICH7 Family Datasheet 205 Functional Description Table 5-47. USB Legacy Keyboard State Transitions (Sheet 2 of 2) Current State Action Data Value Next State Comment Cycle passed through to 8042, even if trap enabled via Bit 3 in Config Register. No SMI# generated. PSTATE remains 1. Stay in GateState1 because this is part of the double-trigger sequence. Bit 3 in Config space determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. This is an invalid sequence. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of Config Register. PSTATE remains 1. Standard end of sequence. Cycle passed through to 8042. PSTATE goes to 0. Bit 7 in Config Space determines if SMI# should be generated. Improper end of sequence. Bit 3 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Just stay in same state. Generate an SMI# if enabled in Bit 2 of Config Register. PSTATE remains 1. Improper end of sequence. Bit 1 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. Improper end of sequence. Bit 0 in Config Register determines if cycle passed through to 8042 and if SMI# generated. PSTATE goes to 0. If Bit 7 in Config Register is set, then SMI# should be generated. GateState1 64h / Write D1h GateState1 GateState1 64h / Write Not D1h ILDE GateState1 60h / Read N/A IDLE GateState1 64h / Read N/A GateState1 GateState2 64 / Write FFh IDLE GateState2 64h / Write Not FFh IDLE GateState2 64h / Read N/A GateState2 GateState2 60h / Write XXh IDLE GateState2 60h / Read N/A IDLE 206 Intel (R) ICH7 Family Datasheet Functional Description 5.20 USB EHCI Host Controller (D29:F7) The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller which supports up to eight USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to 480 Mb/s using the same pins as the eight USB full-speed/low-speed ports. The ICH7 contains port-routing logic that determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. USB 2.0 based Debug Port is also implemented in the ICH7. A summary of the key architectural differences between the USB UHCI host controllers and the EHCI host controller are shown in Table 5-48. Table 5-48. UHCI vs. EHCI Parameter Accessible by Memory Data Structure Differential Signaling Voltage Ports per Controller USB UHCI I/O space Single linked list 3.3 V 2 Memory Space Separated in to Periodic and Asynchronous lists 400 mV 8 USB EHCI 5.20.1 EHC Initialization The following descriptions step through the expected ICH7 Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.20.1.1 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional ICH7 BIOS information. 5.20.1.2 Driver Initialization See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. Intel (R) ICH7 Family Datasheet 207 Functional Description 5.20.1.3 EHC Resets In addition to the standard ICH7 hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3HOT device power management state to the D0 state. The effects of each of these resets are: Reset Does Reset Memory space registers except Structural Parameters (which is written by BIOS). Does not Reset Comments The HCRESET must only affect registers that the EHCI driver controls. PCI Configuration space and BIOS-programmed parameters can not be reset. The D3-to-D0 transition must not cause wake information (suspend well) to be lost. It also must not clear BIOSprogrammed registers because BIOS may not be invoked following the D3-to-D0 transition. HCRESET bit set. Configuration registers. Software writes the Device Power State from D3HOT (11b) to D0 (00b). Core well registers (except BIOSprogrammed registers). Suspend well registers; BIOSprogrammed core well registers. If the detailed register descriptions give exceptions to these rules, those exceptions override these rules. This summary is provided to help explain the reasons for the reset policies. 5.20.2 Data Structures in Main Memory See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for details. 5.20.3 USB 2.0 Enhanced Host Controller DMA The ICH7 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2. The Periodic DMA engine, and 3. The Asynchronous DMA engine. The ICH7 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port traffic is only presented on one port (Port #0), while the other ports are idle during this time. 5.20.4 Data Encoding and Bit Stuffing See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. 5.20.5 Packet Formats See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. The ICH7 EHCI allows entrance to USB test modes, as defined in the USB 2.0 specification, including Test J, Test Packet, etc. However, note that the ICH7 Test Packet test mode interpacket gap timing may not meet the USB 2.0 specification. 208 Intel (R) ICH7 Family Datasheet Functional Description 5.20.6 USB 2.0 Interrupts and Error Conditions Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only ICH7-specific interrupt and error-reporting behavior is documented in this section. The EHCI Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend the EHC interrupt and error-reporting functionality. * Based on the EHC's Buffer sizes and buffer management policies, the Data Buffer Error can not occur on the ICH7. * Master Abort and Target Abort responses from hub interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered. * The ICH7 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on DMI before the interrupt is asserted. * Since the ICH7 supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds. * The ICH7 delivers interrupts using PIRQH#. * The ICH7 does not modify the CERR count on an Interrupt IN when the "Do Complete-Split" execution criteria are not met. * For complete-split transactions in the Periodic list, the "Missed Microframe" bit does not get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that control structure do not fail the late-start test, then the "Missed Microframe" bit will get set and written back. 5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs: * The Host System Error status bit is set * The DMA engines are halted after completing up to one more transaction on the USB interface * If enabled (by the Host System Error Enable), then an interrupt is generated * If the status is Master Abort, then the Received Master Abort bit in configuration space is set * If the status is Target Abort, then the Received Target Abort bit in configuration space is set * If enabled (by the SERR Enable bit in the function's configuration space), then the Signaled System Error bit in configuration bit is set. Intel (R) ICH7 Family Datasheet 209 Functional Description 5.20.7 5.20.7.1 USB 2.0 Power Management Pause Feature This feature allows platforms (especially mobile systems) to dynamically enter lowpower states during brief periods when the system is idle (i.e., between keystrokes). This is useful for enabling power management features like Intel SpeedStep technology in the ICH7 mobile/ultra mobile only. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC's DMA engines when it knows that the traffic patterns of the attached devices can afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state). 5.20.7.2 Suspend Feature The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification, Section 4.3 describes the details of Port Suspend and Resume. 5.20.7.3 ACPI Device States The USB 2.0 function only supports the D0 and D3 PCI Power Management states. Notes regarding the ICH7 implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must not assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field. 210 Intel (R) ICH7 Family Datasheet Functional Description 5.20.7.4 ACPI System States The EHC behavior as it relates to other power management states in the system is summarized in the following list: -- The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0). -- When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic processor low-power states to be entered. -- The PLL in the EHC is disabled when entering the S3HOT state (48 MHz clock stops), or the S3COLD/S4/S5 states (core power turns off). -- All core well logic is reset in the S3/S4/S5 states. 5.20.7.5 Mobile/Ultra Mobile Only Considerations The ICH7 USB 2.0 implementation does not behave differently in the mobile configurations versus the desktop configurations. However, some features may be especially useful for the mobile configurations. * If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH7 provides mechanisms for changing the structural parameters of the EHC and hiding unused UHCI controllers. See the Intel(R) ICH7 BIOS Specification for information on how BIOS should configure the ICH7. * Mobile/ultra mobile systems may want to minimize the conditions that will wake the system. The ICH7 implements the "Wake Enable" bits in the Port Status and Control registers, as specified in the EHCI spec, for this purpose. * Mobile/Ultra mobile systems may want to cut suspend well power to some or all USB ports when in a low-power state. The ICH7 implements the optional Port Wake Capability Register in the EHC Configuration Space for this platform-specific information to be communicated to software. 5.20.8 Interaction with UHCI Host Controllers The Enhanced Host controller shares the eight USB ports with four UHCI Host controllers in the ICH7. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5; and the UHC at D29:F3 shares ports 6 and 7 with the EHC. There is very little interaction between the Enhanced and the UHCI controllers other than the muxing control which is provided as part of the EHC.Figure 5-11 shows the USB Port Connections at a conceptual level. 5.20.8.1 Port-Routing Logic Integrated into the EHC functionality is port-routing logic, which performs the muxing between the UHCI and EHCI host controllers. The ICH7 conceptually implements this logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of USB 2.0's high-speed signaling protocol or if the EHCI software drivers are not present as indicated by the Configured Flag, then the UHCI controller owns the port. Owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. The host controller that is not the owner of the port internally sees a disconnected port. Intel (R) ICH7 Family Datasheet 211 Functional Description Figure 5-11. Intel(R) ICH7-USB Port Connections UHCI #3 (D29:F3) Port 7 UHCI #2 (D29:F2) UHCI #1 (D29:F1) UCHI #0 (D29:F0) Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Debug Port Enhanced Host Controller Logic Note that the port-routing logic is the only block of logic within the ICH7 that observes the physical (real) connect/disconnect information. The port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and EHCI host controllers. The other USB functional signals are handled as follows: * The Overcurrent inputs (OC[7:0]#) are directly routed to both controllers. An overcurrent event is recorded in both controllers' status registers. The Port-Routing logic is implemented in the Suspend power well so that reenumeration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. The ICH7 also allows the USB Debug Port traffic to be routed in and out of Port #0. When in this mode, the Enhanced Host controller is the owner of Port #0. 212 Intel (R) ICH7 Family Datasheet Functional Description 5.20.8.2 Device Connects The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are four general scenarios that are summarized below. 1. Configure Flag = 0 and a full-speed/low-speed-only Device is connected -- In this case, the UHC is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) does not see the connect occur. The UHCI driver handles the connection and initialization process. 2. Configure Flag = 0 and a high-speed-capable Device is connected -- In this case, the UHC is the owner of the port both before and after the connect occurs. The EHC (except for the port-routing logic) not see the connect occur. The UHCI driver handles the connection and initialization process. Since the UHC does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. Configure Flag = 1 and a full-speed/low-speed-only Device is connected -- In this case, the EHC is the owner of the port before the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has cleared (not set) the Port Enable bit in the EHC's PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the same register, causing the UHC to see a connect event and the EHC to see an "electrical" disconnect event. The UHCI driver and hardware handle the connection and initialization process from that point on. The EHCI driver and hardware handle the perceived disconnect. 4. Configure Flag = 1 and a high-speed-capable Device is connected -- In this case, the EHC is the owner of the port before, and remains the owner after, the connect occurs. The EHCI driver handles the connection and performs the port reset. After the reset process completes, the EHC hardware has set the Port Enable bit in the EHC's PORTSC register. The port is functional at this point. The UHC continues to see an unconnected port. 5.20.8.3 Device Disconnects The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 describes the details of handling Device Connects in Section 4.2. There are three general scenarios that are summarized below. 1. Configure Flag = 0 and the device is disconnected -- In this case, the UHC is the owner of the port both before and after the disconnect occurs. The EHC (except for the port-routing logic) not see a device attached. The UHCI driver handles disconnection process. 2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected -- In this case, the UHC is the owner of the port before the disconnect occurs. The disconnect is reported by the UHC and serviced by the associated UHCI driver. The port-routing logic in the EHC cluster forces the Port Owner bit to 0, indicating that the EHC owns the unconnected port. 3. Configure Flag = 1 and a high-speed-capable Device is disconnected -- In this case, the EHC is the owner of the port before, and remains the owner after, the disconnect occurs. The EHCI hardware and driver handle the disconnection process. The UHC does not see a device attached. Intel (R) ICH7 Family Datasheet 213 Functional Description 5.20.8.4 Effect of Resets on Port-Routing Logic As mentioned above, the Port Routing logic is implemented in the suspend power well so that remuneration and re-mapping of the USB ports is not required following entering and exiting a system sleep state in which the core power is turned off. Reset Event Suspend Well Reset Core Well Reset D3-to-D0 Reset HCRESET Effect on Configure Flag cleared (0) no effect no effect cleared (0) Effect on Port Owner Bits set (1) no effect no effect set (1) 5.20.9 USB 2.0 Legacy Keyboard Operation The ICH7 must support the possibility of a keyboard downstream from either a fullspeed/low-speed or a high-speed port. The description of the legacy keyboard support is unchanged from USB 1.1 (See Section 5.19.8). The EHC provides the basic ability to generate SMIs on an interrupt event, along with more sophisticated control of the generation of SMIs. 5.20.10 USB 2.0 Based Debug Port The ICH7 supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB 2.0 port. High-level restrictions and features are: * Operational before USB 2.0 drivers are loaded. * Functions even when the port is disabled. * Works even though non-configured port is default-routed to the UHCI. Note that the Debug Port can not be used to debug an issue that requires a full-speed/lowspeed device on Port #0 using the UHCI drivers. * Allows normal system USB 2.0 traffic in a system that may only have one USB port. * Debug Port device (DPD) must be high-speed capable and connect directly to Port #0 on ICH7 systems (e.g., the DPD cannot be connected to Port #0 thru a hub). * Debug Port FIFO always makes forward progress (a bad status on USB is simply presented back to software). * The Debug Port FIFO is only given one USB access per microframe. The Debug port facilitates operating system and device driver debug. It allows the software to communicate with an external console using a USB 2.0 connection. Because the interface to this link does not go through the normal USB 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is being debugged. Specific features of this implementation of a debug port are: * Only works with an external USB 2.0 debug device (console) * Implemented for a specific port on the host controller * Operational anytime the port is not suspended AND the host controller is in D0 power state. * Capability is interrupted when port is driving USB RESET 214 Intel (R) ICH7 Family Datasheet Functional Description 5.20.10.1 Theory of Operation There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a "keepalive" packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (i.e., host controller's Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Behavioral Rules 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. If the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. If the standard host controller driver suspends the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register. Table 5-49 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register. Table 5-49. Debug Port Behavior (Sheet 1 of 2) OWNER_CNT 0 1 ENABLED_CT X 0 Port Enable X X Run / Stop X X Suspend X X Debug Port Behavior Debug port is not being used. Normal operation. Debug port is not being used. Normal operation. Debug port in Mode 1. SYNC keepalives sent plus debug traffic Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. Note that no other normal traffic is sent out this port, because the port is not enabled. Invalid. Host controller driver should not put the controller into this state (enabled, not running and not suspended). 1 1 0 0 X 1 1 0 1 X 1 1 1 0 0 Intel (R) ICH7 Family Datasheet 215 Functional Description Table 5-49. Debug Port Behavior (Sheet 2 of 2) OWNER_CNT 1 ENABLED_CT 1 Port Enable 1 Run / Stop 0 Suspend 1 Debug Port Behavior Port is suspended. No debug traffic sent. Debug port in Mode 2. Debug traffic is interspersed with normal traffic. Port is suspended. No debug traffic sent. 1 1 1 1 0 1 1 1 1 1 5.20.10.1.1 OUT Transactions An Out transaction sends data to the debug device. It can occur only when the following are true: * The debug port is enabled * The debug software sets the GO_CNT bit * The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: -- USB_ADDRESS_CNF -- USB_ENDPOINT_CNF -- DATA_BUFFER[63:0] -- TOKEN_PID_CNT[7:0] -- SEND_PID_CNT[15:8] -- DATA_LEN_CNT -- WRITE_READ#_CNT (note: this will always be 1 for OUT transactions) -- GO_CNT (note: this will always be 1 to initiate the transaction) 2. The debug port controller sends a token packet consisting of: -- SYNC -- TOKEN_PID_CNT field -- USB_ADDRESS_CNT field -- USB_ENDPOINT_CNT field -- 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of: -- SYNC -- SEND_PID_CNT field -- The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER -- 16-bit CRC NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 216 Intel (R) ICH7 Family Datasheet Functional Description 4. After sending the data packet, the controller waits for a handshake response from the debug device. * If a handshake is received, the debug port controller: -- a. Places the received PID in the RECEIVED_PID_STS field -- b. Resets the ERROR_GOOD#_STS bit -- c. Sets the DONE_STS bit * If no handshake PID is received, the debug port controller: -- a. Sets the EXCEPTION_STS field to 001b -- b. Sets the ERROR_GOOD#_STS bit -- c. Sets the DONE_STS bit 5.20.10.1.2 IN Transactions An IN transaction receives data from the debug device. It can occur only when the following are true: * The debug port is enabled * The debug software sets the GO_CNT bit * The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: -- USB_ADDRESS_CNF -- USB_ENDPOINT_CNF -- TOKEN_PID_CNT[7:0] -- DATA_LEN_CNT -- WRITE_READ#_CNT (note: this will always be 0 for IN transactions) -- GO_CNT (note: this will always be 1 to initiate the transaction) 2. The debug port controller sends a token packet consisting of: -- SYNC -- TOKEN_PID_CNT field -- USB_ADDRESS_CNT field -- USB_ENDPOINT_CNT field -- 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. If a response is received: -- The received PID is placed into the RECEIVED_PID_STS field -- Any subsequent bytes are placed into the DATA_BUFFER -- The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: -- Resets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit Intel (R) ICH7 Family Datasheet 217 Functional Description 5. If valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: -- Transmits an ACK handshake packet -- Resets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit 6. If no valid packet is received, then the debug port controller: -- Sets the EXCEPTION_STS field to 001b -- Sets the ERROR_GOOD#_STS bit -- Sets the DONE_STS bit. 5.20.10.1.3 Debug Software Enabling the Debug Port There are two mutually exclusive conditions that debug software must address as part of its startup processing: * The EHCI has been initialized by system software * The EHCI has not been initialized by system software Debug software can determine the current `initialized' state of the EHCI by examining the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then system software has initialized the EHCI. Otherwise the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state the EHCI. However, before this can be accomplished, debug software must determine which root USB port is designated as the debug port. Determining the Debug Port Debug software can easily determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. This 4-bit field represents the numeric value assigned to the debug port (i.e., 0001=port 0). Debug Software Startup with Non-Initialized EHCI Debug software can attempt to use the debug port if after setting the OWNER_CNT bit, the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To ensure a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/ Disabled bit in the PORTSC register and the debug software can proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver does not see an enabled port when it is first loaded). 218 Intel (R) ICH7 Family Datasheet Functional Description Debug Software Startup with Initialized EHCI Debug software can attempt to use the debug port if the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. If all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), then the attached device is not a debug peripheral. If the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. 5.21 SMBus Controller (D31:F3) The ICH7 provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The ICH7 is also capable of operating in a mode in which it can communicate with I2C compatible devices. The ICH7 can perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in hardware by the ICH7. The Slave Interface allows an external master to read from or write to the ICH7. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The ICH7's internal host controller cannot access the ICH7's internal Slave Interface. The ICH7 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The ICH7 SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done via the PCI configuration space. Real-time programming of the Host interface is done in system I/O space. The ICH7 SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set. Intel (R) ICH7 Family Datasheet 219 Functional Description 5.21.1 Host Controller The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled. The host controller supports 8 command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write-Block Read Process Call, and Host Notify. The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the "active registers" (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command. Using the SMB host controller to send commands to the ICH7's SMB slave port is supported. The ICH7 supports the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals should not be tied together externally. 5.21.1.1 Command Protocols In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set. Quick Command When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is not appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Send Byte / Receive Byte For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command. The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. 220 Intel (R) ICH7 Family Datasheet Functional Description Write Byte/Word The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Read Byte/Word Reading data is slightly more complicated than writing data. First the ICH7 must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command. When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the ICH7 transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). Block Read/Write The ICH7 contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the ICH7, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. The byte count field is transmitted but ignored by the ICH7 as software will end the transfer after all bytes it cares about have been sent or received. For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command. Intel (R) ICH7 Family Datasheet 221 Functional Description The block write begins with a slave address and a write condition. After the command code the ICH7 issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register. On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The ICH7 will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the message. Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). I2C Read This command allows the ICH7 to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C "Combined Format" that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips. Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read command with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and AAC bit to 0 when running this command. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. 222 Intel (R) ICH7 Family Datasheet Functional Description The format that is used for the command is shown in Table 5-50. Table 5-50. I2C Block Read Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 - - - - Start Slave Address -- 7 bits Write Acknowledge from slave Send DATA1 register Acknowledge from slave Repeated Start Slave Address -- 7 bits Read Acknowledge from slave Data byte 1 from slave -- 8 bits Acknowledge Data byte 2 from slave -- 8 bits Acknowledge Data bytes from slave / Acknowledge Data byte N from slave -- 8 bits NOT Acknowledge Stop Description The ICH7 will continue reading data from the peripheral until the NAK is received. Block Write-Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0. The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows: * M 1 byte * N 1 byte * M + N 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Intel (R) ICH7 Family Datasheet 223 Functional Description Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol. See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. 5.21.2 Bus Arbitration Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The ICH7 continuously monitors the SMBDATA line. When the ICH7 is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the ICH7 will stop transferring data. If the ICH7 sees that it has lost arbitration, the condition is called a collision. The ICH7 will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the ICH7 is a SMBus master, it drives the clock. When the ICH7 is sending address or command as an SMBus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The ICH7 will also provide minimum time between SMBus transactions as a master. Note: The ICH7 supports the same arbitration protocol for both the SMBus and the System Management (SMLINK) interfaces. 5.21.3 5.21.3.1 Bus Timing Clock Stretching Some devices may not be able to handle their clock toggling at the rate that the ICH7 as an SMBus master would like. They have the capability of stretching the low time of the clock. When the ICH7 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The ICH7 monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data. 5.21.3.2 Bus Time Out (Intel(R) ICH7 as SMBus Master) If there is an error in the transaction, such that an SMBus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH7 will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH7 will start after the last bit of data is transferred by the ICH7 and it is waiting for a response. The 25 ms timeout counter will not count under the following conditions: 1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set 2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the system has not locked up). 224 Intel (R) ICH7 Family Datasheet Functional Description 5.21.4 Interrupts / SMI# The ICH7 SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1). Table 5-52 and Table 5-53 specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur. Table 5-51. Enable for SMBALERT# INTREN (Host Control I/O Register, Offset 02h, Bit 0) X X SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) X 1 SMBALERT_DIS (Slave Command I/O Register, Offset 11h, Bit 2) X 0 Event Result SMBALERT# asserted low (always reported in Host Status Register, Bit 5) Wake generated Slave SMI# generated (SMBUS_SMI_STS) Interrupt generated 1 0 0 Table 5-52. Enables for SMBus Slave Write and SMBus Host Events INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit1) Event Event Slave Write to Wake/SMI# Command Slave Write to SMLINK_SLAVE_S MI Command Any combination of Host Status Register [4:1] asserted X X Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS). Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) None Interrupt generated Host SMI# generated X 0 1 1 X X 0 1 Intel (R) ICH7 Family Datasheet 225 Functional Description Table 5-53. Enables for the Host Notify Command HOST_NOTIFY_INTRE N (Slave Control I/O Register, Offset 11h, bit 0) 0 X 1 1 SMB_SMI_EN (Host Config Register, D31:F3:Off40h, Bit 1) X X 0 1 HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, bit 1) 0 1 X X None Wake generated Interrupt generated Slave SMI# generated (SMBUS_SMI_STS) Result 5.21.5 SMBALERT# SMBALERT# is multiplexed with GPIO11. When enable and the signal is asserted, The ICH7 can generate an interrupt, an SMI#, or a wake event from S1-S5. Note: Any event on SMBALERT# (regardless whether it is programmed as a GPI or not), causes the event message to be sent in heartbeat mode. 5.21.6 SMBus CRC Generation and Checking If the AAC bit is set in the Auxiliary Control register, the ICH7 automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result. If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at offset 0Ch will be set. 5.21.7 SMBus Slave Interface The ICH7's SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the ICH7 to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include: * Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify. * Receive Slave Address register: This is the address that the ICH7 decodes. A default value is provided so that the slave interface can be used without the processor having to program this register. * Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller. * Registers that the external microcontroller can read to get the state of the ICH7. * Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. -- Bit 0 of the Slave Status Register for the Host Notify command -- Bit 16 of the SMI Status Register (Section 10.8.3.13) for all others 226 Intel (R) ICH7 Family Datasheet Functional Description Note: The external microcontroller should not attempt to access the ICH7's SMBus slave logic until either: * 800 milliseconds after both: RTEST# is high and RSMRST# is high, OR * the PLTRST# de-asserts The 800 ms case is based on the scenario where the RTC Battery is dead or missing such that the RTC Power Well comes up simultaneously with Suspend Well. In this case, the RTC clock may take a while to stabilize. The ICH7 uses the RTC clock to extend the internal RSMRST# by ~100 ms. Therefore, if the clock is slow to toggle, this time could be extended. 800 ms is assumed to be sufficient guardband for this. If a master leaves the clock and data bits of the SMBus interface at 1 for 50 s or more in the middle of a cycle, the ICH7 slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus a translation in the address is needed to accommodate the least significant bit used for read/write control. For example, if the ICH7 slave address (RCV_SLVA) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read). 5.21.7.1 Format of Slave Write Cycle The external master performs Byte Write commands to the ICH7 SMBus Slave I/F. The "Command" field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register. Note: If the ICH7 is sent a `Hard Reset Without Cycling' command on SMBus while the system is in S4 or S5, the reset command will not be executed until the next wake event. SMBus write commands sent after the Hard Reset Without Cycling command and before the wake event will be NAKed by the ICH7. This also applies to any SMBus wake commands sent after a Hard Reset Without Cycling command, such that the SMBus wake command will not cause the system to wake. Any SMBus read that is accepted by the ICH7 will complete normally. Intel(R) Active Management Technology is not impacted as Intel AMT does not use the Hard Reset Without Cycling command while the system is in S4 or S5. Table 5-54 has the values associated with the registers. Table 5-54. Slave Write Registers Register 0 1-3 4 5 6-7 8 9-FFh Function Command Register. See Table 5-55 below for legal values written to this register. Reserved Data Message Byte 0 Data Message Byte 1 Reserved Reserved Reserved NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The ICH7 overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. ICH7 will not attempt to cover this race condition (i.e., unpredictable results in this case). Intel (R) ICH7 Family Datasheet 227 Functional Description . Table 5-55. Command Types Command Type 0 Reserved WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already awake. The SMI handler should then clear this bit. Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Powerbutton Override occurring. HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. Disable the TCO Messages. This command will disable the Intel(R) ICH7 from sending Heartbeat and Event messages (as described in Section 5.15.2). Once this command has been executed, Heartbeat and Event message reporting can only be re-enabled by assertion and deassertion of the RSMRST# signal. WD RELOAD: Reload watchdog timer. Reserved SMLINK_SLV_SMI. When ICH7 detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 10.9.5). This command should only be used if the system is in an S0 state. If the message is received during S1- S5 states, the ICH7 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. Note: It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the SMI associated with this bit would then be generated. Software must be able to handle this scenario. Reserved Description 1 2 3 4 5 6 7 8 9-FFh 228 Intel (R) ICH7 Family Datasheet Functional Description 5.21.7.2 Format of Read Command The external master performs Byte Read commands to the ICH7 SMBus Slave I/F. The "Command" field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table Table 5-56 shows the Read Cycle Format. Table 5-57 shows the register mapping for the data byte. Table 5-56. Read Cycle Format Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Description Start Slave Address - 7 bits Write ACK Command code - 8 bits ACK Repeated Start Slave Address - 7 bits Read ACK Datay Byte NOT ACK Stop Driven by External Microcontroller External Microcontroller External Microcontroller Intel(R) ICH7 Indicates which register is being accessed See Table 5-57 Must match value in Receive Slave Address register Always 0 Comment External Microcontroller ICH7 External Microcontroller External Microcontroller External Microcontroller ICH7 ICH7 External Microcontroller External Microcontroller Must match value in Receive Slave Address register Always 1 Value depends on register being accessed. See Table 5-57 Table 5-57. Data Values for Slave Read Registers Register 0 Bits 7:0 Reserved System Power State 000 = S0 001 = S1 010 = Reserved 1 2:0 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved 1 2 2 3 3 7:3 3:0 7:4 5:0 7:6 Reserved Frequency Strap Register Reserved Watchdog Timer current value Reserved Description Intel (R) ICH7 Family Datasheet 229 Functional Description Table 5-57. Data Values for Slave Read Registers Register 4 Bits 0 Description 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 = BTI Temperature Event occurred. This bit will be set if the Intel(R) ICH7's THRM# input signal is active. Need to take after polarity control. Boot-status. This bit will be 1 when the processor does not fetch the first instruction. This bit will be set after the TCO timer times out a second time (Both TIMEOUT and SECOND_TO_STS bits set). Reserved The bit will reflect the state of the GPI11/SMBALERT# signal, and will depend on the GP_INV11 bit. It does not matter if the pin is configured as GPI11 or SMBALERT#. * * If the GP_INV11 bit is 1, the value of register 4 bit 7 will equal the level of the GPI11/SMBALERT# pin (high = 1, low = 0). If the GP_INV11 bit is 0, the value of register 4 bit 7 will equal the inverse of the level of the GPI11/SMBALERT# pin (high = 1, low = 0). 4 1 4 4 4 2 3 6:4 4 7 5 0 Unprogrammed flash BIOS bit. This bit will be 1 to indicate that the first BIOS fetch returned FFh, that indicates that the flash BIOS is probably blank. Reserved (Desktop Only) Battery Low Status (Mobile/Ultra Mobile Only). 1 if BATLOW# is `0' Processor Power Failure Status. 1 if the CPUPWR_FLR bit in the GEN_PMCON_2 register is set. INIT# due to receiving Shutdown message. This event is visible from the reception of the shutdown message until a platform reset is done. Events on signal will not create an event message. LT Range: LT reset indication. Events on signal will not create an event message. POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the SLP_S3# pin is deasserted and PWROK pin is not asserted. Thermal Trip: This bit will shadow the state of CPU Thermal Trip status bit (CTS). Events on signal will not create an event message. Reserved Contents of the Message 1 register. Contents of the Message 2 register. Contents of the WDSTATUS register. Reserved 5 5 1 2 5 3 5 4 5 5 5 5 6 7 8 9-FFh 6 7 7:0 7:0 7:0 7:0 5.21.7.2.1 Behavioral Notes According to SMBus protocol, Read and Write messages always begin with a Start bit - Address- Write bit sequence. When the ICH7 detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In 230 Intel (R) ICH7 Family Datasheet Functional Description other words, if a Start -Address-Read occurs (which is invalid for SMBus Read or Write protocol), and the address matches the ICH7's Slave Address, the ICH7 will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start-Address- Read sequence beginning at bit 20. Once again, if the Address matches the ICH7's Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the ICH7's SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are deasserted (high). 5.21.7.3 Format of Host Notify Command The ICH7 tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the ICH7 already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. Table 5-58 shows the Host Notify format. Table 5-58. Host Notify Format Bit 1 8:2 9 10 17:11 Start SMB Host Address -- 7 bits Write ACK (or NACK) Device Address - 7 bits Description Driven By External Master External Master External Master Intel(R) ICH7 External Master External Master ICH7 External Master ICH7 External Master ICH7 External Master Loaded into the Notify Data High Byte Register Loaded into the Notify Data Low Byte Register Always 0001_000 Always 0 ICH7 NACKs if HOST_NOTIFY_STS is 1 Indicates the address of the master; loaded into the Notify Device Address Register 7-bit-only address; this bit is inserted to complete the byte Comment 18 19 27:20 28 36:29 37 38 Unused -- Always 0 ACK Data Byte Low -- 8 bits ACK Data Byte High -- 8 bits ACK Stop Intel (R) ICH7 Family Datasheet 231 Functional Description 5.22 Note: AC '97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) All references to AC '97 in this document refer to the AC '97 Specification, Version 2.3. For further information on the operation of the AC-link protocol, see the AC '97 Specification, Version 2.3. The ICH7 AC '97 controller features include: * Independent PCI functions for audio and modem. * Independent bus master logic for dual Microphone input, dual PCM Audio input (2channel stereo per input), PCM audio output (2-, 4- or 6-channel audio), Modem input, Modem output and S/PDIF output. * 20-bit sample resolution * Multiple sample rates up to 48 kHz * Support for 16 codec-implemented GPIOs * Single modem line * Configure up to three codecs with three ACZ_SDIN pins Table 5-59 shows a detailed list of features supported by the ICH7 AC '97 digital controller . Table 5-59. Features Supported by Intel(R) ICH7 (Sheet 1 of 2) Feature * * Description Isochronous low latency bus master memory interface Scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported) Data buffer size in system memory from 3 to 65535 samples per input Data buffer size in system memory from 0 to 65535 samples per output Independent PCI audio and modem functions with configuration and I/O spaces AC '97 codec registers are shadowed in system memory via driver AC '97 codec register accesses are serialized via semaphore bit in PCI I/O space (new accesses are not allowed while a prior access is still in progress) Power management via PCI Power Management Read/write access to audio codec registers 00h-3Ah and vendor registers 5Ah-7Eh 20-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear channels on slots 3,4,6,7,8,9,10,11) 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4) 16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono mix supports mono hardware AEC reference for speakerphone) 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6) (supports speech recognition or stereo hardware AEC ref for speakerphone) During cold reset ACZ_RST# is held low until after POST and software deassertion of ACZ_RST# (supports passive PC_BEEP to speaker connection during POST) Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah-7Eh 16-bit mono modem line 1 output and input, up to 48 kHz (slot 5) Low latency GPIO[15:0] via hardwired update between slot 12 and PCI I/O register Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT SCI event generation on ACZ_SDIN[2:0] wake-up signal System Interface * * * * * Power Management * * * PCI Audio Function * * * * * PCI Modem function * * * * 232 Intel (R) ICH7 Family Datasheet Functional Description Table 5-59. Features Supported by Intel(R) ICH7 (Sheet 2 of 2) Feature * * Description AC '97 2.3 AC-link interface Variable sample rate output support via AC '97 SLOTREQ protocol (slots 3,4,5,6,7,8,9,10,11) Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6) 3.3 V digital operation meets AC '97 2.3 DC switching levels AC-link I/O driver capability meets AC '97 2.3 triple codec specifications Codec register status reads must be returned with data in the next AC-link frame, per AC '97 Specification, Version 2.3. Triple codec addressing: All AC '97 Audio codec register accesses are addressable to codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary). Modem codec addressing: All AC `97 Modem codec register accesses are addressable to codec ID 00 (primary) or codec ID 01 (secondary). Triple codec receive capability via ACZ_SDIN[2:0] pins (ACZ_SDIN[2:0] frames are internally validated, synchronized, and OR'd depending on the Steer Enable bit status in the SDM register) ACZ_SDIN mapping to DMA engine mapping capability allows for simultaneous input from two different audio codecs. AC-link * * * * * * * Multiple Codec * NOTES: 1. Audio Codec IDs are remappable and not limited to 00,01,10. 2. Modem Codec IDs are remappable and limited to 00, 01. 3. When using multiple codecs, the Modem Codec must be ID 01. Note: Throughout this document, references to D31:F5 indicate that the audio function exists in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI Device 31, Function 6. Throughout this document references to tertiary, third, or triple codecs refer to the third codec in the system connected to the ACZ_SDIN2 pin. The AC '97 Specification, Version 2.3 refers to non-primary codecs as multiple secondary codecs. To avoid confusion and excess verbiage, this datasheet refers to it as the third or tertiary codec. Note: Figure 5-12. Intel(R) ICH7-Based Audio Codec '97 Specification, Version 2.3 Audio In (Record) Audio Out (6 Channel Playback) PC S/PDIF* Output Modem Mic.1 Mic.2 Intel (R) ICH7 Family Datasheet 233 Functional Description 5.22.1 PCI Power Management This Power Management section applies for all AC '97 controller functions. After a power management event is detected, the AC '97 controller wakes the host system. The following sections describe these events and the AC '97 controller power states. Device Power States The AC '97 controller supports D0 and D3 PCI Power Management states. The following are notes regarding the AC '97 controller implementation of the Device States: 1. The AC '97 controller hardware does not inherently consume any more power when it is in the D0 state than it does in D3 state. However, software can halt the DMA engine prior to entering these low power states such that the maximum power consumption is reduced. 2. In the D0 state, all implemented AC '97 controller features are enabled. 3. In D3 state, accesses to the AC '97 controller memory-mapped or I/O range results in master abort. 4. In D3 state, the AC '97 controller interrupt will not assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written from D3HOT to D0, an internal reset is generated. See Section 17.1 for general rules on the effects of this reset. 6. AC97 STS bit is set only when the audio or modem resume events were detected and their respective PME enable bits were set. 7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This causes a wake up event only if the modem controller was in D3 8. Resume events on ACZ_SDIN[2:0] cause resume interrupt status bits to be set only if their respective controllers are not in D3. 9. Edge detect logic prevents the interrupts from being asserted in case the AC97 controller is switched from D3 to D0 after a wake event. 10. Once the interrupt status bits are set, they will cause PIRQB# if their respective enable bits were set. One of the audio or the modem drivers will handle the interrupt. 5.22.2 AC-Link Overview The ICH7 is an AC '97 2.3 controller that communicates with companion codecs via a digital serial link called the AC-link. All digital audio/modem streams and command/ status information is communicated over the AC-link. The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the ICH7 AC-link allows a maximum of three codecs to be connected. Figure 5-13 shows a three codec topology of the AC-link for the ICH7. The AC-link consists of a five signal interface between the ICH7 and codec(s). Note: The ICH7's AC `97 controller shares the signal interface with the Intel High Definition Audio controller. However, only one controller may be enabled at a time. 234 Intel (R) ICH7 Family Datasheet Functional Description Figure 5-13. AC '97 2.3 Controller-Codec Connection AC / MC / AMC ACZ_RST# ACZ_SDOUT ACZ_SYNC ACZ_BIT_CLK Primary Codec Intel(R) ICH7 ACZ_SDIN2 ACZ_SDIN1 ACZ_SDIN0 AC / MC / AMC Secondary Codec AC / MC / AMC Tertiary Codec AC97 ICH codec conn ICH7 core well outputs may be used as strapping options for the ICH7, sampled during system reset. These signals may have weak pullups/pulldowns; however, this will not interfere with link operation. ICH7 inputs integrate weak pulldowns to prevent floating traces when a secondary and/or tertiary codec is not attached. When the Shut Off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pullups/pulldowns. ACZ_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary clocking to support the twelve 20-bit time slots. AC-link serial data is transitioned on each rising edge of ACZ_BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of ACZ_BIT_CLK. If ACZ_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH7 assumes the primary codec is not present or not working. It sets bit 28 of the Global Status Register (I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh to prevent system hangs. Intel (R) ICH7 Family Datasheet 235 Functional Description Synchronization of all AC-link data transactions is signaled by the AC '97 controller via the ACZ_SYNC signal, as shown in Figure 5-14. The primary codec drives the serial bit clock onto the AC-link, which the AC '97 controller then qualifies with the ACZ_SYNC signal to construct data frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing down ACZ_BIT_CLK. ACZ_SYNC remains high for a total duration of 16 ACZ_BIT_CLK at the beginning of each frame. The portion of the frame where ACZ_SYNC is high is defined as the tag phase. The remainder of the frame where ACZ_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge of ACZ_BIT_CLK. Figure 5-14. AC-Link Protocol Tag Phase 20.8uS (48 KHz) SYNC BIT_CLK SDIN End of previous Audio Frame Codec Ready 12.288 MHz 81.4 nS Data Phase slot(1) slot(2) slot(12) "0" "0" "0" 19 0 19 0 19 0 19 0 Time Slot "Valid" Bits ("1" = time slot contains valid PCM Slot 1 Slot 2 Slot 3 Slot 12 The ICH7 has three ACZ_SDIN pins allowing a single, dual, or triple codec configuration. When multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any ACZ_SDIN line. The ICH7 does not distinguish between codecs on its ACZ_SDIN[2:0] pins, however the registers do distinguish between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2] for wake events, etc. If using a Modem Codec it is recommended to connect it to ACZ_SDIN1. The ICH7 does not support optional test modes as outlined in the AC '97 Specification, Version 2.3. 5.22.2.1 Register Access In the ICH7 implementation of the AC-link, up to three codecs can be connected to the SDOUT pin. The following mechanism is used to address the primary, secondary, and tertiary codecs individually. The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 5-60. Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1 and 2 valid bits are set. The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. This allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary codec. If the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. 236 Intel (R) ICH7 Family Datasheet Functional Description Table 5-60. Output Tag Slot 0 Bit 15 14 13 12: 3 2 1:0 Primary Access Example 1 1 1 X 0 00 Secondary Access Example 1 0 0 X 0 01 Frame Valid Slot 1 Valid, Command Address bit (Primary codec only) Slot 2 Valid, Command Data bit (Primary codec only) Slot 3-12 Valid Reserved Codec ID (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary) Description When accessing the codec registers, only one I/O cycle can be pending across the AClink at any time. The ICH7 implements write posting on I/O writes across the AC-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). In order to prevent a second I/O write from occurring before the first one is complete, software must monitor the CAS bit in the Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS bit is cleared, then another codec access (read or write) can go through. The exception to this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data being written. The controller does not issue back to back reads. It must get a response to the first read before issuing a second. In addition, codec reads and writes are only executed once across the link, and are not repeated. 5.22.3 AC-Link Low Power Mode The AC-link signals can be placed in a low-power mode. When the AC '97 Powerdown register (26h), is programmed to the appropriate value, both ACZ_BIT_CLK and ACZ_SDIN will be brought to, and held at a logic low voltage level. Figure 5-15. AC-Link Powerdown Timing SYNC BIT_CLK SDOUT SDIN slot 12 prev. frame TAG Write to 0x20 Data PR4 slot 12 prev. frame TAG Note: BIT_CLK not to scale Intel (R) ICH7 Family Datasheet 237 Functional Description ACZ_BIT_CLK and ACZ_SDIN transition low immediately after a write to the Powerdown Register (26h) with PR4 enabled. When the AC '97 controller driver is at the point where it is ready to program the AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. The AC '97 controller also drives ACZ_SYNC, and ACZ_SDOUT low after programming AC '97 to this low power, halted mode Once the codec has been instructed to halt, ACZ_BIT_CLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal output and input frames can not be communicated in the absence of ACZ_BIT_CLK. Once in a low-power mode, the ICH7 provides three methods for waking up the AC-link; external wake event, cold reset and warm reset. Note: Before entering any low-power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the "Shut Off" bit in the control register. 5.22.3.1 External Wake Event Codecs can signal the controller to wake the AC-link, and wake the system using ACZ_SDIN. Figure 5-16. SDIN Wake Signaling Power Down Frame SYNC BIT_CLK SDOUT SDIN slot 12 prev. frame Sleep State Wake Event New Audio Frame TAG Write to 0x20 Data PR4 TAG Slot 1 Slot 2 slot 12 prev. frame TAG TAG Slot 1 Slot 2 The minimum ACZ_SDIN wake up pulse width is 1 us. The rising edge of ACZ_SDIN0, ACZ_SDIN1 or ACZ_SDIN2 causes the ICH7 to sequence through an AC-link warm reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The primary codec must wait to sample ACZ_SYNC high and low before restarting ACZ_BIT_CLK as diagrammed in Figure 5-16. The codec that signaled the wake event must keep its ACZ_SDIN high until it has sampled ACZ_SYNC having gone high, and then low. The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on the system's current power down state. Unless a cold or register reset (a write to the Reset register in the codec) is performed, wherein the AC '97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, activation of the AC-link via re-assertion of the ACZ_SYNC signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. When AC-link powers up, it indicates readiness via the codec ready bit. 238 Intel (R) ICH7 Family Datasheet Functional Description 5.22.4 AC '97 Cold Reset A cold reset is achieved by asserting ACZ_RST# for 1 s. By driving ACZ_RST# low, ACZ_BIT_CLK, and ACZ_SDOUT will be activated and all codec registers will be initialized to their default power on reset values. ACZ_RST# is an asynchronous AC '97 input to the codec. 5.22.5 AC '97 Warm Reset A warm reset re-activates the AC-link without altering the current codec register values. A warm reset is signaled by driving ACZ_SYNC high for a minimum of 1 s in the absence of ACZ_BIT_CLK. Within normal frames, ACZ_SYNC is a synchronous AC '97 input to the codec. However, in the absence of ACZ_BIT_CLK, ACZ_SYNC is treated as an asynchronous input to the codec used in the generation of a warm reset. The codec must not respond with the activation of ACZ_BIT_CLK until ACZ_SYNC has been sampled low again by the codec. This prevents the false detection of a new frame. Note: On receipt of wake up signaling from the codec, the digital controller issues an interrupt if enabled. Software then has to issue a warm or cold reset to the codec by setting the appropriate bit in the Global Control Register. 5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec Software first performs a read to one of the audio codecs. The read request goes out on ACZ_SDOUT. Since the ICH7 allows one read to be performed at a time on the link, eventually the read data will come back in on one of the ACZ_SDIN[2:0] lines. The codec does this by indicating that status data is valid in its TAG, then echoes the read address in slot 1 followed by the read data in slot 2. The new function of the ICH7 hardware is to notice which ACZ_SDIN line contains the read return data, and to set new bits in the new register indicating which ACZ_SDIN line the register read data returned on. If it returned on ACZ_SDIN[0], bits [1:0] contain the value 00. If it returned on ACZ_SDIN[1], the bits contain the value 01, etc. ICH7 hardware can set these bits every time register read data is returned from a function 5 read. No special command is necessary to cause the bits to be set. The new driver/BIOS software reads the bits from this register when it cares to, and can ignore it otherwise. When software is attempting to establish the codec-to-ACZ_SDIN mapping, it will single feed the read request and not pipeline to ensure it gets the right mapping, we cannot ensure the serialization of the access. Intel (R) ICH7 Family Datasheet 239 Functional Description 5.23 Intel(R) High Definition Audio Overview The ICH7's Intel High Definition Audio controller shares pins with the AC '97 controller. However, only one controller may be enabled at a time. Note: The ICH7-U Ultra Mobile component does not contain an AC `97 controller. The ICH7's controller communicates with the external codec(s) over the Intel High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The ICH7 implements four output DMA engines and 4 input DMA engines. The output DMA engines move digital data from system memory to a D-A converter in a codec. ICH7 implements a single Serial Data Output signal (ACZ_SDOUT) that is connected to all external codecs. The input DMA engines move digital data from the A-D converter in the codec to system memory. The ICH7 implements three Serial Digital Input signals (ACZ_SDI[2:0]) supporting up to three codecs. Audio software renders outbound and processes inbound data to/from buffers in system memory. The location of individual buffers is described by a Buffer Descriptor List (BDL) that is fetched and processed by the controller. The data in the buffers is arranged in a predefined format. The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. The data from the output DMA engines is then combined and serially sent to the external codecs over the Intel High Definition Audio link. The input DMA engines receive data from the codecs over the Intel High Definition Audio link and format the data based on the programmable attributes for that stream. The data is then written to memory in the predefined format for software to process. Each DMA engine moves one stream of data. A single codec can accept or generate multiple streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can accept the same output stream processed by a single DMA engine. Codec commands and responses are also transported to and from the codecs via DMA engines. 5.23.1 5.23.1.1 Intel(R) High Definition Audio Docking (Mobile Only) Dock Sequence Note that this sequence is followed when the system is running and a docking event occurs. 1. Since the ICH7 supports docking, the Docking Supported (DCKSTS. DS) bit defaults to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST to effectively turn off the docking feature. 2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate (DCKSTS.DM) bit are both de-asserted. The AZ_DOCK_EN# signal is de-asserted and AZ_DOCK_RST# is asserted. BCLK, SYNC and SDO signals may or may not be running at the point in time that the docking event occurs. 3. The physical docking event is signaled to ACPI BIOS software via ACPI control methods. This is normally accomplished through a GPIO signal on the ICH7 and is outside the scope of this section. 4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1 and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1 to the DCKCTL.DA bit. 240 Intel (R) ICH7 Family Datasheet Functional Description 5. The HD Audio controller then asserts the AZ_DOCK_EN# signal so that the BCLK signal begins toggling to the dock codec. AZ_DOCK_EN# shall be asserted synchronously to BCLK and timed such that BCLK is low, SYNC is low, and SDO is low. Pull-down resistors on these signals in the docking station discharge the signals low so that the state of the signal on both sides of the switch is the same when the switch is turned on. This reduces the potential for charge coupling glitches on these signals. Note that in the ICH7 the first 8 bits of the Command field are "reserved" and always driven to 0s. This creates a predictable point in time to assert AZ_DOCK_EN#. Note that the HD Audio link reset exit specification that requires that SYNC and SDO be driven low during BCLK startup is not ensured. Note also that the SDO and BCLK signals may not be low while AZ_DOCK_RST# is asserted which also does not comply with the specification. 6. After the controller asserts AZ_DOCK_EN# it waits for a minimum of 2400 BCLKs (100 us) and then de-asserts AZ_DOCK_RST#. This is accomplished in such a way to meet the HD Audio link reset exit specification. AZ_DOCK_RST# de-assertion should be synchronous to BCLK and timed such that there are least 4 full BCLKS from the de-assertion of AZ_DOCK_RST# to the first frame SYNC assertion. 7. The Connect/Turnaround/Address Frame hardware initialization sequence will now occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high on the last BCLK cycle of the Frame Sync of a Connect Frame. The appropriate bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround and Address Frame initialization sequence then occurs on the dock codec's SDI(s). 8. After this hardware initialization sequence is complete (approximately 32 frames), the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1, conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD Audio Bus Driver, which then begins its codec discovery, enumeration, and configuration process. 9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs attached to them. When a corresponding STATESTS bit gets set, an interrupt is generated. In this case the HD Audio Bus Driver is called directly by this interrupt instead of being notified by the plug-N-play IRP. 10. HD Audio Bus Driver software "discovers" the dock codecs by comparing the bits now set in the STATESTS register with the bits that were set prior to the docking event. 5.23.1.2 Exiting D3/CRST# when Docked 1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# deasserted) and DOCK_RST# is asserted. 2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits approximately 7ms, then checks the STATESTS bits to see which codecs are present. 3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is still set and the controller hardware sequences through steps to electrically connect the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#. This completes within the 7 ms mentioned in step 2). 4. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits. 5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit. Intel (R) ICH7 Family Datasheet 241 Functional Description 5.23.1.3 Cold Boot/Resume from S3 When Docked 1. When booting and resuming from S3, PLTRST# switches from asserted to deasserted. This clears the DCKCTL.DA bit and the dock state machines. Because the dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# deasserted) and DOCK_RST# is asserted. 2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. Note that at this point CRST# is still asserted so the dock state machine will remain in its reset state. 3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits approximately 7 ms, then checks the STATESTS bits to see which codecs are present. 4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is still set and the controller hardware sequences through steps to electrically connect the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#. This completes within the 7 ms mentioned in step 3). 5. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits. 5.23.1.4 Undock Sequence There are two possible undocking scenarios. The first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. The second is referred to as the "surprise undock" where the user undocks while the dock codec is running. Both of these situations appear the same to the controller as it is not cognizant of the "surprise removal". But both sequences will be discussed here. 5.23.1.4.1 Normal Undock 1. In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate (DCKSTS.DM) bit are both asserted. The AZ_DOCK_EN# signal is asserted and AZ_DOCK_RST# is de-asserted. 2. The user initiates an undock event through the GUI interface or by pushing a button. This mechanism is outside the scope of this section of the document. Either way ACPI BIOS software will be invoked to manage the undock process. 3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not capable of halting the stream to the docked codec, ACPI BIOS will initiate the hardware undocking sequence as described in the next step while the dock stream is still running. From this standpoint, the result is similar to the "surprise undock" scenario where an audio glitch may occur to the docked codec(s) during the undock process. 4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the DCKCTL.DA bit. 5. The HD Audio controller asserts AZ_DOCK_RST#. AZ_DOCK_RST# assertion shall be synchronous to BCLK. There are no other timing requirements for AZ_DOCK_RST# assertion. Note that the HD Audio link reset specification requirement that the last Frame sync be skipped will not be met. 6. A minimum of 4 BCLKs after AZ_DOCK_RST# the controller will de-assert AZ_DOCK_EN# to isolate the dock codec signals from the ICH7 HD Audio link signals. AZ_DOCK_EN# is de-asserted synchronously to BCLK and timed such that BCLK, SYNC, and SDO are low. 7. After this hardware undocking sequence is complete (a maximum of TBD from DCKCTL.DA being written from "1" to "0"), the controller hardware clears the DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS software polls DCKSTS.DM and when it sees DM set, conveys to the end user that physical undocking can proceed. The controller is now ready for a subsequent docking event. 242 Intel (R) ICH7 Family Datasheet Functional Description 5.23.1.4.2 Surprise Undock 1. In the surprise undock case the user undocks before software has had the opportunity to gracefully halt the stream to the dock codec and initiate the hardware undock sequence. 2. A signal on the docking connector is connected to the switch that isolates the dock codec signals from the ICH7 HD Audio link signals (DOCK_DET# in the conceptual diagram). When the undock event begins to occur the switch will be put into isolate mode. 3. The undock event is communicated to the ACPI BIOS via ACPI control methods that are outside the scope of this section of the document. 4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up the dock codec stream. 5. The HD Audio controller hardware is oblivious to the fact that a surprise undock occurred. The flow from this point on is identical to the normal undocking sequence described in section 0 starting at step 3). It finishes with the hardware clearing the DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is now ready for a subsequent docking event. 5.23.1.5 Interaction Between Dock/Undock and Power Management States When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for initiating the docking sequence if the dock is already attached when PLTRST# is deasserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver deasserting CRTS# and detecting and enumerating the codecs attached to the AZ_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware signal indicating that a dock is attached. Therefore, a method outside the scope of this document must be used to cause the POST BIOS to initiate the docking sequence. When exiting from D3, CRST# will be asserted. When CRST# bit is "0" (asserted), the DCKCTL.DA bit is not cleared. The dock state machine will be reset such that AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to "1" and will begin sequencing through the dock process. Note that this does not require any software intervention. 5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# AZ_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As long as AZ_RST# is asserted, the DOCK_RST# signal will also be asserted. When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to their default state (0's), and the dock state machine will be reset such that AZ_DOCK_EN# will be de-asserted, and AZ_DOCK_RST# will be asserted. After any PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and then writing a "1" to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting CRST#. When CRST# bit is "0" (asserted), the DCKCTL.DA bit is not cleared. The dock state machine will be reset such that AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to "1" and will begin sequencing through the dock process. Note that this does not require any software intervention. Intel (R) ICH7 Family Datasheet 243 Functional Description 5.24 Intel(R) Active Management Technology (Intel(R) AMT) (Desktop and Mobile Only) Intel Active Management Technology is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. Reducing the Total Cost of Ownership (TCO) through improved asset tracking, remote manageability, and fewer desk-side visits were identified as key IT priorities. PT extends the capabilities of existing management solutions by making the asset information, remote diagnostics, and recovery capabilities always available, or Out of Band (OOB), even when the system is in a low-power "off" state or the OS is hung. 5.24.1 Intel(R) AMT Features * E-Asset Tag * OOB HW and SW Inventory Logs * OOB Alerts * IDE Redirect * Serial over LAN for Remote Control * Remote Diagnostics Execution * OS Lock-Up Alert * OS Repair * Remote BIOS Recovery and Update 5.24.2 Intel(R) AMT Requirements Intel AMT is a platform-level solution that uses multiple system components including: * Intel AMT-Ready ICH7 component for the SMBus, PCI Express, SPI flash bus, and system sensors * Intel(R) PRO 82573E Gigabit Ethernet Controller with Intel(R) Active Management Technology for remote access * An embedded microcontroller to run OOB firmware/software * SPI flash memory (4 Mb for Intel AMT) to store asset information, management software code, and logs * BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can optionally share same flash memory device) * Familiar ISV software packages to take advantage of Intel AMT's platform management capabilities 244 Intel (R) ICH7 Family Datasheet Functional Description 5.25 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost alternative for system flash versus the Firmware Hub on the LPC bus. The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (CS#). Communication on the SPI bus is done with a Master - Slave protocol. The typical bus topology consists of a single SPI Master (ICH7) with a single SPI Slave (flash device). The Slave is connected to the ICH7 and is implemented as a tri-state bus. Arbitration has been added that enables an optional shared flash configuration where the ICH7 shares access to the SPI flash device with the PCI Express based Intel PRO 82573E Gigabit Ethernet Controller. This configuration allows a single larger density flash device to replace two smaller density flash devices on the motherboard to potentially reduce bill of material (BOM) costs. Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected by the ICH7, LPC based BIOS flash is disabled. 5.25.1 SPI Arbitration between Intel(R) ICH7 and Intel PRO 82573E The Shared Flash implementation consists of two SPI masters (ICH7 and Intel PRO 82573E) that arbitrate for access to a single shared SPI Device. This allows for consolidation of Non-Volatile memory required by the Intel PRO 82573E GbE device with the system BIOS offering the potential for BOM and board real estate savings. The arbitration between Intel PRO 82573E and ICH7 occurs with the addition of an ARB signal. The SPI flash device is connected to both the Intel PRO 82573E and ICH7 chips and implemented as a shared tri-state bus; the ARB signal is connected directly from Intel PRO 82573E to ICH7 and not to the SPI device. The Shared Flash configuration allows each master to complete write and erase commands to the SPI Flash, before allowing the other master to take ownership of the bus 5.25.2 Flash Device Configurations The ICH7, Intel PRO 82573E GbE LAN with Intel(R) Active Management Technology, and SPI flash may be used in multiple configurations. Table 5-61 focuses on these various configurations involving the ICH7. Table 5-61. SPI Implementation Options Configuration Intel PRO 82573E with Intel AMT Present No No Yes Yes Yes Intel PRO 82573E Firmware with Intel AMT No No SPI SPI SPI System BIOS Location FWH SPI FWH SPI SPI System BIOS and Intel AMT Shared Flash No No No No Yes FWH Present Yes No Yes No No Number of SPI Device(s) 0 1 1 2 1 1 2 3 4 5 Note: The ICH7 SPI interface supports a single Chip Select pin for a single SPI device. Intel (R) ICH7 Family Datasheet 245 Functional Description 5.25.3 SPI Device Compatibility Requirements A variety of SPI flash devices exist in the market. In order for a SPI device to be compatible with the ICH7 it must meet the minimum requirements detailed in the following sections. 5.25.3.1 Intel(R) ICH7 SPI Based BIOS Only Configuration Requirements (Non-Shared Flash Configuration) A SPI flash device must meet the following minimum requirements to be compatible with the ICH7 in a non-shared flash configuration: * Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB, 512 bytes, or 256 bytes. * Required command set and associated opcodes (Refer to Section 5.25.4.1). * Device identification command (Refer to Section 5.25.4.2). * Device must support multiple writes to a page without requiring a preceding erase cycle (Refer to Section 5.25.4.3) * Serial flash device must ignore the upper address bits such that an address of FFFFFFh simply aliases to the top of the flash memory. * SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). * If the device receives a command that is not supported, the device must complete the cycle gracefully without any impact on the flash content. * An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits inside the designated area (page, sector, block, chip, or etc.). * Minimum density of 4 Mb (Platform dependent based on size of BIOS). Note: The ICH7 only supports Mode 0 on SPI flash devices 5.25.3.2 Intel(R) ICH7 with Intel(R) PRO 82573E with Intel AMT Firmware Configuration Requirements (Shared Flash Configuration) A SPI flash device must meet the following minimum requirements to be compatible with the ICH7 and the Intel PRO 82573E GbE with Intel AMT device in a shared flash configuration: The following are requirements that are in common with the BIOS only configuration listed in Section 5.25.3.1: * Required command set and associated opcodes (Refer to Section 5.25.4.1) * Device identification command (Refer to Section 5.25.4.2) * Device must support multiple writes to a page without requiring a preceding erase cycle (Refer to Section 5.25.4.3) * Serial flash device must ignore the upper address bits such that an address of FFFFFFh simply aliases to the top of the flash memory. * SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). * If the device receives a command that is not supported, the device must complete the cycle gracefully without any impact on the flash content. * An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits inside the designated area (page, sector, block, chip, or etc.). 246 Intel (R) ICH7 Family Datasheet Functional Description The following is a list of additional requirements specific to the ICH7 with Intel PRO 82573E configuration: * Erase size capability of at least one of the following: 4 KBytes (preferred) or 256 bytes. * Byte write must be supported. * A serial flash device that requires the Write Enable command must automatically clear the Write Enable Latch at the end of Data Program instructions * Status Register bit 0 must be set to 1 when a write or erase is in progress and cleared to 0 when a write or erase is not in progress. * Minimum density of 4 Mb for non-BIOS data storage * Minimum density of 8 Mb for shared flash configurations (4 Mb for non-BIOS data + 4 Mb for BIOS - platform dependant based on size of BIOS) Note: The ICH7 only supports Mode 0 on SPI flash devices. 5.25.4 5.25.4.1 Intel(R) ICH7 Compatible Command Set Required Command Set for Inter Operability Table 5-62 contains a list of commands and the associated opcodes that a SPI based serial flash device must support in order to be interoperable with the serial flash interface. Table 5-62. Required Commands and Opcodes Commands Program Data Read Data Read Status OPCODE 02h 03h 05h 5.25.4.2 Recommended Standard Commands The following table contains a list of standard commands that a SPI device should support to be compatible with the ICH7. This list only contains standard commands and is not meant to be an all inclusive list of commands that SPI devices can support. Table 5-63. Intel(R) ICH7 Standard SPI Commands Commands Write Status Write Disable Write Enable Fast Read JEDEC ID Identify Device OPCODE 01h 04h 06h 0Bh 9Fh ABh If command is supported by a device, 06h must be supported. Intel(R) ICH7 does not support this command. Either JEDEC ID (9Fh) or an Identify Device with ABh is required, not both. Either JEDEC ID (9Fh) or an Identify Device with ABh is required, not both Notes If command is supported by a device, 01h must be supported. Intel (R) ICH7 Family Datasheet 247 Functional Description 5.25.4.3 Multiple Page Write Usage Model The system BIOS and Intel(R) Active Management Technology firmware usage models require that the serial flash device support multiple writes (minimum of 512 writes) to a page (256 bytes) without requiring a preceding erase command. BIOS commonly uses capabilities such as counters that are typically implemented by using byte writes to `increment' the bits within a page that have been designated as the counter. The Intel AMT firmware usage model requires the capability for multiple data updates within any given page. These data updates occur via byte writes without executing a preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple page write usage models apply to sequential and non-sequential data writes. Note: This usage model requirement is based on any given bit only being written once from a `1' to a `0' without requiring the preceding erase. An erase would be required to change bits back to the `1' state. 5.25.5 Flash Protection There are three types of Flash Protection mechanisms: 1. BIOS Range Write Protection 2. SMI#-Based Global Write Protection 3. Shared Flash Address Range Protection The three mechanisms are conceptually OR'd together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. Table 5-64 provides a summary of the Three Mechanisms. Table 5-64. Flash Protection Mechanism Summary Mechanism BIOS Range Write Protection Write Protect BIOS BAR Accesses Blocked Range Specific ? Yes Reset-Override or SMI#Override? Reset Override Equivalent Function on FWH Writes FWH Sector Protection Same as Write Protect in previous ICH components for FWH Not Applicable- Specific to Flash Sharing Writes Reads and Writes No Yes SMI# Override Reset Override A blocked command will appear to software to finish, except that the Blocked Access status bit is set in this case. 5.25.5.1 BIOS Range Write Protection The ICH7 provides a method for blocking writes to specific ranges in the SPI flash when the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) and the address of the requested command against the base and limit fields of a Write Protected BIOS range. Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism remains in place until the next system reset. 248 Intel (R) ICH7 Family Datasheet Functional Description 5.25.5.2 SMI# Based Global Write Protection The ICH7 provides a method for blocking writes to the SPI flash when the Write Protect bit is cleared (i.e., protected). This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) of the requested command. The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as they do for the FWH BIOS. 5.25.5.3 Shared Flash Address Range Protection The System Flash (BIOS) occupies the top part of the SPI Flash Memory Device when sharing this space with the LAN and Manageability functions. To prevent the system from inappropriately accessing or modifying information in the LAN and Manageability areas, the ICH7 checks outgoing addresses with the BIOS Base Address register and blocks any cycles with addresses below that value. This includes Direct Memory Reads to the SPI flash. Note: Once BIOS has locked down the BIOS BAR, this mechanism remains in place until the next system reset. 5.26 Intel(R) Quick Resume Technology (Digital Home Only) ICH7 implements the following Intel(R) Quick Resume Technology (QRT) features: * Visual Off * Consumer Electronics (CE) like On/Off 5.26.1 Visual Off Intel Quick Resume Technology provides a new functional state called Visual Off. In Visual Off the PC appears to be Off but is actually active and able to run program tasks. The Visual Off state is transparent to the user. It is entered by simply pressing the power button when the system is On. This turns off the display, sound, front panel lights and HID devices (e.g. keyboard and mouse) but the PC stays active. Perceptually to the user, the system appears Off in this state. Pressing the power button again will turn back On the perceptual components that were "muted" in Visual Off. From the Visual Off state, the system's power management can place the PC in a low power suspend state (S3) using existing mechanisms. Again, this is transparent to the end user. 5.26.2 CE-like On/Off Intel Quick Resume Technology redefines the PC's power button behavior to switch between user perceived On and Off states like a consumer electronics (CE) device. For example when a television is turned off there is no shutdown procedure. The viewer simply turns it Off. Likewise when a modern television is turned On it returns to the same channel, volume level, color balance, etc. as when it was turned Off. Intel Quick Resume Technology gives the PC this similar functionality. A simple press of the power button turns it On or Off. There is no user visible lengthy boot up or shutdown process as the Visual Off state is used. Therefore, there is no need to exit running applications. Intel (R) ICH7 Family Datasheet 249 Functional Description Just as televisions may have multiple power buttons (e.g., on the TV and on a remote control) so may the PC (e.g., a power button on the system unit and another on the keyboard). However, all power buttons behave the same -- On/Off. The PC will not turn On (wake up) when any key is pressed or the mouse moved just as pressing the volume button or TV channel button does not cause the TV to turn On. Only a power button press turns it On and Off. 5.26.3 Intel(R) Quick Resume Technology Signals (ICH7DH Only) To provide the end user notification of the system power state, it is recommended that the front panel LED be used to indicate Visual Off in the same way that the front panel LED is used to indicate the S3 system state. For example, if in the S3 state the front panel LED is solid amber, also set the front panel LED to be solid amber upon entrance into Visual Off. To provide for platform implementation flexibility, the ICH7DH implements two Intel Quick Resume Technology (QRT) signals that are multiplexed with GPIOs: EL_STATE0/ GPIO27 and EL_STATE1/GPIO28. The EL_STATE[1:0] pins may be used to control LED(s) to provide end-user notification of the current system state or may be used as GPIO pins (independently or combined). See Chapter 14 for further details on controlling these signals. The ICH7DH has an additional Intel QRT pin: EL_RSVD/GPIO26. When Intel QRT is enabled, this signal is used exclusively as EL_RSVD and should be left as no connect. Note: EL_RSVD should be left as a no connect on motherboards that will implement Intel QRT. 5.26.4 Power Button Sequence (ICH7DH Only) When Intel Quick Resume Technology (QRT) is enabled and the user presses the PWRBTN# to put the system into the Visual Off state, the following sequence is assumed: 1. User presses the Power Button, which causes the PWRBTN# signal to go low. 2. Intel QRT logic sets the EL_PB_STS bit. If the PWRBTN_INT_EN bit is set, the ICH7 does NOT set the PWRBTN_STS bit at this point. 3. Intel QRT logic causes an SMI or SCI (depending on the SMI_OPTION_CNT bit.) 4. If the Intel QRT logic was set to cause an SMI, the SMI handler executes and then sets the SCI_NOW_CNT bit. 5. The Intel QRT SCI handler executes. 6. The Intel QRT SCI handler needs to cause the PWRBTN_STS bit to be set, it can do so by setting the PWRBTN_EVENT bit. Note: When PWRBTN_STS is set, the ICH7 causes an SCI and the normal OS handler for PWRBTN_STS is called. 250 Intel (R) ICH7 Family Datasheet Functional Description 5.27 Feature Capability Mechanism A new set of registers have been added into ICH7 LPC Interface (Device 31, Function 0, offset E0h - EBh) that allows the system software or BIOS to easily determine the features supported by ICH7. These registers can be accessed through LPC PCI configuration space; thus allowing for convenient single point access mechanism for chipset feature detection. This set of registers consists of: Capability ID (FDCAP) Capability Length (FDLEN) Capability Version and Vendor-Specific Capability ID (FDVER) Feature Vector (FVECT) Intel (R) ICH7 Family Datasheet 251 Functional Description 252 Intel (R) ICH7 Family Datasheet Register and Memory Mapping 6 Register and Memory Mapping The ICH7 contains registers that are located in the processor's I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the ICH7 I/O and memory maps at the register-set level. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations and definitions are used in the register/instruction description chapters. RO Read Only. In some cases, If a register is read only, writes to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. Write Only. In some cases, If a register is write only, reads to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. Read/Write. A register with this attribute can be read and written. Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. Read/Write-Once. A register bit with this attribute can be written only once after power up. After the first write, the bit becomes read only. Read/Write, Lock-Once. A register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. After the locked value has been written, the bit becomes read only. When ICH7 is reset, it sets its registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ICH7 registers accordingly. Register bits that are highlighted in bold text indicate that the bit is implemented in the ICH7. Register bits that are not implemented or are hardwired will remain in plain text. WO R/W R/WC R/WO R/WLO Default Bold All bit(s) or bit-fields must be correctly dealt with by software. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit locations are preserved. Any ICH7 configuration register or I/O or memory mapped location not explicitly indicated in this document must be considered reserved. Intel (R) ICH7 Family Datasheet 253 Register and Memory Mapping 6.1 PCI Devices and Functions The ICH7 incorporates a variety of PCI functions as shown in Table 6-1. These functions are divided into six logical devices (B0:D30, B0:D31, B0:D29, B0:D28, B0:D27 and B1:D8). D30 contains the DMI interface-to-PCI bridge and the AC '97 Audio and Modem controller. D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and the SMBus controller. D29 contains the four USB UHCI controllers and one USB EHCI controller. D27 contains the Intel High Definition Audio controller. B1:D8 is the integrated LAN controller. Note: From a software perspective, the integrated LAN controller resides on the ICH7's external PCI bus. This is typically Bus 1, but may be assigned a different number depending on system configuration. If for some reason, the particular system platform does not want to support any one of the Device Functions, with the exception of D30:F0, they can individually be disabled. The integrated LAN controller will be disabled if no Platform LAN Connect component is detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. b Table 6-1. PCI Devices and Functions Bus:Device:Function1 Bus 0:Device 30:Function 0 Bus 0:Device 30:Function 2 Bus 0:Device 30:Function 3 Bus 0:Device 31:Function 0 Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 0:Device 29:Function 0 Bus 0:Device 29:Function 1 Bus 0:Device 29:Function 2 Bus 0:Device 29:Function 3 Bus 0:Device 29:Function 7 Bus 0:Device 28:Function 0 Bus 0:Device 28:Function 1 Bus 0:Device 28:Function 2 Bus 0:Device 28:Function 3 Bus 0:Device 28:Function 4 Bus 0:Device 28:Function 5 Bus 0:Device 27:Function 0 Bus n:Device 8:Function 0 PCI-to-PCI Bridge AC '97 Audio Controller (Desktop and Mobile Only) AC '97 Modem Controller (Desktop and Mobile Only) LPC Controller1 IDE Controller SATA Controller (Desktop and Mobile Only) SMBus Controller USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 USB UHCI Controller #4 USB 2.0 EHCI Controller PCI Express* Port 1 (Desktop and Mobile Only) PCI Express Port 2 (Desktop and Mobile Only) PCI Express Port 3 (Desktop and Mobile Only) PCI Express Port 4 (Desktop and Mobile Only) PCI Express Port 5 (Intel(R) ICH7R, and ICH7DH, and ICH7-M Only) PCI Express Port 6 (Intel(R) ICH7R, and ICH7DH, and ICH7-M Only) Intel(R) High Definition Audio Controller LAN Controller (Desktop and Mobile Only) Function Description NOTES: 1. The LPC controller contains registers that control LPC, Power Management, System Management, GPIO, processor Interface, RTC, Interrupts, Timers, DMA. 254 Intel (R) ICH7 Family Datasheet Register and Memory Mapping 6.2 PCI Configuration Map Each PCI function on the ICH7 has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.3. Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the configuration space contains reserved locations. Software should not write to reserved PCI configuration locations in the device-specific region (above address offset 3Fh). 6.3 I/O Map The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but in some cases can be disabled. Variable ranges can be moved and can also be disabled. 6.3.1 Fixed I/O Address Ranges Table 6-2 shows the Fixed I/O decode ranges from the processor perspective. Note that for each I/O range, there may be separate behavior for reads and writes. DMI (Direct Media Interface) cycles that go to target ranges that are marked as "Reserved" will not be decoded by the ICH7, and will be passed to PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the ICH7 in medium speed. Address ranges that are not listed or marked "Reserved" are not decoded by the ICH7 (unless assigned to one of the variable ranges). Intel (R) ICH7 Family Datasheet 255 Register and Memory Mapping Table 6-2. Fixed I/O Ranges Decoded by Intel(R) ICH7 (Sheet 1 of 2) I/O Address 00h-08h 09h-0Eh 0Fh 10h-18h 19h-1Eh 1Fh 20h-21h 24h-25h 28h-29h 2Ch-2Dh 2E-2F 30h-31h 34h-35h 38h-39h 3Ch-3Dh 40h-42h 43h 4E-4F 50h-52h 53h 60h 61h 62h 64h 66h 70h 71h 72h 73h 74h 75h 76h 77h 80h 81h-83h Read Target DMA Controller RESERVED DMA Controller DMA Controller RESERVED DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller LPC SIO Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Timer/Counter RESERVED LPC SIO Timer/Counter RESERVED Microcontroller NMI Controller Microcontroller Microcontroller Microcontroller RESERVED RTC Controller RTC Controller RTC Controller RTC Controller RTC Controller RTC Controller RTC Controller DMA Controller, or LPC, or PCI DMA Controller Write Target DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller LPC SIO Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Timer/Counter Timer/Counter LPC SIO Timer/Counter Timer/Counter Microcontroller NMI Controller Microcontroller Microcontroller Microcontroller NMI and RTC Controller RTC Controller NMI and RTC Controller RTC Controller NMI and RTC Controller RTC Controller NMI and RTC Controller RTC Controller DMA Controller and LPC or PCI DMA Controller Internal Unit DMA DMA DMA DMA DMA DMA Interrupt Interrupt Interrupt Interrupt Forwarded to LPC Interrupt Interrupt Interrupt Interrupt PIT (8254) PIT Forwarded to LPC PIT PIT Forwarded to LPC Processor I/F Forwarded to LPC Forwarded to LPC Forwarded to LPC RTC RTC RTC RTC RTC RTC RTC RTC DMA DMA 256 Intel (R) ICH7 Family Datasheet Register and Memory Mapping Table 6-2. Fixed I/O Ranges Decoded by Intel(R) ICH7 (Sheet 2 of 2) I/O Address 84h-86h 87h 88h 89h-8Bh 8Ch-8Eh 08Fh 90h-91h 92h 93h-9Fh A0h-A1h A4h-A5h A8h-A9h ACh-ADh B0h-B1h B2h-B3h B4h-B5h B8h-B9h BCh-BDh C0h-D1h D2h-DDh DEh-DFh F0h 170h-177h 1F0h-1F7h 376h 3F6h 4D0h-4D1h CF9h Read Target DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller Reset Generator DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Power Management Interrupt Controller Interrupt Controller Interrupt Controller DMA Controller RESERVED DMA Controller FERR#/IGNNE# / Interrupt Controller IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI 1 IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI 1 Interrupt Controller Reset Generator Write Target DMA Controller and LPC or PCI DMA Controller DMA Controller and LPC or PCI DMA Controller DMA Controller and LPC or PCI DMA Controller DMA Controller Reset Generator DMA Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Power Management Interrupt Controller Interrupt Controller Interrupt Controller DMA Controller DMA Controller DMA Controller FERR#/IGNNE# / Interrupt Controller IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI IDE Controller, SATA Controller, or PCI Interrupt Controller Reset Generator Internal Unit DMA DMA DMA DMA DMA DMA DMA Processor I/F DMA Interrupt Interrupt Interrupt Interrupt Interrupt Power Management Interrupt Interrupt Interrupt DMA DMA DMA Processor I/F Forwarded to IDE or SATA Forwarded to IDE or SATA Forwarded to IDE or SATA Forwarded IDE or SATA Interrupt Processor I/F NOTES: 1. Only if IDE I/O space is enabled (D31:F1:40 bit 15) and the IDE controller is in legacy mode. Otherwise, the target is PCI. Intel (R) ICH7 Family Datasheet 257 Register and Memory Mapping 6.3.2 Variable I/O Decode Ranges Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable results if the configuration software allows conflicts to occur. The ICH7 does not perform any checks for conflicts. Variable I/O Decode Ranges Range Name ACPI IDE Bus Master Native IDE Command Native IDE Control USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 USB UHCI Controller #4 SMBus AC '97 Audio Mixer AC '97 Audio Bus Master AC '97 Modem Mixer AC '97 Modem Bus Master TCO GPIO Parallel Port Serial Port 1 Serial Port 2 Floppy Disk Controller Mappable Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space 96 Bytes above ACPI Base Anywhere in 64 KB I/O Space 3 Ranges in 64 KB I/O Space 8 Ranges in 64 KB I/O Space 8 Ranges in 64 KB I/O Space 2 Ranges in 64 KB I/O Space Size (Bytes) 64 16 8 4 32 32 32 32 32 256 64 256 128 32 64 8 8 8 8 Target Power Management IDE Unit IDE Unit IDE Unit USB Unit 1 USB Unit 2 USB Unit 3 USB Unit 4 SMB Unit AC '97 Unit AC '97 Unit AC '97 Unit AC '97 Unit TCO Unit GPIO Unit LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral Table 6-3. 258 Intel (R) ICH7 Family Datasheet Register and Memory Mapping Table 6-3. Variable I/O Decode Ranges Range Name LAN LPC Generic 1 LPC Generic 21 LPC Generic 3 LPC Generic 4 I/O Trapping Ranges Mappable Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Anywhere in 64 KB I/O Space Size (Bytes) 64 4 to 256 4 to 256 4 to 256 4 to 256 1 to 256 Target LAN Unit LPC Peripheral LPC Peripheral LPC Peripheral LPC Peripheral Trap on Backbone NOTE: 1. Decode range size determined by D31:F0:ADh:bits 5:4 6.4 Memory Map Table 6-4 shows (from the processor perspective) the memory ranges that the ICH7 decodes. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be driven out on PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH7 may then claim the cycle for the internal LAN controller. PCI cycles generated by external PCI masters will be positively decoded unless they fall in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller's range, it will be forwarded up to DMI. Software must not attempt locks to the ICH7's memorymapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which means potential deadlock conditions may occur. Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2) Memory Range 0000 0000h-000D FFFFh 0010 0000h-TOM (Top of Memory) 000E 0000h-000E FFFFh 000F 0000h-000F FFFFh FEC0 0000h-FEC0 0100h FED4 0000h-FED4 0FFFh FFC0 0000h-FFC7 FFFFh FF80 0000h-FF87 FFFFh FFC8 0000h-FFCF FFFFh FF88 0000h-FF8F FFFFh Main Memory Firmware Hub Firmware Hub I/O APIC inside Intel(R) ICH7 TPM on LPC Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Bit 8 in Firmware Hub Decode Enable register is set Bit 9 in Firmware Hub Decode Enable register is set TOM registers in Host controller Bit 6 in Firmware Hub Decode Enable register is set Bit 7 in Firmware Hub Decode Enable register is set Target Dependency/Comments Intel (R) ICH7 Family Datasheet 259 Register and Memory Mapping Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2) Memory Range FFD0 0000h-FFD7 FFFFh FF90 0000h-FF97 FFFFh FFD8 0000h-FFDF FFFFh FF98 0000h-FF9F FFFFh FFE0 000h-FFE7 FFFFh FFA0 0000h-FFA7 FFFFh FFE8 0000h-FFEF FFFFh FFA8 0000h-FFAF FFFFh FFF0 0000h-FFF7 FFFFh FFB0 0000h-FFB7 FFFFh FFF8 0000h-FFFF FFFFh FFB8 0000h-FFBF FFFFh FF70 0000h-FF7F FFFFh FF30 0000h-FF3F FFFFh FF60 0000h-FF6F FFFFh FF20 0000h-FF2F FFFFh FF50 0000h-FF5F FFFFh FF10 0000h-FF1F FFFFh FF40 0000h-FF4F FFFFh FF00 0000h-FF0F FFFFh 4 KB anywhere in 4-GB range 1 KB anywhere in 4-GB range 512 B anywhere in 4-GB range 256 B anywhere in 4-GB range 512 B anywhere in 64-bit addressing space FED0 X000h-FED0 X3FFh All other Target Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Firmware Hub (or PCI)1 Integrated LAN Controller2 USB EHCI Controller 2 AC '97 Host Controller (Mixer) AC '97 Host Controller (Bus Master) Intel(R) High Definition Audio Host Controller High Precision Event Timers 3 PCI Dependency/Comments Bit 10 in Firmware Hub Decode Enable register is set Bit 11 in Firmware Hub Decode Enable register is set Bit 12 in Firmware Hub Decode Enable register is set Bit 13 in Firmware Hub Decode Enable register is set Bit 14 in Firmware Hub Decode Enable register is set Always enabled. The top two, 64 KB blocks of this range can be swapped, as described in Section 7.4.1. Bit 3 in Firmware Hub Decode Enable register is set Bit 2 in Firmware Hub Decode Enable register is set Bit 1 in Firmware Hub Decode Enable register is set Bit 0 in Firmware Hub Decode Enable register is set Enable via BAR in Device 29:Function 0 (Integrated LAN Controller) Enable via standard PCI mechanism (Device 29, Function 7) Enable via standard PCI mechanism (Device 30, Function 2) Enable via standard PCI mechanism (Device 30, Function 3) Enable via standard PCI mechanism (Device 30, Function 1) BIOS determines the "fixed" location which is one of four, 1-KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. None NOTES: 1. PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Config Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits have no effect. 2. Only LAN cycles can be seen on PCI. 3. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 260 Intel (R) ICH7 Family Datasheet Register and Memory Mapping 6.4.1 Boot-Block Update Scheme The ICH7 supports a "top-block swap" mode that has the ICH7 swap the top block in the Firmware Hub (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the "TOP_SWAP" Enable bit is set, the ICH7 will invert A16 for cycles targeting Firmware Hub space. When this bit is 0, the ICH7 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the "boot" block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be directed to FFFE_0000h through FFFE_FFFFh in the Firmware Hub, and processor accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h through FFFF_FFFFh. 4. Software erases the top block 5. Software writes the new top block 6. Software checks the new top block 7. Software clears the TOP_SWAP bit 8. Software sets the Top_Swap Lock-Down bit If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (See Section 2.24.1). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Top-block swap mode only affects accesses to the Firmware Hub space, not feature space. The top-block swap mode has no effect on accesses below FFFE_0000h. Note: Note: Intel (R) ICH7 Family Datasheet 261 Register and Memory Mapping 262 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7 Chipset Configuration Registers This chapter describes all registers and base functionality that is related to chipset configuration and not a specific interface (e.g., LPC, PCI, or PCI Express*). It contains the root complex register block that describes the behavior of the upstream internal link. This block is mapped into memory space, using register RCBA of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DWord) bit quantities. Burst accesses are not allowed. 7.1 Note: . Chipset Configuration Registers (Memory Space) Address locations that are not shown should be treated as Reserved (see Section 6.2 for details). Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3) Offset 0000-0003h 0004-0007h 0008-000Bh 000C-000Dh 000E-000Fh 0010-0013h 0014-0017h 001A-001Bh 001C-001Fh 0020-0023h 0026-0027h 0100-0103h 0104-0107h 0110-0113h 0118-011Fh 0120-0123h 0128-012Fh 0130-0133h 0138-013Fh 0140-0143h Mnemonic VCH VCAP1 VCAP2 PVC PVS V0CAP V0CTL V0STS V1CAP V1CTL V1STS RCTCL ESD ULD ULBA RP1D RP1BA RP2D RP2BA RP3D Register Name Virtual Channel Capability Header Virtual Channel Capability #1 Virtual Channel Capability #2 Port Virtual Channel Control Port Virtual Channel Status Virtual Channel 0 Resource Capability Virtual Channel 0 Resource Control Virtual Channel 0 Resource Status Virtual Channel 1 Resource Capability Virtual Channel 1 Resource Control Virtual Channel 1 Resource Status Root Complex Topology Capability List Element Self Description Upstream Link Descriptor Upstream Link Base Address Root Port 1 Descriptor Root Port 1 Base Address Root Port 2 Descriptor Root Port 2 Base Address Root Port 3 Descriptor Default 10010002h 00000801h 00000001h 0000h 0000h 00000001h 800000FFh 0000h 30008010h 00000000h 0000h 1A010005h 00000602h 00000001h 0000000000000000h 01xx0002h 00000000000E0000h 02xx0002h 00000000000E1000h 03xx0002h Type RO RO RO R/W, RO RO RO R/W, RO RO R/WO, RO R/W, RO RO RO R/WO, RO R/WO, RO R/WO R/WO, RO RO R/WO, RO RO R/WO, RO Table 7-1. Intel (R) ICH7 Family Datasheet 263 Chipset Configuration Registers Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3) Offset 0148-014Fh 0150-0153h 0158-015Fh 0160-0163h 0168-016Fh 0170-0173h 0178-017Fh 0180-0183h 0188-018Fh 01A0-01A3h 01A4-01A7h 01A8-01A9h 01AA-01ABh 0224-0227h 0238-023Bh 1E00-1E03h 1E10-1E17h 1E18-1E1Fh 1E80-1E87h 1E88-1E8Fh 1E90-1E97h 1E98-1E9Fh 3000-3001h 3100-3103h 3104-3107h 3108-310Bh 310C-310Fh 3110-3113h 3140-3141h 3142-3143h 3144-3145h 3146-3147h 3148-3149h 31FF-31FFh 3400-3403h 3404-3407h Mnemonic RP3BA RP4D RP4BA HDD HDBA RP5D RP5BA RP6D RP6BA ILCL LCAP LCTL LSTS RPC RPFN TRSR TRCR TWDR IOTR0 IOTR1 IOTR2 IOTR3 TCTL D31IP D30IP D29IP D28IP D27IP D31IR D30IR D29IR D28IR D27IR OIC RC HPTC Register Name Root Port 3 Base Address Root Port 4 Descriptor Root Port 4 Base Address Intel(R) High Definition Audio Descriptor Intel(R) High Definition Audio Base Address Root Port 5 Descriptor Root Port 5 Base Address Root Port 6 Descriptor Root Port 6 Base Address Internal Link Capability List Link Capabilities Link Control Link Status Root Port Configuration Root Port Function Number for PCI Express Root Ports (Desktop and Mobile only) Trap Status Register Trapped Cycle Register Trapped Write Data Register I/O Trap Register 0 I/O Trap Register 1 I/O Trap Register 2 I/O Trap Register 3 TCO Control Device 31 Interrupt Pin Device 30 Interrupt Pin Device 29 Interrupt Pin Device 28 Interrupt Pin Device 27 Interrupt Pin Device 31 Interrupt Route Device 30 Interrupt Route Device 29 Interrupt Route Device 28 Interrupt Route Device 27 Interrupt Route Other Interrupt Control RTC Configuration High Precision Timer Configuration Default 00000000000E2000h 04xx0002h 00000000000E3000h 05xx0002h 00000000000D8000 h 05xx0002h 00000000000E4000h 06xx0002h 00000000000E5000h 00010006h 00012441h 0000h 0041h 0000000xh 00543210h 00h 0000000000000000h 0000000000000000h 0000000000000000h 0000000000000000h 0000000000000000h 0000000000000000h 00h 00042210h 00002100h 10004321h 00004321h 00000001h 3210h 3210h 3210h 3210h 3210h 00h 00000000h 00000000h Type RO R/WO, RO RO R/WO, RO RO R/WO, RO RO R/WO, RO RO RO RO, R/WO R/W RO R/W, RO R/WO, RO R/WC, RO RO RO R/W, RO R/W, RO R/W, RO R/W, RO R/W R/W, RO R/W, RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W, R/WLO R/W 264 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3) Offset 3410-3413h Mnemonic GCS Register Name General Control and Status Default 0000000xh 0000001xb (Mobile/Ultra Mobile Only) 0000000xb (Desktop Only) 3418-341Bh 341C-341Fh FD CG Function Disable Clock Gating (Mobile/Ultra Mobile Only) See bit description 00000000h R/W, RO R/W, RO Type R/W, R/WLO 3414-3414h BUC Backed Up Control R/W 7.1.1 VCH--Virtual Channel Capability Header Register Offset Address: 0000-0003h Default Value: 10010002h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32-bit Next Capability Offset (NCO) -- RO.This field indicates the next item in the list. Capability Version (CV) -- RO. This field indicates support as a version 1 capability structure. Capability ID (CID) -- RO. This field indicates this is the Virtual Channel capability item. 7.1.2 VCAP1--Virtual Channel Capability #1 Register Offset Address: 0004-0007h Default Value: 00000801h Bit 31:12 11:10 9:8 7 6:4 3 2:0 Reserved Port Arbitration Table Entry Size (PATS) -- RO. This field indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). Reference Clock (RC) -- RO. Fixed at 100 ns. Reserved Low Priority Extended VC Count (LPEVC) -- RO. This field indicates that there are no additional VCs of low priority with extended capabilities. Reserved Extended VC Count (EVC) -- RO. This field indicates that there is one additional VC (VC1) that exists with extended capabilities. Attribute: Size: Description RO 32-bit Intel (R) ICH7 Family Datasheet 265 Chipset Configuration Registers 7.1.3 VCAP2--Virtual Channel Capability #2 Register Offset Address: 0008-000Bh Default Value: 00000001h Bit 31:24 23:8 7:0 Attribute: Size: Description RO 32-bit VC Arbitration Table Offset (ATO) -- RO. This field indicates that no table is present for VC arbitration since it is fixed. Reserved VC Arbitration Capability (AC) -- RO. This field indicates that the VC arbitration is fixed in the root complex. VC1 is highest priority and VC0 is lowest priority. 7.1.4 PVC--Port Virtual Channel Control Register Offset Address: 000C-000Dh Default Value: 0000h Bit 15:04 3:1 Reserved VC Arbitration Select (AS) -- RO. This field indicates which VC should be programmed in the VC arbitration table. The root complex takes no action on the setting of this field since there is no arbitration table. Load VC Arbitration Table (LAT) -- RO. This bit indicates that the table programmed should be loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on reads. Attribute: Size: Description R/W, RO 16-bit 0 7.1.5 PVS--Port Virtual Channel Status Register Offset Address: 000E-000Fh Default Value: 0000h Bit 15:01 0 Reserved VC Arbitration Table Status (VAS) -- RO. This bit indicates the coherency status of the VC Arbitration table when it is being updated. This field is always 0 in the root complex since there is no VC arbitration table. Attribute: Size: Description RO 16-bit 266 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.6 V0CAP--Virtual Channel 0 Resource Capability Register Offset Address: 0010-0013h Default Value: 00000001h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32-bit Port Arbitration Table Offset (AT) -- RO. This VC implements no port arbitration table since the arbitration is fixed. Reserved Maximum Time Slots (MTS) -- RO. This VC implements fixed arbitration, and therefore this field is not used. Reject Snoop Transactions (RTS) -- RO. This VC must be able to take snoopable transactions. Advanced Packet Switching (APS) -- RO. This VC is capable of all transactions, not just advanced packet switching transactions. Reserved Port Arbitration Capability (PAC) -- RO. This field indicates that this VC uses fixed port arbitration. 7.1.7 V0CTL--Virtual Channel 0 Resource Control Register Offset Address: 0014-0017h Default Value: 800000FFh Bit 31 30:27 26:24 23:20 19:17 Attribute: Size: Description R/W, RO 32-bit Virtual Channel Enable (EN) -- RO. Always set to 1. VC0 is always enabled and cannot be disabled. Reserved Virtual Channel Identifier (ID) -- RO. This field indicates the ID to use for this virtual channel. Reserved Port Arbitration Select (PAS) -- R/W. This field indicates which port table is being programmed. The root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. Load Port Arbitration Table (LAT) -- RO. The root complex does not implement an arbitration table for this virtual channel. Reserved Transaction Class / Virtual Channel Map (TVM) -- R/W. This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved 16 15:8 7:1 0 Intel (R) ICH7 Family Datasheet 267 Chipset Configuration Registers 7.1.8 V0STS--Virtual Channel 0 Resource Status Register Offset Address: 001A-001Bh Default Value: 0000h Bit 15:02 1 0 Reserved VC Negotiation Pending (NP) -- RO. When set, this bit indicates the virtual channel is still being negotiated with ingress ports. Port Arbitration Tables Status (ATS) -- RO. There is no port arbitration table for this VC, so this bit is reserved at 0. Attribute: Size: Description RO 16-bit 7.1.9 V1CAP--Virtual Channel 1 Resource Capability Register Offset Address: 001C-001Fh Default Value: 30008010h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description R/WO, RO 32-bit Port Arbitration Table Offset (AT) -- RO. This field indicates the location of the port arbitration table in the root complex. A value of 3h indicates the table is at offset 30h. Reserved Maximum Time Slots (MTS) -- R/WO. This value is updated by platform BIOS based upon the determination of the number of time slots available in the platform. Reject Snoop Transactions (RTS) -- RO. All snoopable transactions on VC1 are rejected. This VC is for isochronous transfers only. Advanced Packet Switching (APS) -- RO. This VC is capable of all transactions, not just advanced packet switching transactions. Reserved Port Arbitration Capability (PAC) -- RO. This field indicates the port arbitration capability is time-based WRR of 128 phases. 268 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.10 V1CTL--Virtual Channel 1 Resource Control Register Offset Address: 0020-0023h Default Value: 00000000h Bit 31 30:27 26:24 23:20 19:17 0 = Disables the VC. 1 = Enables the VC. Reserved Virtual Channel Identifier (ID) -- R/W. This field indicates the ID to use for this virtual channel. Reserved Port Arbitration Select (PAS) -- R/W. This field indicates which port table is being programmed. The only permissible value of this field is 4h for the time-based WRR entries. Load Port Arbitration Table (LAT) -- RO/W. When set, the port arbitration table loaded is based upon the PAS field in this register. This bit always returns 0 when read. Reserved Transaction Class / Virtual Channel Map (TVM) -- R/W. This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Reserved Attribute: Size: Description R/W, RO 32-bit Virtual Channel Enable (EN) -- R/W. 16 15:8 7:1 0 7.1.11 V1STS--Virtual Channel 1 Resource Status Register Offset Address: 0026-0027h Default Value: 0000h Bit 15:02 1 Reserved VC Negotiation Pending (NP) -- RO. 0 = Virtual channel is Not being negotiated with ingress ports. 1 = The virtual channel is still being negotiated with ingress ports. Port Arbitration Tables Status (ATS) -- RO. This field indicates the coherency status of the port arbitration table. This bit is set when LAT (offset 000Ch:bit 0) is written with value 1 and PAS (offset 0014h:bits19:17) has value of 4h. This bit is cleared after the table has been updated. Attribute: Size: Description RO 16-bit 0 Intel (R) ICH7 Family Datasheet 269 Chipset Configuration Registers 7.1.12 RCTCL--Root Complex Topology Capabilities List Register Offset Address: 0100-0103h Default Value: 1A010005h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32-bit Next Capability (NEXT) -- RO. This field indicates the next item in the list. Capability Version (CV) -- RO. This field indicates the version of the capability structure. Capability ID (CID) -- RO. This field indicates this is a PCI Express* link capability section of an RCRB. 7.1.13 ESD--Element Self Description Register Offset Address: 0104-0107h Default Value: 00000602h Bit 31:24 23:16 Attribute: Size: Description R/WO, RO 32-bit Port Number (PN) -- RO. A value of 0 to indicate the egress port for the Intel(R) ICH7. Component ID (CID) -- R/WO. This field indicates the component ID assigned to this element by software. This is written once by platform BIOS and is locked until a platform reset. Number of Link Entries (NLE) -- RO. This field indicates that one link entry (corresponding to DMI), 6 root port entries (for the downstream ports), and the Intel(R) High Definition Audio device are described by this RCRB. Reserved Element Type (ET) -- RO. This field indicates that the element type is a root complex internal link. 15:8 7:4 3:0 7.1.14 ULD--Upstream Link Descriptor Register Offset Address: 0110-0113h Default Value: 00000001h Bit 31:24 23:16 15:2 1 0 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- R/WO. This field is programmed by platform BIOS to match the port number of the (G)MCH RCRB that is attached to this RCRB. Target Component ID (TCID) -- R/WO. This field is programmed by platform BIOS to match the component ID of the (G)MCH RCRB that is attached to this RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to the (G)MCH RCRB. Link Valid (LV) -- RO. This bit indicates that the link entry is valid. 270 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.15 ULBA--Upstream Link Base Address Register Offset Address: 0118-011Fh Default Value: 0000000000000000h Bit 63:32 Attribute: Size: Description R/WO 64-bit Base Address Upper (BAU) -- R/WO. This field is programmed by platform BIOS to match the upper 32-bits of base address of the (G)MCH RCRB that is attached to this RCRB. Base Address Lower (BAL) -- R/WO. This field is programmed by platform BIOS to match the lower 32-bits of base address of the (G)MCH RCRB that is attached to this RCRB. 31:0 7.1.16 RP1D--Root Port 1 Descriptor Register Offset Address: 0120-0123h Default Value: 01xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates that the target port number is 1h (root port #1). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1). 23:16 15:2 1 0 7.1.17 RP1BA--Root Port 1 Base Address Register Offset Address: 0128-012Fh Default Value: 00000000000E0000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #0. Reserved Attribute: Size: Description RO 64-bit Intel (R) ICH7 Family Datasheet 271 Chipset Configuration Registers 7.1.18 RP2D--Root Port 2 Descriptor Register Offset Address: 0130-0133h Default Value: 02xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 2h (root port #2). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When RPC.PC (offset 0224h, bits 1:0) is `01', `10', or `11', or FD.PE2D (offset 3418h, bit 17) is set, the link for this root port is not valid (return 0). When RPC.PC is `00' and FD.PE2D is cleared, the link for this root port is valid (return 1). 23:16 15:2 1 0 7.1.19 RP2BA--Root Port 2 Base Address Register Offset Address: 0138-013Fh Default Value: 00000000000E1000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #1. Reserved Attribute: Size: Description RO 64-bit 7.1.20 RP3D--Root Port 3 Descriptor Register Offset Address: 0140-0143h Default Value: 03xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 3h (root port #3). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When RPC.PC (offset 0224h, bits 1:0) is `11', or FD.PE3D (offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). When RPC.PC is `00', `01', or "10', and FD.PE3D is cleared, the link for this root port is valid (return 1). 23:16 15:2 1 0 272 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.21 RP3BA--Root Port 3 Base Address Register Offset Address: 0148-014Fh Default Value: 00000000000E2000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #2. Reserved Attribute: Size: Description RO 64-bit 7.1.22 RP4D--Root Port 4 Descriptor Register Offset Address: 0150-0153h Default Value: 04xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 4h (root port #4). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When RPC.PC (offset 0224h, bits 1:0) is `10' or `11', or FD.PE4D (offset 3418h, bit 19) is set, the link for this root port is not valid (return 0). When RPC.PC is `00' or `01' and FD.PE4D is cleared, the link for this root port is valid (return 1). 23:16 15:2 1 0 7.1.23 RP4BA--Root Port 4 Base Address Register Offset Address: 0158-015Fh Default Value: 00000000000E3000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #3. Reserved Attribute: Size: Description RO 64-bit Intel (R) ICH7 Family Datasheet 273 Chipset Configuration Registers 7.1.24 HDD--Intel(R) High Definition Audio Descriptor Register Offset Address: 0160-0163h Default Value: 15xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 15h (Intel(R) High Definition Audio). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When FD.ZD (offset 3418h, bit 4) is set, the link to Intel High Definition Audio is not valid (return 0). When FD.ZD is cleared, the link to Intel High Definition Audio is valid (return 1). 23:16 15:2 1 0 7.1.25 HDBA--Intel(R) High Definition Audio Base Address Register Offset Address: 0168-016Fh Default Value: 00000000000D8000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #27. Function Number (FN) -- RO. This field indicates the root port is on function #0. Reserved Attribute: Size: Description RO 64-bit 7.1.26 RP5D--Root Port 5 Descriptor Register Offset Address: 0170-0173h Default Value: 05xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 5h (root port #5). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When FD.PE5D (offset 3418h, bit 20) is set, the link for this root port is not valid (return 0). When FD.PE5D is cleared, the link for this root port is valid (return 1). 23:16 15:2 1 0 274 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.27 RP5BA--Root Port 5 Base Address Register Offset Address: 0178-017Fh Default Value: 00000000000E4000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #4. Reserved Attribute: Size: Description RO 64-bit 7.1.28 RP6D--Root Port 6 Descriptor Register Offset Address: 0180-0183h Default Value: 06xx0002h Bit 31:24 Attribute: Size: Description R/WO, RO 32-bit Target Port Number (PN) -- RO. This field indicates the target port number is 6h (root port #6). Target Component ID (TCID) -- R/WO. This field returns the value of the ESD.CID (offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved Link Type (LT) -- RO. This bit indicates that the link points to a root port. Link Valid (LV) -- RO. When RPC.PC2 (offset 0224h, bits 1:0) is `01' or FD.PE6D (offset 3418h, bit 21) is set, the link for this root port is not valid (return 0). When RPC.PC is `00' and FD.PE6D is cleared, the link for this root port is valid (return 1). 23:16 15:2 1 0 7.1.29 RP6BA--Root Port 6 Base Address Register Offset Address: 0188-018Fh Default Value: 00000000000E5000h Bit 63:32 31:28 27:20 19:15 14:12 11:0 Reserved Reserved Bus Number (BN) -- RO. This field indicates the root port is on bus #0. Device Number (DN) -- RO. This field indicates the root port is on device #28. Function Number (FN) -- RO. This field indicates the root port is on function #5. Reserved Attribute: Size: Description RO 64-bit Intel (R) ICH7 Family Datasheet 275 Chipset Configuration Registers 7.1.30 ILCL--Internal Link Capabilities List Register Offset Address: 01A0-01A3h Default Value: 00010006h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32-bit Next Capability Offset (NEXT) -- RO. Indicates this is the last item in the list. Capability Version (CV) -- RO. This field indicates the version of the capability structure. Capability ID (CID) -- RO. This field indicates this is capability for DMI. 7.1.31 LCAP--Link Capabilities Register Offset Address: 01A4-01A7h Default Value: 00012441h Bit 31:18 17:15 Desktop Only 17:15 Mobile/ Ultra Mobile Only 14:12 11:10 Desktop Only 11:10 Mobile/ Ultra Mobile Only 9:4 3:0 L1 Exit Latency (EL1) -- RO. This field is set to 010b to indicate an exit latency of 2 us to 4 us. L1 Exit Latency (EL1) -- L1 not supported on DMI. Reserved Attribute: Size: Description RO/ R/WO 32-bit L0s Exit Latency (EL0) -- R/WO. This field indicates that exit latency is 128 ns to less than 256 ns. Active State Link PM Support (ASPM) -- R/WO. This field indicates that L0s is supported on DMI. Active State Link PM Support (ASPM) -- R/WO. This field indicates the level of active state power management on DMI. 00 = Neither L0s nor L1s are supported 01 = L0s Entry supported on DMI 10 = L1 Entry supported on DMI 11 = Both L0s and L1 supported on DMI Maximum Link Width (MLW) -- Indicates the maximum link width is 4 ports. Maximum Link Speed (MLS) -- Indicates the link speed is 2.5 Gb/s. 276 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.32 LCTL--Link Control Register Offset Address: 01A8-01A9h Default Value: 0000h Bit 15:8 7 6:2 Reserved Extended Synch (ES) -- R/W. When set, this bit forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Mobile/ Ultra Mobile Only) at exit from L1 prior to entering L0. Reserved Active State Link PM Control (APMC) -- R/W. This field indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s entry enabled 10 = Reserved 11 = Reserved 1:0 Mobile/ Ultra Mobile Only Active State Link PM Control (APMC) -- R/W. This field indicates whether DMI should enter L0s or L1 or both. 00 = Disabled 01 = L0s entry enabled 10 = L1 Entry enabled 11 = L0s and L1 Entry enabled Attribute: Size: Description R/W 16-bit 1:0 Desktop Only 7.1.33 LSTS--Link Status Register Offset Address: 01AA-01ABh Default Value: 0041h Bit 15:10 9:4 3:0 Reserved Negotiated Link Width (NLW) -- RO. Negotiated link width is x4 (000100b). Mobile/Ultra Mobile only: The ICH7 may also indicate x2 (000010b), depending on (G)MCH configuration. Link Speed (LS) -- RO. Link is 2.5 Gb/s. Attribute: Size: Description RO 16-bit Intel (R) ICH7 Family Datasheet 277 Chipset Configuration Registers 7.1.34 RPC--Root Port Configuration Register Offset Address: 0224-0227h Default Value: 0000000yh (y = 00xxb) Bit 31:8 Reserved High Priority Port Enable (HPE) -- R/W. 7 0 = The high priority path is not enabled. 1 = The port selected by the HPP field in this register is enabled for high priority. It will be arbitrated above all other VC0 (including integrated VC0) devices. High Priority Port (HPP) -- R/W. This field controls which port is enabled for high priority when the HPE bit in this register is set. 111 = Reserved 110 = Reserved 6:4 101 = Port 6 100 = Port 5 100 = Port 4 010 = Port 3 001 = Port 2 000 = Port 1 3 Reserved Port Configuration2 (PC2) -- RO. This bit controls how the PCI bridges are organized in various modes of operation for Ports 5 and 6. 2 1 = Reserved 0 = 2 x1s, Port 5 (x1), Port 6 (x1) This bit is in the resume well and is only reset by RSMRST#. Port Configuration (PC) -- RO. This field controls how the PCI bridges are organized in various modes of operation. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0) when TP3 is not pulled low at the rising edge of PWROK. 11 = 1 x4, Port 1 (x4) 10 = Reserved 01 = Reserved 00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1) These bits live in the resume well and are only reset by RSMRST#. Attribute: Size: Description R/W, RO 32-bit 1:0 278 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.35 RPFN--Root Port Function Number for PCI Express Root Ports (Desktop and Mobile only) Offset Address: 0238-023Bh Default Value: 00543210h Attribute: Size: R/WO, RO 32-bit For the PCI Express root ports, the assignment of a function number to a root port is not fixed. BIOS may re-assign the function numbers on a port by port basis. This capability will allow BIOS to disable/hide any root port and have still have functions 0 thru N-1 where N is the total number of enabled root ports. Port numbers will remain fixed to a physical root port. The existing root port Function Disable registers operate on physical ports (not functions). Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number assignment and is associated with physical ports. Bit 31:23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3 2:0 Reserved Root Port 6 Function Number (RP6FN) -- R/WO. These bits set the function number for PCI Express Root Port 6. This root port function number must be a unique value from the other root port function numbers. Reserved Root Port 5 Function Number (RP5FN) -- R/WO. These bits set the function number for PCI Express Root Port 5. This root port function number must be a unique value from the other root port function numbers. Reserved Root Port 4 Function Number (RP4FN) -- R/WO. These bits set the function number for PCI Express Root Port 4. This root port function number must be a unique value from the other root port function numbers. Reserved Root Port 3 Function Number (RP3FN) -- R/WO. These bits set the function number for PCI Express Root Port 3. This root port function number must be a unique value from the other root port function numbers. Reserved Root Port 2 Function Number (RP2FN) -- R/WO. These bits set the function number for PCI Express Root Port 2. This root port function number must be a unique value from the other root port function numbers. Reserved Root Port 1 Function Number (RP1FN) -- R/WO. These bits set the function number for PCI Express Root Port 1. This root port function number must be a unique value from the other root port function numbers. Description Intel (R) ICH7 Family Datasheet 279 Chipset Configuration Registers 7.1.36 TRSR--Trap Status Register Offset Address: 1E00-1E03h Default Value: 00000000h Bit 31:4 Reserved Cycle Trap SMI# Status (CTSS) -- R/WC. These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR'ed together to create a single status bit in the Power Management register space. 3:0 Note that the SMI# and trapping must be enabled in order to set these bits. These bits are set before the completion is generated for the trapped cycle, thereby completes. Each status bit is cleared by writing a 1 to the corresponding bit location in this register. Attribute: Size: Description R/WC, RO 32-bit ensuring that the processor can enter the SMI# handler when the instruction 7.1.37 TRCR--Trapped Cycle Register Offset Address: 1E10-1E17h Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read. Bit 63:25 24 23:20 19:16 Reserved Read/Write# (RWI) -- RO. 0 = Trapped cycle was a write cycle. 1 = Trapped cycle was a read cycle. Reserved Active-high Byte Enables (AHBE) -- RO. This is the DWord-aligned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle. Trapped I/O Address (TIOA) -- RO. This is the DWord-aligned address of the trapped cycle. Reserved Description 15:2 1:0 7.1.38 TWDR--Trapped Write Data Register Offset Address: 1E18-1E1Fh Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves the data from I/O write cycles that are trapped for software to read. Bit 63:32 31:0 Reserved Trapped I/O Data (TIOD) -- RO. DWord of I/O write data. This field is undefined after trapping a read cycle. Description 280 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.39 IOTRn -- I/O Trap Register (0-3) Offset Address: 1E80-1E87h Register 0 1E88-1E8Fh Register 1 1E90-1E97h Register 2 1E98-1E9Fh Register 3 Default Value: 0000000000000000h Attribute: R/W, RO Size: 64-bit These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality. Bit 63:50 49 Reserved Read/Write Mask (RWM) -- R/W. 0 = The cycle must match the type specified in bit 48. 1 = Trapping logic will operate on both read and write cycles. Read/Write# (RWIO) -- R/W. 48 0 = Write 1 = Read NOTE: The value in this field does not matter if bit 49 is set. Reserved Byte Enable Mask (BEM) -- R/W. A 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit in the Byte Enables field, below, is ignored. Byte Enables (TBE) -- R/W. Active-high DWord-aligned byte enables. Reserved Address[7:2] Mask (ADMA) -- R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for traps on address ranges up to 256 bytes in size. Reserved I/O Address[15:2] (IOAD) -- R/W. DWord-aligned address Reserved Trap and SMI# Enable (TRSE) -- R/W. 0 0 = Trapping and SMI# logic disabled. 1 = The trapping logic specified in this register is enabled. Description 47:40 39:36 35:32 31:24 23:18 17:16 15:2 1 Intel (R) ICH7 Family Datasheet 281 Chipset Configuration Registers 7.1.40 TCTL--TCO Configuration Register Offset Address: 3000-3000h Default Value: 00h Bit TCO IRQ Enable (IE) -- R/W. 7 6:3 0 = TCO IRQ is disabled. 1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field. Reserved TCO IRQ Select (IS) -- R/W. Specifies on which IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and can be shared with other interrupt. 000 = IRQ 9 001 = IRQ 10 010 = IRQ 11 011 = Reserved 2:0 100 = IRQ 20 (only if APIC enabled) 101 = IRQ 21 (only if APIC enabled) 110 = IRQ 22 (only if APIC enabled) 111 = IRQ 23 (only if APIC enabled) NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching. NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for activelow reception. Attribute: Size: Description R/W 8-bit 282 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.41 D31IP--Device 31 Interrupt Pin Register Offset Address: 3100-3103h Default Value: 00042210h Bit 31:16 Reserved SM Bus Pin (SMIP) -- R/W. This field indicates which pin the SMBus controller drives as its interrupt. 0h = No interrupt 15:12 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved SATA Pin (SIP) -- R/W. This field indicates which pin the SATA controller drives as its interrupt. 0h = No interrupt 11:8 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved PATA Pin (PIP) -- R/W. This field indicates which pin the PATA controller drives as its interrupt. 0h = No interrupt 7:4 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved 3:0 PCI Bridge Pin (PCIP) -- RO. Currently, the PCI bridge does not generate an interrupt, so this field is read-only and 0. Attribute: Size: Description R/W, RO 32-bit Intel (R) ICH7 Family Datasheet 283 Chipset Configuration Registers 7.1.42 D30IP--Device 30 Interrupt Pin Register Offset Address: 3104-3107h Default Value: 00002100h Bit 31:16 Reserved AC `97 Modem Pin (AMIP) -- R/W. This field indicates which pin the AC `97 Modem controller drives as its interrupt. 15:12 (Desktop and Mobile Only) 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved 15:12 (Ultra Mobile Only) Attribute: Size: Description R/W, RO 32-bit Reserved AC `97 Audio Pin (AAIP) -- R/W. This field indicates which pin the AC `97 audio controller drives as its interrupt. 11:8 (Desktop and Mobile Only) 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved 11:8 (Ultra Mobile Only) 7:4 3:0 Reserved Reserved LPC Bridge Pin (LIP) -- RO. Currently, the LPC bridge does not generate an interrupt, so this field is read-only and 0. 284 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.43 D29IP--Device 29 Interrupt Pin Register Offset Address: 3108-310Bh Default Value: 10004321h Bit Attribute: Size: Description R/W 32-bit EHCI Pin (EIP) -- R/W. This field indicates which pin the EHCI controller drives as its interrupt. 0h = No interrupt 31:28 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved 27:16 Reserved UHCI #3 Pin (U3P) -- R/W. This field indicates which pin the UHCI controller #3 (ports 6 and 7) drives as its interrupt. 0h = No interrupt 15:12 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h-Fh = Reserved UHCI #2 Pin (U2P) -- R/W. This field indicates which pin the UHCI controller #2 (ports 4 and 5) drives as its interrupt. 0h = No interrupt 11:8 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h-Fh = Reserved UHCI #1 Pin (U1P) -- R/W. This field indicates which pin the UHCI controller #1 (ports 2 and 3) drives as its interrupt. 0h = No interrupt 7:4 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved UHCI #0 Pin (U0P) -- R/W. This field indicates which pin the UHCI controller #0 (ports 0 and 1) drives as its interrupt. 0h = No interrupt 3:0 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Intel (R) ICH7 Family Datasheet 285 Chipset Configuration Registers 7.1.44 D28IP--Device 28 Interrupt Pin Register (Desktop and Mobile Only) Offset Address: 310C-310Fh Default Value: 00214321h Bit 31:24 Reserved PCI Express #6 Pin (P6IP) -- R/W. This field indicates which pin the PCI Express* port #6 drives as its interrupt. 23:20 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved PCI Express #5 Pin (P5IP) -- R/W. This field indicates which pin the PCI Express port #5 drives as its interrupt. 19:16 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved PCI Express #4 Pin (P4IP) -- R/W. This field indicates which pin the PCI Express* port #4 drives as its interrupt. 15:12 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h-Fh = Reserved PCI Express #3 Pin (P3IP) -- R/W. This field indicates which pin the PCI Express port #3 drives as its interrupt. 11:8 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h-Fh = Reserved PCI Express #2 Pin (P2IP) -- R/W. This field indicates which pin the PCI Express port #2 drives as its interrupt. 7:4 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h-Fh = Reserved Attribute: Size: Description R/W 32-bit 286 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Bit Description PCI Express #1 Pin (P1IP) -- R/W.This field iIndicates which pin the PCI Express port #1 drives as its interrupt. 3:0 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved 7.1.45 D27IP--Device 27 Interrupt Pin Register Offset Address: 3110-3113h Default Value: 00000001h Bit 31:4 Reserved Intel(R) High Definition Audio Pin (ZIP) -- R/W. This field indicates which pin the Intel High Definition Audio controller drives as its interrupt. 0h = No interrupt 3:0 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h-Fh = Reserved Attribute: Size: Description R/W 32-bit 7.1.46 D31IR--Device 31 Interrupt Route Register Offset Address: 3140-3141h Default Value: 3210h Bit 15 Reserved Interrupt D Pin Route (IDR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 14:12 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: Ultra Mobile. PIRQA#-PIRQD# are not on the ICH7U. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 11 Reserved Attribute: Size: Description R/W 16-bit Intel (R) ICH7 Family Datasheet 287 Chipset Configuration Registers Bit Description Interrupt C Pin Route (ICR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTC# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 10:8 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7 Reserved Interrupt B Pin Route (IBR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTB# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 6:4 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 3 Reserved Interrupt A Pin Route (IAR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTA# pin reported for device 31 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 2:0 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 288 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.47 D30IR--Device 30 Interrupt Route Register Offset Address: 3142-3143h Default Value: 3210h Bit 15 Reserved Interrupt D Pin Route (IDR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTD# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 14:12 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a nonICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 11 Reserved Interrupt C Pin Route (ICR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTC# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 10:8 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7 Reserved Interrupt B Pin Route (IBR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTB# pin reported for device 30 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 6:4 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 3 Reserved Attribute: Size: Description R/W 16-bit Intel (R) ICH7 Family Datasheet 289 Chipset Configuration Registers Bit Description Interrupt A Pin Route (IAR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTA# pin reported for device 30 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 2:0 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7.1.48 D29IR--Device 29 Interrupt Route Register Offset Address: 3144-3145h Default Value: 3210h Bit 15 Reserved Interrupt D Pin Route (IDR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTD# pin reported for device 29 functions. 0h 1h 2h 3h 4h 5h 6h 7h = = = = = = = = PIRQA# PIRQB# PIRQC# PIRQD# (Default) PIRQE# PIRQF# PIRQG# PIRQH# Attribute: Size: Description R/W 16-bit 14:12 NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 11 Reserved Interrupt C Pin Route (ICR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTC# pin reported for device 29 functions. 0h 1h 2h 3h 4h 5h 6h 7h = = = = = = = = PIRQA# PIRQB# PIRQC# (Default) PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# 10:8 NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7 Reserved 290 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Bit Description Interrupt B Pin Route (IBR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTB# pin reported for device 29 functions. 0h 1h 2h 3h 4h 5h 6h 7h = = = = = = = = PIRQA# PIRQB# (Default) PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# 6:4 NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 3 Reserved Interrupt A Pin Route (IAR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTA# pin reported for device 29 functions. 0h 1h 2h 3h 4h 5h 6h 7h = = = = = = = = PIRQA# (Default) PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# 2:0 NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. Intel (R) ICH7 Family Datasheet 291 Chipset Configuration Registers 7.1.49 D28IR--Device 28 Interrupt Route Register Offset Address: 3146-3147h Default Value: 3210h Bit 15 Reserved Interrupt D Pin Route (IDR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTD# pin reported for device 28 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# PIRQC# PIRQD# (Default) PIRQE# PIRQF# PIRQG# Attribute: Size: Description R/W 16-bit 14:12 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 11 Reserved Interrupt C Pin Route (ICR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTC# pin reported for device 28 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# PIRQC# (Default) PIRQD# PIRQE# PIRQF# PIRQG# 10:8 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7 Reserved Interrupt B Pin Route (IBR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTB# pin reported for device 28 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# (Default) PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# 6:4 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 3 Reserved 292 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Bit Description Interrupt A Pin Route (IAR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTA# pin reported for device 28 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# (Default) PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# 2:0 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7.1.50 D27IR--Device 27 Interrupt Route Register Offset Address: 3148-3149h Default Value: 3210h Bit 15 Reserved Interrupt D Pin Route (IDR) -- R/W. This field indicates which physical pin on the Intel(R) ICH7 is connected to the INTD# pin reported for device 27 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# PIRQC# PIRQD# (Default) PIRQE# PIRQF# PIRQG# Attribute: Size: Description R/W 16-bit 14:12 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 11 Reserved Interrupt C Pin Route (ICR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTC# pin reported for device 27 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# PIRQC# (Default) PIRQD# PIRQE# PIRQF# PIRQG# 10:8 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7 Reserved Intel (R) ICH7 Family Datasheet 293 Chipset Configuration Registers Bit Description Interrupt B Pin Route (IBR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTB# pin reported for device 27 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# PIRQB# (Default) PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# 6:4 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 3 Reserved Interrupt A Pin Route (IAR) -- R/W. This field indicates which physical pin on the ICH7 is connected to the INTA# pin reported for device 27 functions. 0h 1h 2h 3h 4h 5h 6h = = = = = = = PIRQA# (Default) PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# 2:0 7h = PIRQH# NOTE: PIRQA#-PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-ICH7U pin routing, BIOS default sets the register for PIRQE#-PIRQH#. 7.1.51 OIC--Other Interrupt Control Register Offset Address: 31FF-31FFh Default Value: 00h Bit 7:2 Reserved Coprocessor Error Enable (CEN) -- R/W. 1 0 = FERR# will not generate IRQ13 nor IGNNE#. 1 = If FERR# is low, the Intel(R) ICH7 generates IRQ13 internally and holds it until an I/O port F0h write. It will also drive IGNNE# active. APIC Enable (AEN) -- R/W. 0 0 = The internal IOxAPIC is disabled. 1 = Enables the internal IOxAPIC and its address decode. Attribute: Size: Description R/W 8-bit 294 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.52 RC--RTC Configuration Register Offset Address: 3400-3403h Default Value: 00000000h Bit 31:5 Reserved Upper 128 Byte Lock (UL) -- R/WLO. 4 0 = Bytes not locked. 1 = Bytes 38h-3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return valid data. This bit is reset on system reset. Lower 128 Byte Lock (LL) -- R/WLO. 3 0 = Bytes not locked. 1 = Bytes 38h-3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return valid data. Bit reset on system reset. Upper 128 Byte Enable (UE) -- R/W. 2 1:0 0 = Bytes locked. 1 = The upper 128-byte bank of RTC RAM can be accessed. Reserved Attribute: Size: Description R/W, R/WLO 32-bit 7.1.53 HPTC--High Precision Timer Configuration Register Offset Address: 3404-3407h Default Value: 00000000h Bit 31:8 Reserved Address Enable (AE) -- R/W. 7 0 = Address disabled. 1 = The Intel(R) ICH7 will decode the High Precision Timer memory address range selected by bits 1:0 below. Reserved Address Select (AS) -- R/W. This field selects 1 of 4 possible memory address ranges for the High Precision Timer functionality. The encodings are: 1:0 00 = FED0_0000h - FED0_03FFh 01 = FED0_1000h - FED0_13FFh 10 = FED0_2000h - FED0_23FFh 11 = FED0_3000h - FED0_33FFh Attribute: Size: Description R/W 32-bit 6:2 Intel (R) ICH7 Family Datasheet 295 Chipset Configuration Registers 7.1.54 GCS--General Control and Status Register Offset Address: 3410-3413h Default Value: 00000yy0h (yy = xx0000x0b) Bit 31:12 Reserved Boot BIOS Straps (BBS): This field determines the destination of accesses to the BIOS memory range. The default values for these bits represent the strap values of GNT5#/GPIO17 (bit 11) and GNT4#/GPIO48 (bit 10) (active-high logic levels) at the rising edge of PWROK. Bits 11:10 00b 01b 10b 11:10 11b Description Reserved SPI (supports shared flash with LAN) PCI LPC Attribute:R/W, R/WLO Size: 32-bit Description When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is accepted by the primary side of the PCI-to-PCI bridge and forwarded to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to be set (nor any other bits) for these cycles to go to PCI. Note that BIOS decode range bits and the other BIOS protection bits have no effect when PCI is selected. When SPI or LPC is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down (bit 0) is not set. Server Error Reporting Mode (SERM) -- R/W. 0 = The Intel(R) ICH7 is the final target of all errors. The (G)MCH sends a messages to the ICH7 for the purpose of generating NMI. 1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this mode, if the ICH7 detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends a message to the (G)MCH. If the ICH7 receives an ERR_* message from the downstream port, it sends that message to the (G)MCH. Reserved Mobile IDE Configuration Lock Down (MICLD) -- R/WLO. 0 = Disabled. 1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system reset occurs. This prevents rogue software from changing the default state of the PATA pins during boot after BIOS configures them. This bit is write once, and is cleared by system reset and when returning from the S3/S4/S5 states. Reserved FERR# MUX Enable (FME) -- R/W. This bit enables FERR# to be a processor break event indication. 0 = Disabled. 1 = The ICH7-M examines FERR# during a C2, C3, or C4 state as a break event. See Chapter 5.14.5 for a functional description. 9 8 7 (Mobile/ Ultra Mobile Only) 7 (Desktop Only) 6 (Mobile/ Ultra Mobile Only) 296 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Bit 6 (Desktop Only) Reserved Description 5 No Reboot (NR) -- R/W. This bit is set when the "No Reboot" strap (SPKR pin on Intel(R) ICH7) is sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates "No Reboot". 0 = System will reboot upon the second timeout of the TCO timer. 1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot on the second timeout. Alternate Access Mode Enable (AME) -- R/W. 0 = Disabled. 1 = Alternate access read only registers can be written, and write only registers can be read. Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the ICH7 implements an alternate access mode. For a list of these registers see Section 5.14.10. Reserved. Reserved Page Route (RPR) -- R/W. This bit determines where to send the reserved page registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh. 0 = Writes will be forwarded to LPC, shadowed within the ICH7, and reads will be returned from the internal shadow 1 = Writes will be forwarded to PCI, shadowed within the ICH7, and reads will be returned from the internal shadow. NOTE: If some writes are completed to LPC/PCI to these I/O ranges, and then this bit is flipped such that writes will now go to the other interface, the reads will not return what was last written. Shadowing is performed on each interface. The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always decoded to LPC. 4 3 2 1 Reserved BIOS Interface Lock-Down (BILD) -- R/WLO. 0 = Disabled. 1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) from being changed. This bit can only be written from 0 to 1 once. 0 Intel (R) ICH7 Family Datasheet 297 Chipset Configuration Registers 7.1.55 BUC--Backed Up Control Register Offset Address: 3414-3414h Attribute: Size: Default Value: 0000000xb (Desktop Only) 0000001xb (Mobile/Ultra Mobile Only) R/W 8-bit All bits in this register are in the RTC well and only cleared by RTCRST#. Bit 7:3 Reserved CPU BIST Enable (CBE) -- R/W. This bit is in the resume well and is reset by RSMRST#, but not PLTRST# nor CF9h writes. 2 0 = Disabled. 1 = The INIT# signals will be driven active when CPURST# is active. INIT# and INIT3_3V# will go inactive with the same timings as the other processor I/F signals (hold time after CPURST# inactive). PATA Reset State (PRS) -- R/W. 0 = Disabled. 1 = The reset state of the PATA pins will be driven/tri-state. Description 1 (Mobile/ Ultra Mobile Only) 1 (Desktop Only) Reserved Top Swap (TS) -- R/W. 0 = Intel(R) ICH7 will not invert A16. 1 = ICH7 will invert A16 for cycles going to the BIOS space (but not the feature space) in the FWH. If the ICH7 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted. 0 298 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers 7.1.56 FD--Function Disable Register Offset Address: 3418-341Bh Default Value: See bit description Attribute: Size: R/W, RO 32-bit The UHCI functions must be disabled from highest function number to lowest. For example, if only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set). When disabling UHCIs, the EHCI Structural Parameters Registers must be updated with coherent information in "Number of Companion Controllers" and "N_Ports" fields. When disabling a function, only the configuration space is disabled. Software must ensure that all functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function. When a function is disabled, software must not attempt to re-enable it. A disabled function can only be re-enabled by a platform reset. Bit 31:22 Reserved PCI Express 6 Disable (PE6D) -- R/W. When disabled, the link for this port is put into the "link down" state. 21 0 = PCI Express* port #6 is enabled. (Default) 1 = PCI Express port #6 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. PCI Express 5 Disable (PE5D) -- R/W. When disabled, the link for this port is put into the link down state. 20 0 = PCI Express port #5 is enabled. (Default) 1 = PCI Express port #5 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. PCI Express 4 Disable (PE4D) -- R/W. DWhen disabled, the link for this port is put into the "link down" state. 19 0 = PCI Express* port #4 is enabled. (Default) 1 = PCI Express port #4 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. PCI Express 3 Disable (PE3D) -- R/W. When disabled, the link for this port is put into the link down state. 18 0 = PCI Express port #3 is enabled. (Default) 1 = PCI Express port #3 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. PCI Express 2 Disable (PE2D) -- R/W. When disabled, the link for this port is put into the link down state. 17 0 = PCI Express port #2 is enabled. (Default) 1 = PCI Express port #2 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. PCI Express 1 Disable (PE1D) -- R/W. When disabled, the link for this port is put into the link down state. 16 0 = PCI Express port #1 is enabled. (Default) 1 = PCI Express port #1 is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. Description Intel (R) ICH7 Family Datasheet 299 Chipset Configuration Registers Bit EHCI Disable (EHCID) -- R/W. 15 0 = The EHCI is enabled. (Default) 1 = The EHCI is disabled. Description LPC Bridge Disable (LBD) -- R/W. 0 = The LPC bridge is enabled. (Default) 1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional spaces will no longer be decoded by the LPC bridge: 14 * * * Memory cycles below 16 MB (1000000h) I/O cycles below 64 KB (10000h) The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is set, but the aliases at the top of 1 MB (the E and F segment) no longer will be decoded. 13:12 11 Reserved UHCI #4 Disable (U4D) -- R/W. 0 = The 4th UHCI (ports 6 and 7) is enabled. (Default) 1 = The 4th UHCI (ports 6 and 7) is disabled. UHCI #3 Disable (U3D) -- R/W. 10 0 = The 3rd UHCI (ports 4 and 5) is enabled. (Default) 1 = The 3rd UHCI (ports 4 and 5) is disabled. UHCI #2 Disable (U2D) -- R/W. 9 0 = The 2nd UHCI (ports 2 and 3) is enabled. (Default) 1 = The 2nd UHCI (ports 2 and 3) is disabled. UHCI #1 Disable (U1D) -- R/W. 8 0 = The 1st UHCI (ports 0 and 1) is enabled. (Default) 1 = The 1st UHCI (ports 0 and 1) is disabled. Hide Internal LAN (HIL) -- R/W. 7 0 = The LAN controller is enabled. (Default) 1 = The LAN controller is disabled and will not decode configuration cycles off of PCI NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. . AC `97 Modem Disable (AMD) -- R/W. 6 0 = The AC `97 modem function is enabled. (Default) 1 = The AC `97 modem function is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. AC `97 Audio Disable (AAD) -- R/W. 5 0 = The AC `97 audio function is enabled. (Default) 1 = The AC `97 audio function is disabled. NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. Intel(R) High Definition Audio Disable (ZD) -- R/W. 4 0 = The Intel High Definition Audio controller is enabled. (Default) 1 = The Intel High Definition Audio controller is disabled and its PCI configuration space is not accessible. SM Bus Disable (SD) -- R/W. 3 0 = The SM Bus controller is enabled. (Default) 1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/ O space. In the Intel(R) ICH7, it only disables the configuration space. 300 Intel (R) ICH7 Family Datasheet Chipset Configuration Registers Bit 0 = The SATA controller is enabled. 1 = The SATA controller is disabled. Description Serial ATA Disable (SAD) -- R/W. Default is 0. 2 NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. Parallel ATA Disable (PAD) -- R/W. 1 0 0 = The PATA controller is enabled. (Default) 1 = The PATA controller is disabled and its PCI configuration space is not accessible. Reserved 7.1.57 CG--Clock Gating (Mobile/Ultra Mobile Only) Offset Address: 341C-341Fh Default Value: 00000000h Bit 31 Attribute: Size: Description R/W, RO 32-bit Legacy (LPC) Dynamic Clock Gate Enable -- R/W. 0 = Legacy Dynamic Clock Gating is Disabled 1 = Legacy Dynamic Clock Gating is Enabled PATA Dynamic Clock Gate Enable -- R/W. 30 0 = PATA Dynamic Clock Gating is Disabled 1 = PATA Dynamic Clock Gating is Enabled USB UHCI Dynamic Clock Gate Enable -- R/W. 29:28 0 = USB UHCI Dynamic Clock Gating is Disabled 1 = USB UHCI Dynamic Clock Gating is Enabled 0 = Reserved 1 = Reserved SATA Port 3 Dynamic Clock Gate Enable -- R/W. 27 0 = SATA Port 3 Dynamic Clock Gating is Disabled 1 = SATA Port 3 Dynamic Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. SATA Port 2 Dynamic Clock Gate Enable -- R/W. 26 0 = SATA Port 2 Dynamic Clock Gating is Disabled 1 = SATA Port 2 Dynamic Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. SATA Port 1 Dynamic Clock Gate Enable -- R/W. 25 0 = SATA Port 1 Dynamic Clock Gating is Disabled 1 = SATA Port 1 Dynamic Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. SATA Port 0 Dynamic Clock Gate Enable -- R/W. 24 0 = SATA Port 0 Dynamic Clock Gating is Disabled 1 = SATA Port 0 Dynamic Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. Intel (R) ICH7 Family Datasheet 301 Chipset Configuration Registers Bit Description AC `97 Static Clock Gate Enable -- R/W. 0 = AC `97 Static Clock Gating is Disabled 1 = AC `97 Static Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. 23 27:23 22 Reserved High Definition Audio Dynamic Clock Gate Enable -- R/W. 0 = HIgh Definition Audio Dynamic Clock Gating is Disabled 1 = HIgh Definition Audio Dynamic Clock Gating is Enabled High Definition Audio Static Clock Gate Enable -- R/W. 0 = HIgh Definition Audio Static Clock Gating is Disabled 1 = HIgh Definition Audio Static Clock Gating is Enabled USB EHCI Static Clock Gate Enable -- R/W. 0 = USB EHCI Static Clock Gating is Disabled 1 = USB EHCI Static Clock Gating is Enabled USB EHCI Dynamic Clock Gate Enable -- R/W. 0 = USB EHCI Dynamic Clock Gating is Disabled 1 = USB EHCI Dynamic Clock Gating is Enabled Reserved PCI Dynamic Gate Enable -- R/W. Funcitonality reserved. BIOS must ensure bit is 0. Reserved DMI and PCI Express* RX Dynamic Clock Gate Enable -- R/W. 0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled 1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled PCI Express TX Dynamic Clock Gate Enable -- R/W. 0 = PCI Express root port TX Dynamic Clock Gating is Disabled 1 = PCI Express root port TX Dynamic Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. DMI TX Dynamic Clock Gate Enable -- R/W. 21 20 19 18:17 16 15:4 3 2 1 0 = DMI TX Dynamic Clock Gating is Disabled 1 = DMI TX Dynamic Clock Gating is Enabled PCI Express Root Port Static Clock Gate Enable -- R/W. 0 = PCI Express root port Static Clock Gating is Disabled 1 = PCI Express root port Static Clock Gating is Enabled NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0. 0 302 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) LAN is not supported on ICH7-U Ultra Mobile. The ICH7 integrated LAN controller appears to reside at PCI Device 8, Function 0 on the secondary side of the ICH7's virtual PCI-to-PCI bridge. This is typically Bus 1, but may be assigned a different number depending upon system configuration. The LAN controller acts as both a master and a slave on the PCI bus. As a master, the LAN controller interacts with the system main memory to access data for transmission or deposit received data. As a slave, some of the LAN controller's control structures are accessed by the host processor to read or write information to the on-chip registers. The processor also provides the LAN controller with the necessary commands and pointers that allow it to process receive and transmit data. Note: 8.1 Note: . PCI Configuration Registers (LAN Controller--B1:D8:F0) Address locations that are not shown should be treated as Reserved (See Section 6.2 for details). LAN Controller PCI Register Address Map (LAN Controller--B1:D8:F0) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 10h-13h 14h-17h 2Ch-2Dh 2Eh-2Fh 34h 3Ch 3Dh 3Eh Mnemonic VID DID PCICMD PCISTS RID SCC BCC CLS PMLT HEADTYP CSR_MEM_BASE CSR_IO_BASE SVID SID CAP_PTR INT_LN INT_PN MIN_GNT Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Sub Class Code Base Class Code Cache Line Size Primary Master Latency Timer Header Type CSR Memory-Mapped Base Address CSR I/O-Mapped Base Address Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin Minimum Grant Default 8086h See register description. 0000h 0290h See register description. 00h 02 00h 00h 00h 00000008h 00000001h 0000h 0000h DCh 00h 01h 08h Type RO RO RO, R/W RO, R/WC RO RO RO R/W R/W RO R/W, RO R/W, RO RO RO RO R/W RO RO Table 8-1. Intel (R) ICH7 Family Datasheet 303 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Table 8-1. LAN Controller PCI Register Address Map (LAN Controller--B1:D8:F0) (Sheet 2 of 2) Offset 3Fh DCh DDh DEh-DFh Mnemonic MAX_LAT CAP_ID NXT_PTR PM_CAP Register Name Maximum Latency Capability ID Next Item Pointer Power Management Capabilities Power Management Control/ Status PCI Power Management Data Default 38h 01h 00h FE21h (Desktop Only) 7E21h (Mobile Only) 0000h 00h Type RO RO RO RO R/W, RO, R/WC RO E0h-E1h E3 PMCSR PCIDATA 8.1.1 VID--Vendor Identification Register (LAN Controller--B1:D8:F0) Offset Address: 00h-01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel. 8.1.2 DID--Device Identification Register (LAN Controller--B1:D8:F0) Offset Address: 02h-03h Default Value: See bit description Bit Attribute: Size: Description RO 16 bits 15:0 Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 integrated LAN controller. NOTES: 1. If the EEPROM is not present (or not properly programmed), reads to the Device ID return the default value referred to in the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update. 2. If the EEPROM is present (and properly programmed) and if the value of word 23h is not 0000h or FFFFh, the Device ID is loaded from the EEPROM, word 23h after the hardware reset. (See Section 8.1.14 - SID, Subsystem ID of LAN controller for detail) 304 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.3 PCICMD--PCI Command Register (LAN Controller--B1:D8:F0) Offset Address: 04h-05h Default Value: 0000h Bit 15:11 10 Reserved Interrupt Disable -- R/W. 0 = Enable. 1 = Disables LAN controller to assert its INTA signal. Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. The integrated LAN controller will not run fast back-to-back PCI cycles. SERR# Enable (SERR_EN) -- R/W. 8 7 0 = Disable. 1 = Enable. Allow SERR# to be asserted. Wait Cycle Control (WCC) -- RO. Hardwired to 0. Not implemented. Parity Error Response (PER) -- R/W. 6 0 = The LAN controller will ignore PCI parity errors. 1 = The integrated LAN controller will take normal action when a PCI parity error is detected and will enable generation of parity on DMI. VGA Palette Snoop (VPS) -- RO. Hardwired to 0. Not Implemented. Memory Write and Invalidate Enable (MWIE) -- R/W. 4 0 = Disable. The LAN controller will not use the Memory Write and Invalidate command. 1 = Enable. Special Cycle Enable (SCE) -- RO. Hardwired to 0. The LAN controller ignores special cycles. Bus Master Enable (BME) -- R/W. 2 0 = Disable. 1 = Enable. The Intel(R) ICH7's integrated LAN controller may function as a PCI bus master. Memory Space Enable (MSE) -- R/W. 1 0 = Disable. 1 = Enable. The ICH7's integrated LAN controller will respond to the memory space accesses. I/O Space Enable (IOSE) -- R/W. 0 0 = Disable. 1 = Enable. The ICH7's integrated LAN controller will respond to the I/O space accesses. Attribute: Size: Description RO, R/W 16 bits 9 5 3 Intel (R) ICH7 Family Datasheet 305 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.4 PCISTS--PCI Status Register (LAN Controller--B1:D8:F0) Offset Address: 06h-07h Default Value: 0290h Attribute: Size: RO, R/WC 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) -- R/WC. 15 0 = Parity error Not detected. 1 = The Intel(R) ICH7's integrated LAN controller has detected a parity error on the PCI bus (will be set even if Parity Error Response is disabled in the PCI Command register). Signaled System Error (SSE) -- R/WC. 14 0 = Integrated LAN controller has not asserted SERR# 1 = The ICH7's integrated LAN controller has asserted SERR#. SERR# can be routed to cause NMI, SMI#, or interrupt. Master Abort Status (RMA) -- R/WC. 13 0 = Master Abort not generated 1 = The ICH7's integrated LAN controller (as a PCI master) has generated a master abort. Received Target Abort (RTA) -- R/WC. 12 0 = Target abort not received. 1 = The ICH7's integrated LAN controller (as a PCI master) has received a target abort. Signaled Target Abort (STA) -- RO. Hardwired to 0. The device will not signal Target Abort. DEVSEL# Timing Status (DEV_STS) -- RO. 01h = Medium timing. Data Parity Error Detected (DPED) -- R/WC. 0 = Parity error not detected (conditions below are not met). 1 = All of the following three conditions have been met: 1. The LAN controller is acting as bus master 2. The LAN controller has asserted PERR# (for reads) or detected PERR# asserted (for writes) 3. The Parity Error Response bit in the LAN controller's PCI Command Register is set. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. The device can accept fast back-to-back transactions. User Definable Features (UDF) -- RO. Hardwired to 0. Not implemented. 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. The device does not support 66 MHz PCI. Capabilities List (CAP_LIST) -- RO. 4 0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power Management. 1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management. Interrupt Status (INTS) -- RO. This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the command register. Reserved 11 10:9 8 7 6 5 3 2:0 306 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.5 RID--Revision Identification Register (LAN Controller--B1:D8:F0) Offset Address: 08h Default Value: See bit description Bit Attribute: Size: Description RO 8 bits 7:0 Revision ID (RID) -- RO. This field is an 8-bit value that indicates the revision number for the integrated LAN controller. The three least significant bits in this register may be overridden by the ID and REV ID fields in the EEPROM. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. 8.1.6 SCC--Sub Class Code Register (LAN Controller--B1:D8:F0) Offset Address: 0Ah Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Sub Class Code (SCC) -- RO. This 8-bit value specifies the sub-class of the device as an Ethernet controller. 8.1.7 BCC--Base-Class Code Register (LAN Controller--B1:D8:F0) Offset Address: 0Bh Default Value: 02h Bit 7:0 Attribute: Size: Description RO 8 bits Base Class Code (BCC) -- RO. This 8-bit value specifies the base class of the device as a network controller. Intel (R) ICH7 Family Datasheet 307 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.8 CLS--Cache Line Size Register (LAN Controller--B1:D8:F0) Offset Address: 0Ch Default Value: 00h Bit 7:5 Reserved Cache Line Size (CLS) -- R/W. 00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN controller. 4:3 01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is written to this register). 10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h is written to this register). 11 = Invalid. MWI command will not be used. 2:0 Reserved Attribute: Size: Description R/W 8 bits 8.1.9 PMLT--Primary Master Latency Timer Register (LAN Controller--B1:D8:F0) Offset Address: 0Dh Default Value: 00h Bit 7:3 2:0 Attribute: Size: Description R/W 8 bits Master Latency Timer Count (MLTC) -- R/W. This field defines the number of PCI clock cycles that the integrated LAN controller may own the bus while acting as bus master. Reserved 8.1.10 HEADTYP--Header Type Register (LAN Controller--B1:D8:F0) Offset Address: 0Eh Default Value: 00h Bit 7 6:0 Attribute: Size: Description RO 8 bits Multi-Function Device (MFD) -- RO. Hardwired to 0 to indicate a single function device. Header Type (HTYPE) -- RO. This 7-bit field identifies the header layout of the configuration space as an Ethernet controller. 308 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.11 CSR_MEM_BASE -- CSR Memory-Mapped Base Address Register (LAN Controller--B1:D8:F0) Offset Address: 10h-13h Default Value: 00000008h Attribute: Size: R/W, RO 32 bits Note: The ICH7's integrated LAN controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the LAN controller's CSR registers. Bit 31:12 11:4 3 2:1 0 Description Base Address (MEM_ADDR) -- R/W. This field contains the upper 20 bits of the base address provides 4 KB of memory-Mapped space for the LAN controller's Control/Status registers. Reserved Prefetchable (MEM_PF) -- RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-Mapped address range. Type (MEM_TYPE) -- RO. Hardwired to 00b to indicate the memory-Mapped address range may be located anywhere in 32-bit address space. Memory-Space Indicator (MEM_SPACE) -- RO. Hardwired to 0 to indicate that this base address maps to memory space. 8.1.12 CSR_IO_BASE -- CSR I/O-Mapped Base Address Register (LAN Controller--B1:D8:F0) Offset Address: 14h-17h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits Note: The ICH7's integrated LAN controller requires one BAR for memory mapping. Software determines which BAR (memory or I/O) is used to access the LAN controller's CSR registers. Bit 31:16 15:6 5:1 0 Reserved Base Address (IO_ADDR)-- R/W. This field provides 64 bytes of I/O-Mapped address space for the LAN controller's Control/Status registers. Reserved I/O Space Indicator (IO_SPACE) -- RO. Hardwired to 1 to indicate that this base address maps to I/O space. Description 8.1.13 SVID -- Subsystem Vendor Identification (LAN Controller--B1:D8:F0) Offset Address: 2Ch-2D Default Value: 0000h Bit 15:0 Attribute: Size: Description RO 16 bits Subsystem Vendor ID (SVID) -- RO. See Section 8.1.14 for details. Intel (R) ICH7 Family Datasheet 309 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.14 SID -- Subsystem Identification (LAN Controller--B1:D8:F0) Offset Address: 2Eh-2Fh Default Value: 0000h Bit 15:0 Subsystem ID (SID) -- RO. Attribute: Size: Description RO 16 bits Note: The ICH7's integrated LAN controller provides support for configurable Subsystem ID and Subsystem Vendor ID fields. After reset, the LAN controller automatically reads addresses Ah through Ch, and 23h of the EEPROM. The LAN controller checks bits 15:13 in the EEPROM word Ah, and functions according to Table 8-2. Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM Bits 15:14 11b, 10b, 00b 01b 01b Bit 13 X 0b 1b Device ID1 1051h Word 23h Word 23h Vendor ID 8086h 8086h Word Ch Revision ID2 00h 00h 80h + Word Ah, bits 10:8 Subsystem ID 0000h Word Bh Word Bh Subsystem Vendor ID 0000h Word Ch Word Ch Table 8-2. NOTES: 1. The Device ID is loaded from Word 23h only if the value of Word 23h is not 0000h or FFFFh 2. The Revision ID is subject to change according to the silicon stepping. 8.1.15 CAP_PTR -- Capabilities Pointer (LAN Controller--B1:D8:F0) Offset Address: 34h Default Value: DCh Bit 7:0 Attribute: Size: Description RO 8 bits Capabilities Pointer (CAP_PTR) -- RO. Hardwired to DCh to indicate the offset within configuration space for the location of the Power Management registers. 8.1.16 INT_LN -- Interrupt Line Register (LAN Controller--B1:D8:F0) Offset Address: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- R/W. This field identifies the system interrupt line to which the LAN controller's PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed. 310 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.17 INT_PN -- Interrupt Pin Register (LAN Controller--B1:D8:F0) Offset Address: 3Dh Default Value: 01h Bit Attribute: Size: Description RO 8 bits 7:0 Interrupt Pin (INT_PN) -- RO. Hardwired to 01h to indicate that the LAN controller's interrupt request is connected to PIRQA#. However, in the Intel(R) ICH7 implementation, when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though PIRQE# will still go active internally). 8.1.18 MIN_GNT -- Minimum Grant Register (LAN Controller--B1:D8:F0) Offset Address: 3Eh Default Value: 08h Bit 7:0 Attribute: Size: Description RO 8 bits Minimum Grant (MIN_GNT) -- RO. This field indicates the amount of time (in increments of 0.25 s) that the LAN controller needs to retain ownership of the PCI bus when it initiates a transaction. 8.1.19 MAX_LAT -- Maximum Latency Register (LAN Controller--B1:D8:F0) Offset Address: 3Fh Default Value: 38h Bit 7:0 Attribute: Size: Description RO 8 bits Maximum Latency (MAX_LAT) -- RO. This field defines how often (in increments of 0.25 s) the LAN controller needs to access the PCI bus. 8.1.20 CAP_ID -- Capability Identification Register (LAN Controller--B1:D8:F0) Offset Address: DCh Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Capability ID (CAP_ID) -- RO. Hardwired to 01h to indicate that the Intel(R) ICH7's integrated LAN controller supports PCI power management. Intel (R) ICH7 Family Datasheet 311 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.21 NXT_PTR -- Next Item Pointer (LAN Controller--B1:D8:F0) Offset Address: DDh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Next Item Pointer (NXT_PTR) -- RO. Hardwired to 00b to indicate that power management is the last item in the capabilities list. 8.1.22 PM_CAP -- Power Management Capabilities (LAN Controller--B1:D8:F0) Offset Address: DEh-DFh Default Value: FE21h (Desktop Only) 7E21h (Mobile Only) Bit 15:11 Attribute: Size: RO 16 bits Description PME Support (PME_SUP) -- RO. Hardwired to 11111b. This 5-bit field indicates the power states in which the LAN controller may assert PME#. The LAN controller supports wake-up in all power states. D2 Support (D2_SUP) -- RO. Hardwired to 1 to indicate that the LAN controller supports the D2 power state. D1 Support (D1_SUP) -- RO. Hardwired to 1 to indicate that the LAN controller supports the D1 power state. Auxiliary Current (AUX_CUR) -- RO. Hardwired to 000b to indicate that the LAN controller implements the Data registers. The auxiliary power consumption is the same as the current consumption reported in the D3 state in the Data register. Device Specific Initialization (DSI) -- RO. Hardwired to 1 to indicate that special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. DSI is required for the LAN controller after D3-to-D0 reset. Reserved PME Clock (PME_CLK) -- RO. Hardwired to 0 to indicate that the LAN controller does not require a clock to generate a power management event. Version (VER) -- RO. Hardwired to 010b to indicate that the LAN controller complies with of the PCI Power Management Specification, Revision 1.1. 10 9 8:6 5 4 3 2:0 312 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.23 PMCSR -- Power Management Control/ Status Register (LAN Controller--B1:D8:F0) Offset Address: E0h-E1h Default Value: 0000h Bit PME Status (PME_STAT) -- R/WC. 15 0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and clears the PME status bit in the Power Management Driver Register. When the PME# signal is enabled, the PME# signal reflects the state of the PME status bit. 1 = Set upon occurrence of a wake-up event, independent of the state of the PME enable bit. Data Scale (DSCALE) -- RO. This field indicates the data register scaling factor. It equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as selected by the "Data Select" field. Data Select (DSEL) -- R/W. This field is used to select which data is reported through the Data register and Data Scale field. PME Enable (PME_EN) -- R/W. This bit enables the Intel(R) ICH7's integrated LAN controller to assert PME#. 0 = The device will not assert PME#. 1 = Enable PME# assertion when PME Status is set. Reserved Dynamic Data (DYN_DAT) -- RO. Hardwired to 0 to indicate that the device does not support the ability to monitor the power consumption dynamically. Reserved Power State (PWR_ST) -- R/W. This 2-bit field is used to determine the current power state of the integrated LAN controller, and to put it into a new power state. The definition of the field values is as follows: 1:0 00 = D0 01 = D1 10 = D2 11 = D3 Attribute: Size: Description RO, R/W, R/WC 16 bits 14:13 12:9 8 7:5 4 3:2 Intel (R) ICH7 Family Datasheet 313 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.1.24 PCIDATA -- PCI Power Management Data Register (LAN Controller--B1:D8:F0) Offset Address: E3h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Power Management Data (PWR_MGT) -- RO. State dependent power consumption and heat dissipation data. The data register is an 8-bit read only register that provides a mechanism for the ICH7's integrated LAN controller to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 W to 2.55 W with 0.01 W resolution, scaled according to the Data Scale field in the PMCSR. The structure of the Data Register is given in Table 8-3. Table 8-3. Data Register Structure Data Select 0 1 2 3 4 5 6 7 8 9-15 Data Scale 2 2 2 2 2 2 2 2 2 0 Data Reported D0 Power Consumption D1 Power Consumption D2 Power Consumption D3 Power Consumption D0 Power Dissipated D1 Power Dissipated D2 Power Dissipated D3 Power Dissipated Common Function Power Dissipated Reserved 314 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2 LAN Control / Status Registers (CSR) (LAN Controller--B1:D8:F0) Intel(R) ICH7 Integrated LAN Controller CSR Space Register Address Map Offset 00h-01h 02h-03h 04h-07h 08h-0Bh 0Ch- 0Dh 0Eh 0Fh 10h-13h 14h-17h 18h 19-1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h-3Ch Mnemonic SCB_STA SCB_CMD SCB_GENPNT Port -- EEPROM_CNTL -- MDI_CNTL REC_DMA_BC EREC_INTR FLOW_CNTL PMDR GENCNTL GENSTA -- SMB_PCI -- Register Name System Control Block Status Word System Control Block Command Word System Control Block General Pointer PORT Interface Reserved EEPROM Control Reserved Management Data Interface Control Receive DMA Byte Count Early Receive Interrupt Flow Control Power Management Driver General Control General Status Reserved SMB via PCI Reserved Default 0000h 0000h 0000 0000h 0000 0000h -- 00 -- 0000 0000h 0000 0000h 00h 0000h 00h 00h 00h -- 27h -- Type R/WC, RO R/W, WO R/W R/W (special) -- R/W, RO, WO -- R/W (special) RO R/W RO, R/W (special) R/WC R/W RO -- R/W -- Table 8-4. Intel (R) ICH7 Family Datasheet 315 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.1 SCB_STA--System Control Block Status Word Register (LAN Controller--B1:D8:F0) Offset Address: 00h-01h Default Value: 0000h Attribute: Size: R/WC, RO 16 bits The ICH7's integrated LAN controller places the status of its Command Unit (CU) and Receive Unit (RC) and interrupt indications in this register for the processor to read. Bit Description Command Unit (CU) Executed (CX) -- R/WC. 15 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set. Frame Received (FR) -- R/WC. 14 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame. CU Not Active (CNA) -- R/WC. 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU leaves the Active state and enters either the Idle or the Suspended state. When configured to generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state. Receive Not Ready (RNR) -- R/WC. 12 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame Descriptor. Management Data Interrupt (MDI) -- R/WC. 11 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Set when a Management Data Interface read or write cycle has completed. The management data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data Interface Control register in the CSR). Software Interrupt (SWI) -- R/WC. 10 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Set when software generates an interrupt. Early Receive (ER) -- R/WC. 9 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Indicates the occurrence of an Early Receive Interrupt. Flow Control Pause (FCP) -- R/WC. 8 0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = Indicates Flow Control Pause interrupt. 13 316 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit 00 01 10 11 = = = = Description Command Unit Status (CUS) -- RO. Idle Suspended LPQ (Low Priority Queue) active HPQ (High Priority Queue) active 7:6 Receive Unit Status (RUS) -- RO. Value 0000b 0001b 5:2 0010b 0011b 0100b 0101b 0110b 0111b 1:0 Reserved Status Idle Suspended No Resources Reserved Ready Reserved Reserved Reserved Value 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Status Reserved Suspended with no more RBDs No resources due to no more RBDs Reserved Ready with no RBDs present Reserved Reserved Reserved 8.2.2 SCB_CMD--System Control Block Command Word Register (LAN Controller--B1:D8:F0) Offset Address: 02h-03h Default Value: 0000h Attribute: Size: R/W, WO 16 bits The processor places commands for the Command and Receive units in this register. Interrupts are also acknowledged in this register. Bit CX Mask (CX_MSK) -- R/W. 15 0 = Interrupt not masked. 1 = Disable the generation of a CX interrupt. FR Mask (FR_MSK) -- R/W. 14 0 = Interrupt not masked. 1 = Disable the generation of an FR interrupt. CNA Mask (CNA_MSK) -- R/W. 13 0 = Interrupt not masked. 1 = Disable the generation of a CNA interrupt. RNR Mask (RNR_MSK) -- R/W. 12 0 = Interrupt not masked. 1 = Disable the generation of an RNR interrupt. ER Mask (ER_MSK) -- R/W. 11 0 = Interrupt not masked. 1 = Disable the generation of an ER interrupt. FCP Mask (FCP_MSK) -- R/W. 10 0 = Interrupt not masked. 1 = Disable the generation of an FCP interrupt. Description Intel (R) ICH7 Family Datasheet 317 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit 9 Description Software Generated Interrupt (SI) -- WO. 0 = No Effect. 1 = Setting this bit causes the LAN controller to generate an interrupt. Interrupt Mask (IM) -- R/W. This bit enables or disables the LAN controller's assertion of the INTA# signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit. 0 = Enable the assertion of INTA#. 1 = Disable the assertion of INTA#. Command Unit Command (CUC) -- R/W. Valid values are listed below. All other values are Reserved. 0000 = NOP: Does not affect the current state of the unit. 0001 = CU Start: Start execution of the first command on the CBL. A pointer to the first CB of the CBL should be placed in the SCB General Pointer before issuing this command. The CU Start command should only be issued when the CU is in the Idle or Suspended states (not when the CU is in the active state), and all of the previously issued Command Blocks have been processed and completed by the CU. Sometimes it is only possible to determine that all Command Blocks are completed by checking that the Complete bit is set in all previously issued Command Blocks. 0010 = CU Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. 0011 = CU HPQ Start: Start execution of the first command on the high priority CBL. A pointer to the first CB of the HPQ CBL should be placed in the SCB General POinter before issuing this command. 8 7:4 0100 = Load Dump Counters Address: Indicates to the device where to write dump data when using the Dump Statistical Counters or Dump and Reset Statistical Counters commands. This command must be executed at least once before any usage of the Dump Statistical Counters or Dump and Reset Statistical Counters commands. The address of the dump area must be placed in the General Pointer register. 0101 = Dump Statistical Counters: Tells the device to dump its statistical counters to the area designated by the Load Dump Counters Address command. 0110 = Load CU Base: The device's internal CU Base Register is loaded with the value in the CSB General Pointer. 0111 = Dump and Reset Statistical Counters: Indicates to the device to dump its statistical counters to the area designated by the Load Dump Counters Address command, and then to clear these counters. 1010 = CU Static Resume: Resume operation of the Command unit by executing the next command. This command will be ignored if the CU is idle. This command should be used only when the CU is in the Suspended state and has no pending CU Resume commands. 1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL. this command will be ignored if the HPQ was not started. 3 Reserved 318 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit Description Receive Unit Command (RUC) -- R/W. Valid values are: 000 = NOP: Does not affect the current state of the unit. 001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in the SCB General POinter before using this command. The device pre-fetches the first RFD and the first RBD (if in flexible mode) in preparation to receive incoming frames that pass its address filtering. 010 = RU Resume: Resume frame reception (only when in suspended state). 011 = RCV DMA Redirect: Resume the RCV DMA when configured to "Direct DMA Mode." The buffers are indicated by an RBD chain which is pointed to by an offset stored in the General Pointer Register (this offset will be added to the RU Base). 2:0 100 = RU Abort: Abort RU receive operation immediately. 101 = Load Header Data Size (HDS): This value defines the size of the Header portion of the RFDs or Receive buffers. The HDS value is defined by the lower 14 bits of the SCB General Pointer, so bits 31:15 should always be set to 0's when using this command. Once a Load HDS command is issued, the device expects only to find Header RFDs, or be used in "RCV Direct DMA mode" until it is reset. Note that the value of HDS should be an even, non-zero number. 110 = Load RU Base: The device's internal RU Base Register is loaded with the value in the SCB General Pointer. 111 = RBD Resume: Resume frame reception into the RFA. This command should only be used when the RU is already in the "No Resources due to no RBDs" state or the "Suspended with no more RBDs" state. 8.2.3 SCB_GENPNT--System Control Block General Pointer Register (LAN Controller--B1:D8:F0) Offset Address: 04h-07h Default Value: 0000 0000h Bit 15:0 Attribute: Size: Description R/W 32 bits SCB General Pointer -- R/W. The SCB General Pointer register is programmed by software to point to various data structures in main memory depending on the current SCB Command word. 8.2.4 PORT--PORT Interface Register (LAN Controller--B1:D8:F0) Offset Address: 08h-0Bh Default Value: 0000 0000h Attribute: Size: R/W (special) 32 bits The PORT interface allows the processor to reset the ICH7's internal LAN controller, or perform an internal self test. The PORT DWord may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only accept the command after the high byte (offset 0Bh) is written; therefore, the high byte must be written last. Intel (R) ICH7 Family Datasheet 319 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit 31:4 Description Pointer Field (PORT_PTR) -- R/W (special). A 16-byte aligned address must be written to this field when issuing a Self-Test command to the PORT interface.The results of the Self Test will be written to the address specified by this field. PORT Function Selection (PORT_FUNC) -- R/W (special). Valid values are listed below. All other values are reserved. 0000 = PORT Software Reset: Completely resets the LAN controller (all CSR and PCI registers). This command should not be used when the device is active. If a PORT Software Reset is desired, software should do a Selective Reset (described below), wait for the PORT register to be cleared (completion of the Selective Reset), and then issue the PORT Software Reset command. Software should wait approximately 10 s after issuing this command before attempting to access the LAN controller's registers again. 3:0 0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed by a general internal self-test of the LAN controller. The results of the self-test are written to memory at the address specified in the Pointer field of this register. The format of the self-test result is shown in Table 8-5. After completing the self-test and writing the results to memory, the LAN controller will execute a full internal reset and will re-initialize to the default configuration. Self-Test does not generate an interrupt of similar indicator to the host processor upon completion. 0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise maintains the current configuration parameters (RU and CU Base, HDSSize, Error Counters, Configure information and Individual/Multicast Addresses are preserved). Software should wait approximately 10 s after issuing this command before attempting to access the LAN controller's registers again. Table 8-5. Self-Test Results Format Bit 31:13 12 11:6 Reserved General Self-Test Result (SELF_TST) -- R/W (special). 0 = Pass 1 = Fail Reserved Diagnose Result (DIAG_RSLT) -- R/W (special). This bit provides the result of an internal diagnostic test of the Serial Subsystem. 0 = Pass 1 = Fail Reserved Register Result (REG_RSLT) -- R/W (special). This bit provides the result of a test of the internal Parallel Subsystem registers. 0 = Pass 1 = Fail ROM Content Result (ROM_RSLT) -- R/W (special). This bit provides the result of a test of the internal microcode ROM. 0 = Pass 1 = Fail Reserved Description 5 4 3 2 1:0 320 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.5 EEPROM_CNTL--EEPROM Control Register (LAN Controller--B1:D8:F0) Offset Address: 0Eh Default Value: 00h Attribute: Size: RO, R/W, WO 8 bits The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external EEPROM. Bit 7:4 3 Reserved EEPROM Serial Data Out (EEDO) -- RO. Note that this bit represents "Data Out" from the perspective of the EEPROM device. This bit contains the value read from the EEPROM when performing read operations. EEPROM Serial Data In (EEDI) -- WO. Note that this bit represents "Data In" from the perspective of the EEPROM device. The value of this bit is written to the EEPROM when performing write operations. EEPROM Chip Select (EECS) -- R/W. 1 0 = Drives the Intel(R) ICH7's EE_CS signal low to disable the EEPROM. this bit must be set to 0 for a minimum of 1 s between consecutive instruction cycles. 1 = Drives the ICH7's EE_CS signal high, to enable the EEPROM. EEPROM Serial Clock (EESK) -- R/W. Toggling this bit clocks data into or out of the EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM component's minimum clock frequency specification. 0 = Drives the ICH7's EE_SHCLK signal low. 1 = Drives the ICH7's EE_SHCLK signal high. Description 2 0 Intel (R) ICH7 Family Datasheet 321 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.6 MDI_CNTL--Management Data Interface (MDI) Control Register (LAN Controller--B1:D8:F0) Offset Address: 10h-13h Default Value: 0000 0000h Attribute: Size: R/W (special) 32 bits The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and write bits from the LAN Connect component. This register may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only accept the command after the high byte (offset 13h) is written; therefore, the high byte must be written last. Bit 31:30 Description These bits are reserved and should be set to 00b. Interrupt Enable -- R/W (special). 29 0 = Disable. 1 = Enables the LAN controller to assert an interrupt to indicate the end of an MDI cycle. Ready -- R/W (special). 28 0 = Expected to be reset by software at the same time the command is written. 1 = Set by the LAN controller at the end of an MDI transaction. Opcode -- R/W (special). These bits define the opcode: 00 = Reserved 27:26 01 = MDI write 10 = MDI read 11 = Reserved 25:21 20:16 LAN Connect Address -- R/W (special). This field of bits contains the LAN Connect address. LAN Connect Register Address -- R/W (special). This field contains the LAN Connect Register Address. Data -- R/W (special). In a write command, software places the data bits in this field, and the LAN controller transfers the data to the external LAN Connect component. During a read command, the LAN controller reads these bits serially from the LAN Connect, and software reads the data from this location. 15:0 8.2.7 REC_DMA_BC--Receive DMA Byte Count Register (LAN Controller--B1:D8:F0) Offset Address: 14h-17h Default Value: 0000 0000h Bit 31:0 Attribute: Size: Description RO 32 bits Receive DMA Byte Count -- RO. This field keeps track of how many bytes of receive data have been passed into host memory via DMA. 322 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.8 EREC_INTR--Early Receive Interrupt Register (LAN Controller--B1:D8:F0) Offset Address: 18h Default Value: 00h Attribute: Size: R/W 8 bits The Early Receive Interrupt register allows the internal LAN controller to generate an early interrupt depending on the length of the frame. The LAN controller will generate an interrupt at the end of the frame regardless of whether or not Early Receive Interrupts are enabled. Note: It is recommended that software not use this register unless receive interrupt latency is a critical performance issue in that particular software environment. Using this feature may reduce receive interrupt latency, but will also result in the generation of more interrupts, which can degrade system efficiency and performance in some environments. Bit Description Early Receive Count -- R/W. When some non-zero value x is programmed into this register, the LAN controller will set the ER bit in the SCB Status Word Register and assert INTA# when the byte count indicates that there are x qwords remaining to be received in the current frame (based on the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value of 00h (the default value) is programmed into this register. 7:0 8.2.9 FLOW_CNTL--Flow Control Register (LAN Controller--B1:D8:F0) Offset Address: 19h-1Ah Default Value: 0000h Bit 15:13 Reserved FC Paused Low -- RO. 12 0 = Cleared when the FC timer reaches 0, or a Pause frame is received. 1 = Set when the LAN controller receives a Pause Low command with a value greater than 0. FC Paused -- RO. 11 0 = Cleared when the FC timer reaches 0. 1 = Set when the LAN controller receives a Pause command regardless of its cause (FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its Flow Control Pause bit set, or software writing a 1 to the Xoff bit). FC Full -- RO. 10 0 = Cleared when the FC timer reaches 0. 1 = Set when the LAN controller sends a Pause command with a value greater than 0. Xoff -- R/W (special). This bit should only be used if the LAN controller is configured to operate with IEEE frame-based flow control. 9 0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register). 1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff request due to an "RFD Xoff" bit. Attribute: Size: Description RO, R/W (special) 16 bits Intel (R) ICH7 Family Datasheet 323 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit Description Xon -- WO. This bit should only be used if the LAN controller is configured to operate with IEEE frame-based flow control. 8 0 = This bit always returns 0 on reads. 1 = Writing a 1 to this bit resets the Xoff request to the LAN controller, clearing bit 9 in this register. Reserved Flow Control Threshold -- R/W. The LAN controller can generate a Flow Control Pause frame when its Receive FIFO is almost full. The value programmed into this field determines the number of bytes still available in the Receive FIFO when the Pause frame is generated. Bits 2:0 000b 001b 010b 011b 100b 101b 110b 111b Free Bytes in RX FIFO 0.50 KB 1.00 KB 1.25 KB 1.50 KB 1.75 KB 2.00 KB 2.25 KB 2.50 KB Slow system Comment Fast system (recommended default) 7:3 2:0 8.2.10 PMDR--Power Management Driver Register (LAN Controller--B1:D8:F0) Offset Address: 1Bh Default Value: 00h Attribute: Size: R/WC 8 bits The ICH7's internal LAN controller provides an indication in the PMDR that a wake-up event has occurred. Bit 7 Description Link Status Change Indication -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The link status change bit is set following a change in link status. Magic Packet -- R/WC. 6 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wakeup disable bit in the configuration command and the PME Enable bit in the Power Management Control/ Status Register. Interesting Packet -- R/WC. 5 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when an "interesting" packet is received. Interesting packets are defined by the LAN controller packet filters. Reserved 4:3 324 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Bit 2 1 Description ASF Enabled -- RO. This bit is set to 1 when the LAN controller is in ASF mode. TCO Request -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set to 1b when the LAN controller is busy with TCO activity. PME Status -- R/WC. This bit is a reflection of the PME Status bit in the Power Management Control/Status Register (PMCSR). 0 0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the PMCSR and deasserts the PME signal. 1 = Set upon a wake-up event, independent of the PME Enable bit. 8.2.11 GENCNTL--General Control Register (LAN Controller--B1:D8:F0) Offset Address: 1Ch Default Value: 00h Bit 7:4 Attribute: Size: Description R/W 8 bits Reserved. These bits should be set to 0000b. LAN Connect Software Reset -- R/W. 3 0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt to access the LAN Connect interface for at least 1ms after clearing this bit. 1 = Software can set this bit to force a reset condition on the LAN Connect interface. Reserved. This bit should be set to 0. Deep Power-Down on Link Down Enable 2 -- R/W. 1 0 = Disable 1 = Enable. The Intel(R) ICH7's internal LAN controller may enter a deep power-down state (sub-3 mA) in the D2 and D3 power states while the link is down. In this state, the LAN controller does not keep link integrity. This state is not supported for point-to-point connection of two end stations. Reserved 0 Intel (R) ICH7 Family Datasheet 325 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.12 GENSTA--General Status Register (LAN Controller--B1:D8:F0) Offset Address: 1Dh Default Value: 00h Bit 7:3 2 Reserved Duplex Mode -- RO. This bit indicates the wire duplex mode. 0 = Half duplex 1 = Full duplex Speed -- RO. This bit indicates the wire speed. 1 0 = 10 Mb/s 1 = 100 Mb/s Link Status Indication -- RO. This bit indicates the status of the link. 0 0 = Invalid 1 = Valid Attribute: Size: Description RO 8 bits 8.2.13 SMB_PCI--SMB via PCI Register (LAN Controller--B1:D8:F0) Offset Address: 1Fh Default Value: 27h Attribute: Size: R/W, RO 8 bits Software asserts SREQ when it wants to isolate the PCI-accessible SMBus to the ASF registers/commands. It waits for SGNT to be asserted. At this point SCLI, SDAO, SCLO, and SDAI can be toggled/read to force ASF controller SMBus transactions without affecting the external SMBus. After all operations are completed, the bus is returned to idle (SCLO=1b,SDAO=1b, SCLI=1b, SDAI=1b), SREQ is released (written 0b). Then SGNT goes low to indicate released control of the bus. The logic in the ASF controller only asserts or deasserts SGNT at times when it determines that it is safe to switch (all SMBuses that are switched in/out are idle). When in isolation mode (SGNT=1), software can access the ICH7 SMBus slaves that allow configuration without affecting the external SMBus. This includes configuration register accesses and ASF command accesses. However, this capability is not available to the external TCO controller. When SGNT=0, the bit-banging and reads are reflected on the main SMBus and the PCISML_SDA0, PCISML_SCL0 read only bits. Bit 7:6 5 4 3 2 1 0 Reserved PCISML_SCLO PCISML_SGNT PCISML_SREQ PCISML_SDAO PCISML_SDAI PCISML_SCLI Description -- RO. SMBus Clock from the ASF controller. -- RO. SMBus Isolation Grant from the ASF controller. -- R/W. SMBus Isolation Request to the ASF controller. -- RO. SMBus Data from the ASF controller. -- R/W. SMBus Data to the ASF controller. -- R/W. SMBus Clock to the ASF controller. 326 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.2.14 Statistical Counters (LAN Controller--B1:D8:F0) The ICH7's integrated LAN controller provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the LAN controller when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field. Table 8-6. Statistical Counters (Sheet 1 of 2) ID Counter Description This counter contains the number of frames that were transmitted properly on the link. It is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the Transmit Command Block status. This counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. This counter contains the number of frames that were not transmitted since they encountered a collision later than the configured slot time. A transmit underrun occurs because the system bus cannot keep up with the transmission. This counter contains the number of frames that were either not transmitted or retransmitted due to a transmit DMA underrun. If the LAN controller is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. This counter contains the number of frames that were transmitted by the LAN controller despite the fact that it detected the de-assertion of CRS during the transmission. This counter contains the number of frames that were deferred before transmission due to activity on the link. This counter contains the number of transmitted frames that encountered one collision. This counter contains the number of transmitted frames that encountered more than one collision. This counter contains the total number of collisions that were encountered while attempting to transmit. This count includes late collisions and frames that encountered MAXCOL. This counter contains the number of frames that were received properly from the link. It is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. This counter contains the number of aligned frames discarded because of a CRC error. This counter is updated, if needed, regardless of the Receive Unit state. The Receive CRC Errors counter is mutually exclusive of the Receive Alignment Errors and Receive Short Frame Errors counters. 0 Transmit Good Frames Transmit Maximum Collisions (MAXCOL) Errors Transmit Late Collisions (LATECOL) Errors 4 8 12 Transmit Underrun Errors 16 20 24 28 32 Transmit Lost Carrier Sense (CRS) Transmit Deferred Transmit Single Collisions Transmit Multiple Collisions Transmit Total Collisions Receive Good Frames 36 40 Receive CRC Errors Intel (R) ICH7 Family Datasheet 327 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) Table 8-6. Statistical Counters (Sheet 2 of 2) ID Counter Description This counter contains the number of frames that are both misaligned (for example, CRS de-asserts on a non-octal boundary) and contain a CRC error. The counter is updated, if needed, regardless of the Receive Unit state. The Receive Alignment Errors counter is mutually exclusive of the Receive CRC Errors and Receive Short Frame Errors counters. This counter contains the number of good frames discarded due to unavailability of resources. Frames intended for a host whose Receive Unit is in the No Resources state fall into this category. If the LAN controller is configured to Save Bad Frames and the status of the received frame indicates that it is a bad frame, the Receive Resource Errors counter is not updated. This counter contains the number of frames known to be lost because the local system bus was not available. If the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. This counter contains the number of frames that encountered collisions during frame reception. This counter contains the number of received frames that are shorter than the minimum frame length. The Receive Short Frame Errors counter is mutually exclusive to the Receive Alignment Errors and Receive CRC Errors counters. A short frame will always increment only the Receive Short Frame Errors counter. This counter contains the number of Flow Control frames transmitted by the LAN controller. This count includes both the Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted. This counter contains the number of Flow Control frames received by the LAN controller. This count includes both the Xoff frames received and Xon (PAUSE(0)) frames received. This counter contains the number of MAC Control frames received by the LAN controller that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode. This counter contains the number of TCO packets received by the LAN controller. This counter contains the number of TCO packets transmitted. 44 Receive Alignment Errors 48 Receive Resource Errors 52 Receive Overrun Errors Receive Collision Detect (CDT) 56 60 Receive Short Frame Errors 64 Flow Control Transmit Pause Flow Control Receive Pause Flow Control Receive Unsupported Receive TCO Frames Transmit TCO Frames 68 72 76 78 The Statistical Counters are initially set to 0 by the ICH7's integrated LAN controller after reset. They cannot be preset to anything other than 0. The LAN controller increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the processor and PCI bus. In addition, the counters adhere to the following rules: * The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around to 0. * The LAN controller updates the required counters for each frame. It is possible for more than one counter to be updated as multiple errors can occur in a single frame. * The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1 standard. The LAN controller supports all mandatory and recommend 328 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) statistics functions through the status of the receive header and directly through these Statistical Counters. The processor can access the counters by issuing a Dump Statistical Counters SCB command. This provides a "snapshot", in main memory, of the internal LAN controller statistical counters. The LAN controller supports 21 counters. The dump could consist of the either 16, 19, or all 21 counters, depending on the status of the Extended Statistics Counters and TCO Statistics configuration bits in the Configuration command. 8.3 ASF Configuration Registers (LAN Controller--B1:D8:F0) The ASF registers in this table are accessible through the ICH7 SMBus slave interface. ASF Register Address Map Offset E0h E1h E2h E3h E4h E5h E6h-E7h E8h E9h EAh EBh ECh EDh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Mnemonic ASF_RID SMB_CNTL ASF_CNTL ASF_CNTL_EN ENABLE APM -- WTIM_CONF HEART_TIM RETRAN_INT RETRAN_PCL ASF_WTIM1 ASF_WTIM2 PET_SEQ1 PET_SEQ2 STA FOR_ACT RMCP_SNUM SP_MODE INPOLL_TCONF PHIST_CLR PMSK1 PMSK2 PMSK3 PMSK4 PMSK5 PMSK6 PMSK7 PMSK8 Register Name ASF Revision Identification SMBus Control ASF Control ASF Control Enable Enable APM Reserved Watchdog Timer Configuration Heartbeat Timer Retransmission Interval Retransmission Packet Count Limit ASF Watchdog Timer 1 ASF Watchdog Timer 2 PET Sequence 1 PET Sequence 2 Status Forced Actions RMCP Sequence Number Special Modes Inter-Poll Timer Configuration Poll History Clear Polling Mask 1 Polling Mask 2 Polling Mask 3 Polling Mask 4 Polling Mask 5 Polling Mask 6 Polling Mask 7 Polling Mask 8 Default ECh 40h 00h 00h 00h 08h -- 00h 02h 02h 03h 01h 00h 00h 00h 40h 02h 00h x0h 10h 00h XXh XXh XXh XXh XXh XXh XXh XXh Type RO R/W R/W, RO R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WC, RO R/W R/WC R/W R/W R/W R/W R/W R/W R/W R/W Table 8-7. Intel (R) ICH7 Family Datasheet 329 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.1 ASF_RID--ASF Revision Identification Register (LAN Controller--B1:D8:F0) Offset Address: E0h Default Value: ECh Bit 7:3 2:0 Attribute: Size: Description RO 8 bits ASF ID -- RO. Hardwired to 11101 to identify the ASF controller. ASF Silicon Revision -- RO. This field provides the silicon revision. 8.3.2 SMB_CNTL--SMBus Control Register (LAN Controller--B1:D8:F0) Offset Address: E1h Default Value: 40h Attribute: Size: R/W 8 bits This register is used to control configurations of the SMBus ports. Bit 7 Description SMBus Remote Control ASF Enable (SMB_RCASF) -- R/W. 0 = Legacy descriptors and operations are used. 1 = ASF descriptors and operations are used. SMBus ARP Enable (SMB_ARPEN) -- R/W. 6 5:4 3 2:0 0 = Disable. 1 = ASF enables the SMBus ARP protocol. Reserved SMBus Drive Low (SMB_DRVLO) -- R/W. 0 = ASF will not drive the main SMBus signals low while PWR_GOOD = 0. 1 = ASF will drive the main SMBus signals low while PWR_GOOD = 0. Reserved 330 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.3 ASF_CNTL--ASF Control Register (LAN Controller--B1:D8:F0) Offset Address: E2h Default Value: 00h Attribute: Size: R/W, RO 8 bits This register contains enables for special modes and SOS events. CTL_PWRLS should be set if ASF should be expecting a power loss due to software action. Otherwise, an EEPROM reload will happen when the power is lost. Bit 7 Description SMBus Hang SOS Enable (CTL_SMBHG) -- R/W. 0 = Disable 1 = Enables SMBus Hang SOS to be sent. Watchdog SOS Enable (CTL_WDG) -- R/W. 6 0 = Disable. 1 = Enables Watchdog SOS to be sent. Link Loss SOS Enable (CTL_LINK) -- R/W. 5 0 = Disable. 1 = Enables Link Loss SOS to be sent. OS Hung Status (CTL_OSHUNG) -- RO. 1 = This bit will be set to 1 when ASF has detected a Watchdog Expiration. NOTE: This condition is only clearable by a PCI RST# assertion (system reset). Power-Up SOS Enable (CTL_PWRUP) -- R/W. 3 2 0 = Disable. 1 = Enables Power-Up SOS to be sent. Reserved Receive ARP Enable (CTL_RXARP) -- R/W. The LAN controller interface provides a mode where all packets can be requested. 1 0 = Disable. 1 = Enable. ASF requests all packets when doing a Receive Enable. This is necessary in LAN controller to get ARP packets. NOTE: Changes to this bit will not take effect until the next Receive Enable command to the LAN. Power Loss OK (CTL_PWRLS) -- R/W. 0 0 = Power Loss will reload EEPROM 1 = Power Loss will not reload EEPROM 4 Intel (R) ICH7 Family Datasheet 331 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.4 ASF_CNTL_EN--ASF Control Enable Register (ASF Controller--B1:D8:F0) Offset Address: E3h Default Value: 00h Attribute: Size: R/W 8 bits This register is used to enable global processing as well as polling. GLOBAL ENABLE controls all of the SMBus processing and packet creation. Bit 7 0 = Disable 1 = All control and polling enabled Receive Enable (CENA_RX) -- R/W. 6 0 = Disable 1 = TCO Receives enabled. Transmit Enable (CENA_TX) -- R/W. 5 0 = Disable 1 = SOS and RMCP Transmits enabled ASF Polling Enable (CENA_APOL) -- R/W. 4 0 = Disable 1 = Enable ASF Sensor Polling. Legacy Polling Enable (CENA_LPOL) -- R/W. 3 0 = Disable 1 = Enable Legacy Sensor Polling. Number of Legacy Poll Devices (CENA_NLPOL) -- R/W. This 3-bit value indicates how many of the eight possible polling descriptors are active. 2:0 000 = First polling descriptor is active. 001 = First two polling descriptors are active. ... 111 = Enables all eight descriptors. Description Global Enable (CENA_ALL) -- R/W. 332 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.5 ENABLE--Enable Register (ASF Controller--B1:D8:F0) Offset Address: E4h Default Value: 00h Attribute: Size: R/W 8 bits This register provides the mechanism to enable internal SOS operations and to enable the remote control functions. Bit Description Enable OSHung ARPs (ENA_OSHARP) -- R/W. 7 0 = Disable 1 = ASF will request all packets when in a OSHung state. This allows ASF to receive ARP frames and respond as appropriate. State-based Security Destination Port Select (ENA_SB0298) -- R/W. 6 0 = State-based security will be honored on packets received on port 026Fh. 1 = Packets received on port 0298h will be honored. PET VLAN Enable (ENA_VLAN) -- R/W. 5 0 = Disable 1 = Indicates a VLAN header for PET NOTE: If this bit is set, the PET packet in EEPROM must have the VLAN tag within the packet. 4 3 Reserved System Power Cycle Enable (ENA_CYCLE) -- R/W. 0 = Disable 1 = Enables RMCP Power Cycle action. System Power-Down Enable (ENA_DWN) -- R/W. 2 0 = Disable 1 = Enables RMCP Power-Down action. System Power-Up Enable (ENA_UP) -- R/W. 1 0 = Disable 1 = Enables RMCP Power-Up action. System Reset Enable (ENA_RST) -- R/W. 0 0 = Disable 1 = Enables RMCP Reset action Intel (R) ICH7 Family Datasheet 333 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.6 APM--APM Register (ASF Controller--B1:D8:F0) Offset Address: E5h Default Value: 08h Attribute: Size: R/W 8 bits This register contains the configuration bit to disable state-based security. Bit 7:4 3 2:0 Reserved Disable State-based Security (APM_DISSB) -- R/W. 0 = State-based security on OSHung is enabled. 1 = State-based security is disabled and actions are not gated by OSHung. Reserved Description 8.3.7 WTIM_CONF--Watchdog Timer Configuration Register (ASF Controller--B1:D8:F0) Offset Address: E8h Default Value: 00h Attribute: Size: R/W 8 bits This register contains a single bit that enables the Watchdog timer. This bit is not intended to be accessed by software, but should be configured appropriately in the EEPROM location for this register default. The bit provides real-time control for enabling/disabling the Watchdog timer. When set the timer will count down. When cleared the counter will stop. Timer Start ASF SMBUS messages will set this bit. Timer Stop ASF SMBus transactions will clear this bit. Bit 7:1 0 Reserved Timer Enable (WDG_ENA) -- R/W. 0 = Disable 1 = Enable Counter Description 334 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.8 HEART_TIM--Heartbeat Timer Register (ASF Controller--B1:D8:F0) Offset Address: E9h Default Value: 02h Attribute: Size: R/W 8 bits The HeartBeat Timer register implements the heartbeat timer. This defines the period of the heartbeats packets. It contains a down counting value when enabled and the time-out value when the counter is disabled. The timer can be configured and enabled in a single write. Note: The heartbeat timer controls the heartbeat status packet frequency. The timer is freerunning and the configured time is only valid from one heartbeat to the next. When enabled by software, the next heartbeat may occur in any amount of time less than the configured time. Bit Description Heartbeat Timer Value (HBT_VAL) -- R/W. Heartbeat timer load value in 10.7-second resolution. This field can only be written while the timer is disabled. (10.7 sec - 23 min range). Read as load value when HBT_ENA=0. Read as decrementing value when HBT_ENA=1. Timer resolution is 10.7 seconds. A value of 00h is invalid. Timer Enable (HBT_ENA) -- R/W. 0 0 = Disable 1 = Enable / Reset Counter . 7:1 8.3.9 RETRAN_INT--Retransmission Interval Register (ASF Controller--B1:D8:F0) Offset Address: EAh Default Value: 02h Attribute: Size: R/W 8 bits This register implements the retransmission timer. This is the time between packet transmissions for multiple packets due to a SOS. Bit Description Retransmit Timer Value (RTM_VAL) -- R/W. Retransmit timer load value 2.7 second resolution. This field is always writable (2.7 sec - 5.7 min range). Timer is accurate to +0 seconds, -0.336 seconds. Reads always show the load value (decrement value not shown). A value of 00h is invalid. Reserved 7:1 0 Intel (R) ICH7 Family Datasheet 335 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.10 RETRAN_PCL--Retransmission Packet Count Limit Register (ASF Controller--B1:D8:F0) Offset Address: EBh Default Value: 03h Attribute: Size: R/W 8 bits This register defines the number of packets that are to be sent due to an SOS. Bit 7:0 Description Retransmission Packet Count Limit (RPC_VAL) -- R/W. This field provides the number of packets to be sent for all SOS packets that require retransmissions. 8.3.11 ASF_WTIM1--ASF Watchdog Timer 1 Register (ASF Controller--B1:D8:F0) Offset Address: ECh Default Value: 01h Attribute: Size: R/W 8 bits This register is used to load the low byte of the timer. When read, it reports the decrementing value. This register is not intended to be written by software, but should be configured appropriately in the EEPROM location for this register default. Timer Start ASF SMBus transactions will load values into this register. Once the timer has expired (0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will remain at 00h until otherwise changed. Bit 7:0 Description ASF Watchdog Timer 1 (AWD1_VAL) -- R/W. This field provides the low byte of the ASF 1-second resolution timer. The timer is accurate to +0 seconds, -0.336 seconds. 8.3.12 ASF_WTIM2--ASF Watchdog Timer 2 Register (ASF Controller--B1:D8:F0) Offset Address: EDh Default Value: 00h Attribute: Size: R/W 8 bits This register is used to load the high byte of the timer. When read, it reports the decrementing value. This register is not intended to be written by software, but should be configured appropriately in the EEPROM location for this register default. Timer Start ASF SMBus transactions will load values into this register. Once the timer has expired (0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will remain at 00h until otherwise changed. Bit 7:0 Description ASF Watchdog Timer 2 (AWD2_VAL) -- R/W. This field provides the high byte of the ASF 1-second resolution timer. The timer is accurate to +0 seconds, -0.336 seconds. 336 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.13 PET_SEQ1--PET Sequence 1 Register (ASF Controller--B1:D8:F0) Offset Address: F0h Default Value: 00h Attribute: Size: R/W 8 bits This register (low byte) holds the current value of the PET sequence number. This field is read/write-able through this register, and is also automatically incremented by the hardware when new PET packets are generated. By policy, software should not write to this register unless transmission is disabled. Bit 7:0 Description PET Sequence Byte 1 (PSEQ1_VAL) -- R/W. This field provides the low byte. 8.3.14 PET_SEQ2--PET Sequence 2 Register (ASF Controller--B1:D8:F0) Offset Address: F1h Default Value: 00h Attribute: Size: R/W 8 bits This register (high byte) holds the current value of the PET sequence number. This field is read/write-able through this register, and is also automatically incremented by the hardware when new PET packets are generated. By policy, software should not write to this register unless transmission is disabled. Bit 7:0 Description PET Sequence Byte 2 (PSEQ2_VAL) -- R/W. This field provides the high byte. Intel (R) ICH7 Family Datasheet 337 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.15 STA--Status Register (ASF Controller--B1:D8:F0) Offset Address: F2h Default Value: 40h Attribute: Size: R/W 8 bits This register gives status indication about several aspects of ASF. Bit 7 Description EEPROM Loading (STA_LOAD) -- R/W. EEPROM defaults are in the process of being loaded when this bit is a 1. EEPROM Invalid Checksum Indication (STA_ICRC) -- R/W. This bit should be read only after the EEC_LOAD bit is a 0. 0 = Valid 1 = Invalid checksum detected for ASF portion of the EEPROM. Reserved Power Cycle Status (STA_CYCLE) -- R/W. 3 0 = Software clears this bit by writing a 1. 1 = This bit is set when a Power Cycle operation has been issued. Power Down Status (STA_DOWN) -- R/W. 2 0 = Software clears this bit by writing a 1 1 = This bit is set when a Power Down operation has been issued. Power Up Status (STA_UP) -- R/W. 1 0 = Software clears this bit by writing a 1 1 = This bit is set when a Power Up operation has been issued. System Reset Status (STA_RST) -- R/W. 0 0 = Software clears this bit by writing a 1 1 = This bit is set when a System Reset operation has been issued. 6 5:4 338 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.16 FOR_ACT--Forced Actions Register (ASF Controller--B1:D8:F0) Offset Address: F3h Default Value: 02h Attribute: Size: R/W 8 bits This register contains many different forcible actions including APM functions, flushing internal pending SOS operations, software SOS operations, software reset, and EEPROM reload. Writes to this register must only set one bit per-write. Setting multiple bits in a single write can have indeterminate results. Note: For bits in this register, writing a 1 invokes the operation. The bits self-clear immediately. Bit 7 Description Software Reset (FRC_RST) -- R/W. This bit is used to reset the ASF controller. It performs the equivalent of a hardware reset and re-read the EEPROM. This bit selfclears immediately. Software should wait for the EEC_LOAD bit to clear. Force EEPROM Reload (FRC_EELD) -- R/W. Force Reload of EEPROM without affect current monitoring state of the ASF controller. This bit self-clears immediately. NOTE: Software registers in EEPROM are not loaded by this action. Software should disable the ASF controller before issuing this command and wait for STA_LOAD to clear before enabling again. Flush SOS (FRC_FLUSH) -- R/W. This bit is used to flush any pending SOSes or history internal to the ASF controller. This is necessary because the Status register only shows events that have happened as opposed to SOS events sent. Also, the history bits in the ASF controller are not software visible. Self-clears immediately. Reserved Force APM Power Cycle (FRC_ACYC) -- R/W. This mode forces the ASF controller to initiate a power cycle to the system. The bit self-clears immediately. Force APM Hard Power Down (FRC_AHDN) -- R/W. This mode forces the ASF controller to initiate a hard power down of the system immediately. The bit self-clears immediately. Clear ASF Polling History (FRC_CLRAPOL) -- R/W. Writing a 1b to this bit position will clear the Poll History associated with all ASF Polling. Writing a 0b has no effect. This bit self-clears immediately. Force APM Reset (FRC_ARST) -- R/W. This mode forces the ASF controller to initiate a hard reset of the system immediately. The bit self-clears immediately. 6 5 4 3 2 1 0 Intel (R) ICH7 Family Datasheet 339 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.17 RMCP_SNUM--RMCP Sequence Number Register (ASF Controller--B1:D8:F0) Offset Address: F4h Default Value: 00h Attribute: Size: R/W 8 bits This register is a means for software to read the current sequence number that hardware is using in RMCP packets. Software can also change the value. Software should only write to this register while the GLOBAL ENABLE is off. Bit Description RMCP Sequence Number (RSEQ_VAL) -- R/W. This is the current sequence number of the RMCP packet being sent or the sequence number of the next RMCP packet to be sent. This value can be set by software. At reset, it defaults to 00h. If the sequence number is not FFh, the ASF controller will automatically increment this number by one (or rollover to 00h if incrementing from FEh) after a successful RMCP packet transmission. 7:0 8.3.18 SP_MODE--Special Modes Register (ASF Controller--B1:D8:F0) Offset Address: F5h Default Value: x0h Attribute: Size: R/WC, RO 8 bits The register contains miscellaneous functions. Bit 7 Description SMBus Activity Bit (SPE_ACT) -- RO. 1 = ASF controller is active with a SMBus transaction. This is an indicator to software that the ASF controller is still processing commands on the SMBus. Watchdog Status (SPE_WDG) -- R/WC. 6 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a watchdog expiration occurs. Link Loss Status (SPE_LNK) -- R/WC. 5 4:0 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when a link loss occurs (link is down for more than 5 seconds). Reserved 8.3.19 INPOLL_TCONF--Inter-Poll Timer Configuration Register (ASF Controller--B1:D8:F0) Offset Address: F6h Default Value: 10h Attribute: Size: R/W 8 bits This register is used to load and hold the value (in increments of 5 ms) for the polling timer. This value determines how often the ASF polling timer expires which determines the minimum idle time between sensor polls. Bit 7:0 Description Inter-Poll Timer Configuration (IPTC_VAL) -- R/W. This field identifies the time, in 5.24 ms units that the ASF controller will wait between the end of the one ASF Poll Alert Message to start on the next. The value 00h is invalid and unsupported. 340 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.20 PHIST_CLR--Poll History Clear Register (ASF Controller--B1:D8:F0) Offset Address: F7h Default Value: 00h Attribute: Size: R/WC 8 bits This register is used to clear the history of the Legacy Poll operations. ASF maintains history of the last poll data for each Legacy Poll operation to compare against the current poll to detect changes. By setting the appropriate bit, the history for that Legacy Poll is cleared to 0s. Bit 7 Description Clear Polling Descriptor 8 History (PHC_POLL8) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #8. Writing a 0b has no effect. Clear Polling Descriptor 7 History (PHC_POLL7) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #7. Writing a 0b has no effect. Clear Polling Descriptor 6 History (PHC_POLL6) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #6. Writing a 0b has no effect. Clear Polling Descriptor 5 History (PHC_POLL5) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #5. Writing a 0b has no effect. Clear Polling Descriptor 4 History (PHC_POLL4) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #4. Writing a 0b has no effect. Clear Polling Descriptor 3 History (PHC_POLL3) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #3. Writing a 0b has no effect. Clear Polling Descriptor 2 History (PHC_POLL2) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #2. Writing a 0b has no effect. Clear Polling Descriptor 1 History (PHC_POLL1) -- R/WC. Writing a 1b to this bit position will clear the Poll History associated with Polling Descriptor #1. Writing a 0b has no effect. 6 5 4 3 2 1 0 8.3.21 PMSK1--Polling Mask 1 Register (ASF Controller--B1:D8:F0) Offset Address: F8h Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #1 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #1 (POL1_MSK) -- R/W. This field is used to read and write the data mask for Polling Descriptor #1. Software should only access this register when the ASF controller is GLOBAL DISABLED. Intel (R) ICH7 Family Datasheet 341 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.22 PMSK2--Polling Mask 2 Register (ASF Controller--B1:D8:F0) Offset Address: F9h Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #2 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #2 (POL2_MSK) -- R/W. This field is used to read and write the data mask for Polling Descriptor #2. Software should only access this register when the ASF controller is GLOBAL DISABLED. 8.3.23 PMSK3--Polling Mask 3 Register (ASF Controller--B1:D8:F0) Offset Address: FAh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #3 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #3 (POL3_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #3. Software should only access this register when the ASF controller is GLOBAL DISABLED. 8.3.24 PMSK4--Polling Mask 4 Register (ASF Controller--B1:D8:F0) Offset Address: FBh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #4 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #4 (POL4_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #4. Software should only access this register when the ASF controller is GLOBAL DISABLED. 342 Intel (R) ICH7 Family Datasheet LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.25 PMSK5--Polling Mask 5 Register (ASF Controller--B1:D8:F0) Offset Address: FCh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #5 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #5 (POL5_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #5. Software should only access this register when the ASF controller is GLOBAL DISABLED. 8.3.26 PMSK6--Polling Mask 6 Register (ASF Controller--B1:D8:F0) Offset Address: FDh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #6 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #6 (POL6_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #6. Software should only access this register when the ASF controller is GLOBAL DISABLED. 8.3.27 PMSK7--Polling Mask 7 Register (ASF Controller--B1:D8:F0) Offset Address: FEh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #7 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #7 (POL7_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #7. Software should only access this register when the ASF controller is GLOBAL DISABLED. Intel (R) ICH7 Family Datasheet 343 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) 8.3.28 PMSK8--Polling Mask 8 Register (ASF Controller--B1:D8:F0) Offset Address: FFh Default Value: XXh Attribute: Size: R/W 8 bits This register provides software an interface for the Polling #8 Data Mask. Bit 7:0 Description Polling Mask for Polling Descriptor #8 (POL8_MSK) -- R/W. This register is used to read and write the data mask for Polling Descriptor #8. Software should only access this register when the ASF controller is GLOBAL DISABLED. 344 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9 PCI-to-PCI Bridge Registers (D30:F0) The ICH7 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is handled by this PCI device. 9.1 Note: . PCI Configuration Registers (D30:F0) Address locations that are not shown should be treated as Reserved (see Section 6.2 for details). PCI Bridge Register Address Map (PCI-PCI--D30:F0) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Dh 0Eh 18h-1Ah 1Bh 1Ch-1Dh 1Eh-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 34h 3Ch-3Dh 3Eh-3Fh 40h-41h 44h-47h 48h-4Bh 4Ch-4Fh 50-51h 54h-57h Mnemonic VID DID PCICMD PSTS RID CC PMLT HEADTYP BNUM SMLT IOBASE_LIMIT SECSTS MEMBASE_LIMIT PREF_MEM_BASE _LIMIT PMBU32 PMLU32 CAPP INTR BCTRL SPDH DTC BPS BPC SVCAP SVID Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Primary Master Latency Timer Header Type Bus Number Secondary Master Latency Timer I/O Base and Limit Secondary Status Memory Base and Limit Prefetchable Memory Base and Limit Prefetchable Memory Upper 32 Bits Prefetchable Memory Limit Upper 32 Bits Capability List Pointer Interrupt Information Bridge Control Secondary PCI Device Hiding Delayed Transaction Control Bridge Proprietary Status Bridge Policy Configuration Subsystem Vendor Capability Pointer Subsystem Vendor IDs Default 8086h See register description 0000h 0010h See register description 00060401h 00h 81h 000000h 00h 0000h 0280h 00000000h 00010001h 00000000h 00000000h 50h 0000h 0000h 00h 00000000h 00000000h 00001200h 000Dh 00000000 Type RO RO R/W, RO R/WC, RO RO RO RO RO R/W, RO R/W, RO R/W, RO R/WC, RO R/W, RO R/W, RO R/W R/W RO R/W, RO R/WC, RO R/W, RO R/W, RO R/WC, RO R/W RO RO R/WO Table 9-1. Intel (R) ICH7 Family Datasheet 345 PCI-to-PCI Bridge Registers (D30:F0) 9.1.1 VID-- Vendor Identification Register (PCI-PCI--D30:F0) Offset Address: 00h-01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 9.1.2 DID-- Device Identification Register (PCI-PCI--D30:F0) Offset Address: 02h-03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID -- RO.This is a 16-bit value assigned to the PCI bridge. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 9.1.3 PCICMD--PCI Command (PCI-PCI--D30:F0) Offset Address: 04h-05h Default Value: 0000h Bit 15:11 10 9 Reserved Interrupt Disable (ID) -- RO. Hardwired to 0. The PCI bridge has no interrupts to disable Fast Back to Back Enable (FBE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. SERR# Enable (SERR_EN) -- R/W. 8 0 = Disable. 1 = Enable the Intel(R) ICH7 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit (offset 06h, bit 14) is set. Wait Cycle Control (WCC) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. Parity Error Response (PER) -- R/W. 6 0 = The ICH7 ignores parity errors on the PCI bridge. 1 = The ICH7 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the PCI bridge. VGA Palette Snoop (VPS) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. Memory Write and Invalidate Enable (MWE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a Special Cycle Enable (SCE) -- RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification. Attribute: Size: Description R/W, RO 16 bits 7 5 4 3 346 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) Bit Bus Master Enable (BME) -- R/W. 2 Description 0 = Disable 1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI. Memory Space Enable (MSE) -- R/W. Controls the response as a target for memory cycles targeting PCI. 0 = Disable 1 = Enable I/O Space Enable (IOSE) -- R/W. Controls the response as a target for I/O cycles targeting PCI. 0 = Disable 1 = Enable 1 0 9.1.4 PSTS--PCI Status Register (PCI-PCI--D30:F0) Offset Address: 06h-07h Default Value: 0010h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) -- R/WC. 15 0 = Parity error Not detected. 1 = Indicates that the Intel(R) ICH7 detected a parity error on the internal backbone. This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set. Intel (R) ICH7 Family Datasheet 347 PCI-to-PCI Bridge Registers (D30:F0) Bit Description Signaled System Error (SSE) -- R/WC. Several internal and external sources of the bridge can cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles where the bridge was the master. If either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge captures generic data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the bridge was the master. If either of these two conditions is met, and the secondary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. 14 The final class of errors is system bus errors. There are three status bits associated with system bus errors, each with a corresponding enable. The diagram capturing this is shown below. After checking for the three above classes of errors, an SERR# is generated, and PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below. Received Master Abort (RMA) -- R/WC. 13 0 = No master abort received. 1 = Set when the bridge receives a master abort status from the backbone. Received Target Abort (RTA) -- R/WC. 12 0 = No target abort received. 1 = Set when the bridge receives a target abort status from the backbone. 348 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) Bit Description Signaled Target Abort (STA) -- R/WC. 0 = No signaled target abort 1 = Set when the bridge generates a completion packet with target abort status on the backbone. Reserved. Data Parity Error Detected (DPD) -- R/WC. 0 = Data parity error Not detected. 1 = Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6). Reserved. Capabilities List (CLIST) -- RO. Hardwired to 1. Capability list exist on the PCI bridge. Interrupt Status (IS) -- RO. Hardwired to 0. The PCI bridge does not generate interrupts. Reserved 11 10:9 8 7:5 4 3 2:0 9.1.5 RID--Revision Identification Register (PCI-PCI--D30:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the Intel I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. (R) 9.1.6 CC--Class Code Register (PCI-PCI--D30:F0) Offset Address: 09h-0Bh Default Value: 060401h Bit 23:16 15:8 7:0 Attribute: Size: Description RO 24 bits Base Class Code (BCC) -- RO. Hardwired to 06h. Indicates this is a bridge device. Sub Class Code (SCC) -- RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge. Programming Interface (PI) -- RO. Hardwired to 01h. Indicates the bridge is subtractive decode Intel (R) ICH7 Family Datasheet 349 PCI-to-PCI Bridge Registers (D30:F0) 9.1.7 PMLT--Primary Master Latency Timer Register (PCI-PCI--D30:F0) Offset Address: 0Dh Default Value: 00h Bit 7:3 2:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) -- RO. Reserved per the PCI Express* Base Specification, Revision 1.0a. Reserved 9.1.8 HEADTYP--Header Type Register (PCI-PCI--D30:F0) Offset Address: 0Eh Default Value: 81h Bit Attribute: Size: Description RO 8 bits Multi-Function Device (MFD) -- RO. The value reported here depends upon the state of the AC `97 function hide (FD) register (Chipset Config Registers:Offset 3418h), per the following table: 7 FD.AAD 0 0 1 1 6:0 FD.AMD 0 1 0 1 MFD 1 1 1 0 Header Type (HTYPE) -- RO. This 7-bit field identifies the header layout of the configuration space, which is a PCI-to-PCI bridge in this case. 9.1.9 BNUM--Bus Number Register (PCI-PCI--D30:F0) Offset Address: 18h-1Ah Default Value: 000000h Bit 23:16 15:8 7:0 Attribute: Size: Description R/W, RO 24 bits Subordinate Bus Number (SBBN) -- R/W. Indicates the highest PCI bus number below the bridge. Secondary Bus Number (SCBN) -- R/W. Indicates the bus number of PCI. Primary Bus Number (PBN) -- RO. Hardwired to 00h for legacy software compatibility. 350 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9.1.10 SMLT--Secondary Master Latency Timer Register (PCI-PCI--D30:F0) Offset Address: 1Bh Default Value: 00h Attribute: Size: R/W, RO 8 bits This timer controls the amount of time the ICH7 PCI-to-PCI bridge will burst data on its secondary interface. The counter starts counting down from the assertion of FRAME#. If the grant is removed, then the expiration of this counter will result in the deassertion of FRAME#. If the grant has not been removed, then the ICH7 PCI-to-PCI bridge may continue ownership of the bus. Bit 7:3 2:0 Description Master Latency Timer Count (MLTC) -- R/W. This 5-bit field indicates the number of PCI clocks, in 8-clock increments, that the Intel(R) ICH7 remains as master of the bus. Reserved 9.1.11 IOBASE_LIMIT--I/O Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 1Ch-1Dh Default Value: 0000h Bit 15:12 11:8 7:4 3:0 Attribute: Size: Description R/W, RO 16 bits I/O Limit Address Limit bits[15:12] -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. II/O Limit Address Capability (IOLC) -- RO. Indicates that the bridge does not support 32-bit I/O addressing. I/O Base Address (IOBA) -- R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. I/O Base Address Capability (IOBC) -- RO. Indicates that the bridge does not support 32-bit I/O addressing. Intel (R) ICH7 Family Datasheet 351 PCI-to-PCI Bridge Registers (D30:F0) 9.1.12 SECSTS--Secondary Status Register (PCI-PCI--D30:F0) Offset Address: 1Eh-1Fh Default Value: 0280h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 Description Detected Parity Error (DPE) -- R/WC. 0 = Parity error not detected. 1 = Intel(R) ICH7 PCI bridge detected an address or data parity error on the PCI bus Received System Error (RSE) -- R/WC. 14 0 = SERR# assertion not received 1 = SERR# assertion is received on PCI. Received Master Abort (RMA) -- R/WC. 13 0 = No master abort. 1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is master-aborted. For (G)MCH/ICH7 interface packets that have completion required, this must also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11) Received Target Abort (RTA) -- R/WC. 12 0 = No target abort. 1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is target-aborted on PCI. For (G)MCH/ICH7 interface packets that have completion required, this event must also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11). Signaled Target Abort (STA) -- R/WC. 11 0 = No target abort. 1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort. DEVSEL# Timing (DEVT) -- RO. 01h = Medium decode timing. Data Parity Error Detected (DPD) -- R/WC. 8 0 = Conditions described below not met. 1 = The ICH7 sets this bit when all of the following three conditions are met: * * * The bridge is the initiator on PCI. PERR# is detected asserted or a parity error is detected internally BCTRL.PERE (D30:F0:3E bit 0) is set. 10:9 7 6 5 4:0 Fast Back to Back Capable (FBC) -- RO. Hardwired to 1 to indicate that the PCI to PCI target logic is capable of receiving fast back-to-back cycles. Reserved 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. This bridge is 33 MHz capable only. Reserved 352 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9.1.13 MEMBASE_LIMIT--Memory Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 20h-23h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits This register defines the base and limit, aligned to a 1-MB boundary, of the nonprefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit 31-20 19-16 15:4 3:0 Description Memory Limit (ML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. Reserved Memory Base (MB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. Reserved 9.1.14 PREF_MEM_BASE_LIMIT--Prefetchable Memory Base and Limit Register (PCI-PCI--D30:F0) Offset Address: 24h-27h Default Value: 00010001h Attribute: Size: R/W, RO 32-bit Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit 31-20 19-16 15:4 3:0 Description Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 64-bit Indicator (I64L) -- RO. Indicates support for 64-bit addressing. Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 64-bit Indicator (I64B) -- RO. Indicates support for 64-bit addressing. Intel (R) ICH7 Family Datasheet 353 PCI-to-PCI Bridge Registers (D30:F0) 9.1.15 PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI-PCI--D30:F0) Offset Address: 28h-2Bh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Base Upper Portion (PMBU) -- R/W. Upper 32-bits of the prefetchable address base. 9.1.16 PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCI--D30:F0) Offset Address: 2C-2Fh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. Upper 32-bits of the prefetchable address limit. 9.1.17 CAPP--Capability List Pointer Register (PCI-PCI--D30:F0) Offset Address: 34h Default Value: 50h Bit 7:0 Attribute: Size: Description RO 8 bits Capabilities Pointer (PTR) -- RO. Indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. 9.1.18 INTR--Interrupt Information Register (PCI-PCI--D30:F0) Offset Address: 3Ch-3Dh Default Value: 0000h Bit 15:8 Attribute: Size: Description R/W, RO 16 bits Interrupt Pin (IPIN) -- RO. The PCI bridge does not assert an interrupt. Interrupt Line (ILINE) -- R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Since the bridge does not generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification. 7:0 354 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9.1.19 BCTRL--Bridge Control Register (PCI-PCI--D30:F0) Offset Address: 3Eh-3Fh Default Value: 0000h Bit 15:12 Reserved Discard Timer SERR# Enable (DTE) -- R/W. Controls the generation of SERR# on the primary interface in response to the DTS bit being set: 0 = Do not generate SERR# on a secondary timer discard 1 = Generate SERR# in response to a secondary timer discard Discard Timer Status (DTS) -- R/WC. This bit is set to 1 when the secondary discard timer (see the SDT bit below) expires for a delayed transaction in the hard state. Secondary Discard Timer (SDT) -- R/W. This bit sets the maximum number of PCI clock cycles that the Intel(R) ICH7 waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the ICH7 PCI bridge. If the master has not repeated the transaction at least once before the counter expires, the ICH7 PCI bridge discards the transaction from its queue. 0 = The PCI master timeout value is between 215 and 216 PCI clocks 1 = The PCI master timeout value is between 210 and 211 PCI clocks 8 7 Primary Discard Timer (PDT) -- R/W. This bit is R/W for software compatibility only. Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. The PCI logic will not generate fast back-to-back cycles on the PCI bus. Secondary Bus Reset (SBR) -- R/W. This bit controls PCIRST# assertion on PCI. 6 0 = Bridge de-asserts PCIRST# 1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction buffers, posting buffers, and the PCI bus are initialized back to reset conditions. The rest of the part and the configuration registers are not affected. Master Abort Mode (MAM) -- R/W. This bit controls the ICH7 PCI bridge's behavior when a master abort occurs: Master Abort on (G)MCH/ICH7 Interconnect (DMI): 0 = Bridge asserts TRDY# on PCI. It drives all 1's for reads, and discards data on writes. 1 = Bridge returns a target abort on PCI. 5 Master Abort PCI (non-locked cycles): 0 = Normal completion status will be returned on the (G)MCH/ICH7 interconnect. 1 = Target abort completion status will be returned on the (G)MCH/ICH7 interconnect. NOTE: All locked reads will return a completer abort completion status on the (G)MCH/ ICH7 interconnect. 4 VGA 16-Bit Decode (V16D) -- R/W. This bit controls enables the ICH7 PCI bridge to provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the VGAE bit in this register be set. Attribute: Size: Description R/WC, RO 16 bits 11 10 9 Intel (R) ICH7 Family Datasheet 355 PCI-to-PCI Bridge Registers (D30:F0) Bit Description VGA Enable (VGAE) -- R/W. When set to a 1, the ICH7 PCI bridge forwards the following transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set. 3 * * Memory addresses: 000A0000h-000BFFFFh I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased). The same holds true from secondary accesses to the primary interface in reverse. That is, when the bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be claimed. ISA Enable (IE) -- R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the ICH7 PCI bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). SERR# Enable (SEE) -- R/W. This bit controls the forwarding of secondary interface SERR# assertions on the primary interface. When set, the PCI bridge will forward SERR# pin. * * * SERR# is asserted on the secondary interface. This bit is set. CMD.SEE (D30:F0:04 bit 8) is set. 2 1 Parity Error Response Enable (PERE) -- R/W. 0 0 = Disable 1 = The ICH7 PCI bridge is enabled for parity error reporting based on parity errors on the PCI bus. 9.1.20 SPDH--Secondary PCI Device Hiding Register (PCI-PCI--D30:F0) Offset Address: 40h-41h Default Value: 00h Attribute: Size: R/W, RO 16 bits This register allows software to hide the PCI devices, either plugged into slots or on the motherboard. Bit 15:8 7 6 5 4 3 Reserved Hide Device 7 (HD7) -- R/W, RO. Same as bit 0 of this register, except for device 7 (AD[23]) Hide Device 6 (HD6) -- R/W, RO. Same as bit 0 of this register, except for device 6 (AD[22]) Hide Device 5 (HD5) -- R/W, RO. Same as bit 0 of this register, except for device 5 (AD[21]) Hide Device 4 (HD4) -- R/W, RO. Same as bit 0 of this register, except for device 4 (AD[20]) Hide Device 3 (HD3) -- R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19]) Description 356 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) Bit 2 1 Description Hide Device 2 (HD2) -- R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18]) Hide Device 1 (HD1) -- R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17]) Hide Device 0 (HD0) -- R/W, RO. 0 = The PCI configuration cycles for this slot are not affected. 1 = Intel(R) ICH7 hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low) for configuration cycles to that device. Since the device will not see its IDSEL go active, it will not respond to PCI configuration cycles and the processor will think the device is not present. AD[16] is used as IDSEL for device 0. 0 9.1.21 DTC--Delayed Transaction Control Register (PCI-PCI--D30:F0) Offset Address: 44h-47h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits Discard Delayed Transactions (DDT) -- R/W. 0 = Logged delayed transactions are kept. 1 = The Intel(R) ICH7 PCI bridge will discard any delayed transactions it has logged. This includes transactions in the pending queue, and any transactions in the active queue, whether in the hard or soft DT state. The prefetchers will be disabled and return to an idle state. NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will continue until either the PCI master disconnects (by de-asserting FRAME#) or the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI bridge when the delayed transaction queues are empty and have returned to an idle state. Software sets this bit and polls for its completion Block Delayed Transactions (BDT) -- R/W. 30 0 = Delayed transactions accepted 1 = The ICH7 PCI bridge will not accept incoming transactions which will result in delayed transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory writes) will still be accepted. Reserved Maximum Delayed Transactions (MDT) -- R/W. This field controls the maximum number of delayed transactions that the ICH7 PCI bridge will run. Encodings are: 7: 6 00 =) 2 Active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) Reserved 5 Reserved Auto Flush After Disconnect Enable (AFADE) -- R/W. 4 0 = The PCI bridge will retain any fetched data until required to discard by producer/ consumer rules. 1 = The PCI bridge will flush any prefetched data after either the PCI master (by deasserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer. 31 29: 8 Intel (R) ICH7 Family Datasheet 357 PCI-to-PCI Bridge Registers (D30:F0) Bit Never Prefetch (NP) -- R/W. 3 Description 0 = Prefetch enabled 1 = The ICH7 will only fetch a single DW and will not enable prefetching, regardless of the command being an Memory read (MR), Memory read line (MRL), or Memory read multiple (MRM). Memory Read Multiple Prefetch Disable (MRMPD) -- R/W. 0 = MRM commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte aligned cache line. Memory Read Line Prefetch Disable (MRLPD) -- R/W. 0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line. Memory Read Prefetch Disable (MRPD) -- R/W. 0 = MR commands will fetch up to a 64-byte aligned cache line. 1 = Memory read (MR) commands will fetch only a single DW. 2 1 0 358 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9.1.22 BPS--Bridge Proprietary Status Register (PCI-PCI--D30:F0) Offset Address: 48h-4Bh Default Value: 00000000h Bit 31:17 Reserved PERR# Assertion Detected (PAD) -- R/WC. This bit is set by hardware whenever the PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the chipset is the agent driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and be a source for the NMI logic. This bit can be used by software to determine the source of a system problem. 15:7 Reserved Number of Pending Transactions (NPT) -- RO. This field indicates to debug software how many transactions are in the pending queue. Possible values are: 000 = No pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 6:4 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110 - 111 = Reserved NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than `00'. 3:2 Reserved Number of Active Transactions (NAT) -- RO. This field indicates to debug software how many transactions are in the active queue. Possible values are: 1:0 00 = No active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = Reserved Attribute: Size: Description R/WC, RO 32 bits 16 Intel (R) ICH7 Family Datasheet 359 PCI-to-PCI Bridge Registers (D30:F0) 9.1.23 BPC--Bridge Policy Configuration Register (PCI-PCI--D30:F0) Offset Address: 4Ch-4Fh Default Value: 00001200h Bit 31:14 Reserved Upstream Read Latency Threshold (URLT) -- R/W: This field specifies the number of PCI clocks after internally enqueuing an upstream memory read request at which point the PCI target logic should insert wait states in order to optimize lead-off latency. When the master returns after this threshold has been reached and data has not arrived in the Delayed Transaction completion queue, then the PCI target logic will insert wait states instead of immediately retrying the cycle. The PCI target logic will insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived yet). Note that the starting event for this Read Latency Timer is not explicitly visible externally. A value of 0h disables this policy completely such that wait states will not be inserted on the read lead-off data phase. The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks less than the typical idle lead-off latency expected for desktop Intel(R) ICH7 systems. This value may need to be changed by BIOS, depending on the platform. Subtractive Decode Policy (SDP) -- R/W. 0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other device on the backbone (primary interface) to the PCI bus (secondary interface). 1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the corresponding Space Enable bit is set in the Command register. NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI. PERR#-to-SERR# Enable (PSE) -- R/W. When this bit is set, a 1 in the PERR# Assertion status bit (in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register). SERR# is a source of NMI. Secondary Discard Timer Testmode (SDTT) -- R/W. 5 0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9) 1 = The secondary discard timer will expire after 128 PCI clocks. Reserved Peer Decode Enable (PDE) -- R/W. 2 0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O cycles are not claimed. 1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that falls outside of the memory and I/O window registers Reserved Received Target Abort SERR# Enable (RTAE) -- R/W. When set, the PCI bridge will report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and CMD.SEE (D30:F0:04 bit 8) is set. Attribute: Size: Description R/W, RO 32 bits 13:8 7 6 4:3 1 0 360 Intel (R) ICH7 Family Datasheet PCI-to-PCI Bridge Registers (D30:F0) 9.1.24 SVCAP--Subsystem Vendor Capability Register (PCI-PCI--D30:F0) Offset Address: 50h-51h Default Value: 000Dh Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) -- RO. Value of 00h indicates this is the last item in the list. Capability Identifier (CID) -- RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. 9.1.25 SVID--Subsystem Vendor IDs Register (PCI-PCI--D30:F0) Offset Address: 54h-57h Default Value: 00000000h Bit 31:16 Attribute: Size: Description R/WO 32 bits Subsystem Identifier (SID) -- R/WO. This field indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). Subsystem Vendor Identifier (SVID) -- R/WO. This field indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 Intel (R) ICH7 Family Datasheet 361 PCI-to-PCI Bridge Registers (D30:F0) 362 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10 LPC Interface Bridge Registers (D31:F0) The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers. Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.) are described in their respective sections. 10.1 Note: . PCI Configuration Registers (LPC I/F--D31:F0) Address locations that are not shown should be treated as Reserved. Table 10-1. LPC Interface PCI Register Address Map (LPC I/F--D31:F0) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Dh 0Eh 2Ch-2Fh 34h 40h-43h 44h 48h-4Bh 4C 60h-63h 64h 68h-6Bh 80h 82h-83h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC PLT HEADTYP SS CAPP PMBASE ACPI_CNTL GPIOBASE GC PIRQ[n]_ROUT SIRQ_CNTL PIRQ[n]_ROUT LPC_I/O_DEC LPC_EN Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Primary Latency Timer Header Type Sub System Identifiers Capability List Pointer ACPI Base Address ACPI Control GPIO Base Address GPIO Control PIRQ[A-D] Routing Control (Desktop and Mobile Only) Serial IRQ Control PIRQ[E-H] Routing Control I/O Decode Ranges LPC Interface Enables Default 8086h See register description. 0007h 0200h See register description. 00h 01h 06h 00h 80h 00000000h E0h 00000001h 00h 00000001h 00h 80h 10h 80h 0000h 0000h Type RO RO R/W, RO R/WC, RO RO RO RO RO RO RO R/WO RO R/W, RO R/W R/W, RO R/W R/W R/W, RO R/W R/W R/W Intel (R) ICH7 Family Datasheet 363 LPC Interface Bridge Registers (D31:F0) Table 10-1. LPC Interface PCI Register Address Map (LPC I/F--D31:F0) (Sheet 2 of 2) Offset 84h-87h 88h-8Bh 8Ch-8Eh 90h-93h A0h-CFh D0h-D3h D4h-D5h D8h-D9h DCh E0h-E1h E2h E3h E4h-EBh F0h-F3h Mnemonic GEN1_DEC GEN2_DEC GEN3_DEC GEN4_DEC -- FWH_SEL1 FWH_SEL2 FWH_DEC_EN1 BIOS_CNTL FDCAP FDLEN FDVER FDVCT RCBA Register Name LPC Interface Generic Decode Range 1 LPC Interface Generic Decode Range 2 LPC Interface Generic Decode Range 3 LPC Interface Generic Decode Range 4 Power Management (See Section 10.8.1) Firmware Hub Select 1 Firmware Hub Select 2 Firmware Hub Decode Enable 1 BIOS Control Feature Detection Capability ID Feature Detection Capability Length Feature Detection Version Feature Vector Root Complex Base Address Default 00000000h 00000000h 00000000h 00000000h -- 00112233h 4567h FFCFh 00h 0009h 0Ch 10h See Description 00000000h Type R/W R/W R/W R/W -- R/W, RO R/W R/W, RO R/WLO, R/W RO RO RO RO R/W 10.1.1 VID--Vendor Identification Register (LPC I/F--D31:F0) Offset Address: 00h-01h Default Value: 8086h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16-bit Core Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 10.1.2 DID--Device Identification Register (LPC I/F--D31:F0) Offset Address: 02h-03h Default Value: See bit description Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16-bit Core Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 LPC bridge. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 364 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.3 PCICMD--PCI COMMAND Register (LPC I/F--D31:F0) Offset Address: 04h-05h Default Value: 0007h Lockable: No Bit 15:10 9 8 7 Reserved Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. SERR# Enable (SERR_EN) -- R/W. The LPC bridge generates SERR# if this bit is set. Wait Cycle Control (WCC) -- RO. Hardwired to 0. Parity Error Response Enable (PERE) -- R/W. 6 0 = No action is taken when detecting a parity error. 1 = Enables the Intel(R) ICH7 LPC bridge to respond to parity errors detected on backbone interface. VGA Palette Snoop (VPS) -- RO. Hardwired to 0. Memory Write and Invalidate Enable (MWIE) -- RO. Hardwired to 0. Special Cycle Enable (SCE) -- RO. Hardwired to 0. Bus Master Enable (BME) -- RO. Bus Masters cannot be disabled. Memory Space Enable (MSE) -- RO. Memory space cannot be disabled on LPC. I/O Space Enable (IOSE) -- RO. I/O space cannot be disabled on LPC. Attribute: Size: Power Well: Description R/W, RO 16-bit Core 5 4 3 2 1 0 10.1.4 PCISTS--PCI Status Register (LPC I/F--D31:F0) Offset Address: 06-07h Default Value: 0210h Lockable: Noh Attribute: Size: Power Well: RO, R/WC 16-bit Core Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) -- R/WC. Set when the LPC bridge detects a parity error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0. 0 = Parity Error Not detected. 1 = Parity Error detected. 14 Signaled System Error (SSE)-- R/WC. Set when the LPC bridge signals a system error to the internal SERR# logic. Master Abort Status (RMA) -- R/WC. 13 0 = Unsupported request status not received. 1 = The bridge received a completion with unsupported request status from the backbone. Received Target Abort (RTA) -- R/WC. 12 0 = Completion abort not received. 1 = Completion with completion abort received from the backbone. 15 Intel (R) ICH7 Family Datasheet 365 LPC Interface Bridge Registers (D31:F0) Bit Description Signaled Target Abort (STA) -- R/WC. 0 = Target abort Not generated on the backbone. 1 = LPC bridge generated a completion packet with target abort status on the backbone. DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Medium Timing. Data Parity Error Detected (DPED) -- R/WC. 0 = All conditions listed below Not met. 1 = Set when all three of the following conditions are met: * * * LPC bridge receives a completion packet from the backbone from a previous request, Parity error has been detected (D31:F0:06, bit 15) PCICMD.PERE bit (D31:F0:04, bit 6) is set. 11 10:9 8 7 6 5 4 3 2:0 Fast Back to Back Capable (FBC): Reserved - bit has no meaning on the internal backbone. Reserved. 66 MHz Capable (66MHZ_CAP) -- Reserved - bit has no meaning on internal backbone. Capabilities List (CLIST) -- RO. Capability list exists on the LPC bridge. Interrupt Status (IS) -- RO. The LPC bridge does not generate interrupts. Reserved. 10.1.5 RID--Revision Identification Register (LPC I/F--D31:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID (RID) -- RO. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. 10.1.6 PI--Programming Interface Register (LPC I/F--D31:F0) Offset Address: 09h Default Value: 00h Bit 7:0 Programming Interface -- RO. Attribute: Size: Description RO 8 bits 366 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.7 SCC--Sub Class Code Register (LPC I/F--D31:F0) Offset Address: 0Ah Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Sub Class Code -- RO. 8-bit value that indicates the category of bridge for the LPC bridge. 01h = PCI-to-ISA bridge. 10.1.8 BCC--Base Class Code Register (LPC I/F--D31:F0) Offset Address: 0Bh Default Value: 06h Bit 7:0 Attribute: Size: Description RO 8 bits Base Class Code -- RO. 8-bit value that indicates the type of device for the LPC bridge. 06h = Bridge device. 10.1.9 PLT--Primary Latency Timer Register (LPC I/F--D31:F0) Offset Address: 0Dh Default Value: 00h Bit 7:3 2:0 Attribute: Size: Description RO 8 bits Master Latency Count (MLC) -- Reserved. Reserved. 10.1.10 HEADTYP--Header Type Register (LPC I/F--D31:F0) Offset Address: 0Eh Default Value: 80h Bit 7 6:0 Attribute: Size: Description RO 8 bits Multi-Function Device -- RO. This bit is 1 to indicate a multi-function device. Header Type -- RO. This 7-bit field identifies the header layout of the configuration space. Intel (R) ICH7 Family Datasheet 367 LPC Interface Bridge Registers (D31:F0) 10.1.11 SS--Sub System Identifiers Register (LPC I/F--D31:F0) Offset Address: 2Ch-2Fh Default Value: 00000000h Attribute: Size: R/WO 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# de-assertion. Bit 31:16 15:0 Description Subsystem ID (SSID) -- R/WO This is written by BIOS. No hardware action taken on this value. Subsystem Vendor ID (SSVID) -- R/WO This is written by BIOS. No hardware action taken on this value. 10.1.12 CAPP--Capability List Pointer (LPC I/F--D31:F0) Offset Address: 34h Default Value: E0h Attribute: Size: Power Well: Description Capability Pointer (CP) -- RO. Indicates the offset of the first item. RO 8 bits Core Bit 7:0 10.1.13 PMBASE--ACPI Base Address Register (LPC I/F--D31:F0) Offset Address: 40h-43h Default Value: 00000001h Lockable: No Attribute: Size: Usage: Power Well: R/W, RO 32 bit ACPI, Legacy Core Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries. Bit 31:16 15:7 6:1 0 Reserved Base Address -- R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate I/O space. Description 368 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.14 ACPI_CNTL--ACPI Control Register (LPC I/F -- D31:F0) Offset Address: 44h Default Value: 00h Lockable: No Attribute: Size: Usage: Power Well: Description ACPI Enable (ACPI_EN) -- R/W. 7 0 = Disable. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled. Note that the APM power management ranges (B2/B3h) are always enabled and are not affected by this bit. Reserved SCI IRQ Select (SCI_IRQ_SEL) -- R/W. Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20-23, and can be shared with other interrupts. Bits 000b 001b 2:0 010b 011b 100b 101b 110b 111b SCI Map IRQ9 IRQ10 IRQ11 Reserved IRQ20 (Only available if APIC enabled) IRQ21 (Only available if APIC enabled) IRQ22 (Only available if APIC enabled) IRQ23 (Only available if APIC enabled) R/W 8 bit ACPI, Legacy Core Bit 6:3 NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low 10.1.15 GPIOBASE--GPIO Base Address Register (LPC I/F -- D31:F0) Offset Address: 48h-4Bh Default Value: 00000001h Bit 31:16 15:6 5:1 0 Reserved. Always 0. Base Address (BA) -- R/W. Provides the 64 bytes of I/O space for GPIO. Reserved. Always 0. RO. Hardwired to 1 to indicate I/O space. Attribute: Size: Description R/W, RO 32 bit Intel (R) ICH7 Family Datasheet 369 LPC Interface Bridge Registers (D31:F0) 10.1.16 GC--GPIO Control Register (LPC I/F -- D31:F0) Offset Address: 4Ch Default Value: 00h Bit 7:5 Reserved. GPIO Enable (EN) -- R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function. 0 = Disable. 1 = Enable. Reserved. Attribute: Size: Description R/W 8 bit 4 3:0 10.1.17 PIRQ[n]_ROUT--PIRQ[A,B,C,D] Routing Control Register (LPC I/F--D31:F0) (Desktop and Mobile Only) Offset Address: PIRQA - 60h, PIRQB - 61h, PIRQC - 62h, PIRQD - 63h Default Value: 80h Lockable: No Bit Attribute: R/W Size: 8 bit Power Well: Core Description Interrupt Routing Enable (IRQEN) -- R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 7 6:4 Reserved IRQ Routing -- R/W. (ISA compatible.) Value 0000b 0001b IRQ Reserved Reserved Reserved IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Value 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b IRQ Reserved IRQ9 IRQ10 IRQ11 IRQ12 Reserved IRQ14 IRQ15 3:0 0010b 0011b 0100b 0101b 0110b 0111b 370 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.18 SIRQ_CNTL--Serial IRQ Control Register (LPC I/F--D31:F0) Offset Address: 64h Default Value: 10h Lockable: No Bit 7 Attribute: Size: Power Well: Description R/W, RO 8 bit Core Serial IRQ Enable (SIRQEN) -- R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ. Serial IRQ Mode Select (SIRQMD) -- R/W. 0 = The serial IRQ machine will be in quiet mode. 1 = The serial IRQ machine will be in continuous mode. 6 NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet Mode. Failure to do so will result in the Intel(R) ICH7 not recognizing SERIRQ interrupts. Serial IRQ Frame Size (SIRQSZ) -- RO. Fixed field that indicates the size of the SERIRQ frame as 21 frames. Start Frame Pulse Width (SFPW) -- R/W. This is the number of PCI clocks that the SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH7 will drive the start frame for the number of clocks specified. In quiet mode, the ICH7 will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = Reserved 5:2 1:0 Intel (R) ICH7 Family Datasheet 371 LPC Interface Bridge Registers (D31:F0) 10.1.19 PIRQ[n]_ROUT--PIRQ[E,F,G,H] Routing Control Register (LPC I/F--D31:F0) Offset Address: PIRQE - 68h, PIRQF - 69h, Attribute: PIRQG - 6Ah, PIRQH - 6Bh Default Value: 80h Size: Lockable: No Power Well: Bit Description Interrupt Routing Enable (IRQEN) -- R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 6:4 Reserved IRQ Routing -- R/W. (ISA compatible.) Value 0000b 0001b 3:0 0010b 0011b 0100b 0101b 0110b 0111b IRQ Reserved Reserved Reserved IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Value 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b IRQ Reserved IRQ9 IRQ10 IRQ11 IRQ12 Reserved IRQ14 IRQ15 R/W 8 bit Core 7 372 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.20 LPC_I/O_DEC--I/O Decode Ranges Register (LPC I/F--D31:F0) Offset Address: 80h Default Value: 0000h Bit 15:13 12 11:10 Reserved FDD Decode Range -- R/W. Determines which range to decode for the FDD Port 0 = 3F0h - 3F5h, 3F7h (Primary) 1 = 370h - 375h, 377h (Secondary) Reserved LPT Decode Range -- R/W. This field determines which range to decode for the LPT Port. 9:8 00 01 10 11 = = = = 378h - 37Fh and 778h - 77Fh 278h - 27Fh (port 279h is read only) and 678h - 67Fh 3BCh -3BEh and 7BCh - 7BEh Reserved Attribute: Size: Description R/W 16 bit 7 Reserved COMB Decode Range -- R/W. This field determines which range to decode for the COMB Port. 000 = 3F8h - 3FFh (COM1) 001 = 2F8h - 2FFh (COM2) 010 = 220h - 227h 011 = 228h - 22Fh 100 = 238h - 23Fh 101 = 2E8h - 2EFh (COM4) 110 = 338h - 33Fh 111 = 3E8h - 3EFh (COM3) 6:4 3 Reserved COMA Decode Range -- R/W. This field determines which range to decode for the COMA Port. 000 = 3F8h - 3FFh (COM1) 001 = 2F8h - 2FFh (COM2) 010 = 220h - 227h 011 = 228h - 22Fh 100 = 238h - 23Fh 101 = 2E8h - 2EFh (COM4) 110 = 338h - 33Fh 111 = 3E8h - 3EFh (COM3) 2:0 Intel (R) ICH7 Family Datasheet 373 LPC Interface Bridge Registers (D31:F0) 10.1.21 LPC_EN--LPC I/F Enables Register (LPC I/F--D31:F0) Offset Address: 82h - 83h Default Value: 0000h Attribute: Size: Power Well: Description Reserved CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. 13 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller. CNF1_LPC_EN -- R/W. Super I/O Enable. 12 0 = Disable. 1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used for Super I/O devices. MC_LPC_EN -- R/W. Microcontroller Enable # 1. 11 0 = Disable. 1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used for a microcontroller. KBC_LPC_EN -- R/W. Keyboard Enable. 10 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. GAMEH_LPC_EN -- R/W. High Gameport Enable 9 0 = Disable. 1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used for a gameport. GAMEL_LPC_EN -- R/W. Low Gameport Enable 8 0 = Disable. 1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is used for a gameport. Reserved FDD_LPC_EN -- R/W. Floppy Drive Enable 3 0 = Disable. 1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12). LPT_LPC_EN -- R/W. Parallel Port Enable 2 0 = Disable. 1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8). COMB_LPC_EN -- R/W. Com Port B Enable 1 0 = Disable. 1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4). COMA_LPC_EN -- R/W. Com Port A Enable 0 0 = Disable. 1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2). R/W 16 bit Core Bit 15:14 7:4 374 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.22 GEN1_DEC--LPC I/F Generic Decode Range 1 Register (LPC I/F--D31:F0) Offset Address: 84h - 87h Default Value: 00000000h Attribute: Size: Power Well: Description Reserved Generic I/O Decode Range Address[7:2] Mask: A `1' in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. Reserved Generic I/O Decode Range 1 Base Address (GEN1_BASE) -- R/W. This address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. NOTE: The Intel(R) ICH7 does not provide decode down to the word or byte level. 1 0 Reserved Generic Decode Range 1 Enable (GEN1_EN) -- R/W. 0 = Disable. 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F R/W 32 bit Core Bit 31:24 23:18 17:16 15:2 10.1.23 GEN2_DEC--LPC I/F Generic Decode Range 2Register (LPC I/F--D31:F0) Offset Address: 88h - 8Bh Default Value: 00000000h Attribute: Size: Power Well: Description Reserved Generic I/O Decode Range Address[7:2] Mask: A `1' in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. Reserved Generic I/O Decode Range 2Base Address (GEN1_BASE) -- R/W. 15:2 1 0 NOTE: The Intel(R) ICH7 does not provide decode down to the word or byte level. Reserved Generic Decode Range 2Enable (GEN2_EN) -- R/W. 0 = Disable. 1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F R/W 32 bit Core Bit 31:24 23:18 17:16 Intel (R) ICH7 Family Datasheet 375 LPC Interface Bridge Registers (D31:F0) 10.1.24 GEN3_DEC--LPC I/F Generic Decode Range 3Register (LPC I/F--D31:F0) Offset Address: 8Ch - 8Eh Default Value: 00000000h Attribute: Size: Power Well: Description Reserved Generic I/O Decode Range Address[7:2] Mask: A `1' in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. Reserved Generic I/O Decode Range 3Base Address (GEN3_BASE) -- R/W. 15:2 1 0 NOTE: The Intel(R) ICH7 does not provide decode down to the word or byte level. Reserved Generic Decode Range 3Enable (GEN3_EN) -- R/W. 0 = Disable. 1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F R/W 32 bit Core Bit 31:24 23:18 17:16 10.1.25 GEN4_DEC--LPC I/F Generic Decode Range 4Register (LPC I/F--D31:F0) Offset Address: 90h - 93h Default Value: 00000000h Attribute: Size: Power Well: Description Reserved Generic I/O Decode Range Address[7:2] Mask: A `1' in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. Reserved Generic I/O Decode Range 4Base Address (GEN4_BASE) -- R/W. 15:2 1 0 NOTE: The Intel(R) ICH7 does not provide decode down to the word or byte level. Reserved Generic Decode Range 4Enable (GEN4_EN) -- R/W. 0 = Disable. 1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F R/W 32 bit Core Bit 31:24 23:18 17:16 376 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.26 FWH_SEL1--Firmware Hub Select 1 Register (LPC I/F--D31:F0) Offset Address: D0h-D3h Default Value: 00112233h Bit Attribute: Size: Description R/W, RO 32 bits 31:28 FWH_F8_IDSEL -- RO. IDSEL for two 512-KB Firmware Hub memory ranges and one 128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field addresses the following memory ranges: FFF8 0000h - FFFF FFFFh FFB8 0000h - FFBF FFFFh 000E 0000h - 000F FFFFh FWH_F0_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFF0 0000h - FFF7 FFFFh FFB0 0000h - FFB7 FFFFh FWH_E8_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE8 0000h - FFEF FFFFh FFA8 0000h - FFAF FFFFh FWH_E0_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE0 0000h - FFE7 FFFFh FFA0 0000h - FFA7 FFFFh FWH_D8_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h - FFDF FFFFh FF98 0000h - FF9F FFFFh FWH_D0_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h - FFD7 FFFFh FF90 0000h - FF97 FFFFh FWH_C8_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h - FFCF FFFFh FF88 0000h - FF8F FFFFh FWH_C0_IDSEL -- R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h - FFC7 FFFFh FF80 0000h - FF87 FFFFh 27:24 23:20 19:16 15:12 11:8 7:4 3:0 Intel (R) ICH7 Family Datasheet 377 LPC Interface Bridge Registers (D31:F0) 10.1.27 FWH_SEL2--Firmware Hub Select 2 Register (LPC I/F--D31:F0) Offset Address: D4h-D5h Default Value: 4567h Bit Attribute: Size: Description R/W 16 bits 15:12 FWH_70_IDSEL -- R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF70 0000h - FF7F FFFFh FF30 0000h - FF3F FFFFh FWH_60_IDSEL -- R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF60 0000h - FF6F FFFFh FF20 0000h - FF2F FFFFh FWH_50_IDSEL -- R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF50 0000h - FF5F FFFFh FF10 0000h - FF1F FFFFh FWH_40_IDSEL -- R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF40 0000h - FF4F FFFFh FF00 0000h - FF0F FFFFh 11:8 7:4 3:0 10.1.28 FWH_DEC_EN1--Firmware Hub Decode Enable Register (LPC I/F--D31:F0) Offset Address: D8h-D9h Default Value: FFCFh Bit Attribute: Size: Description R/W, RO 16 bits FWH_F8_EN -- RO. This bit enables decoding two 512-KB Firmware Hub memory ranges, and one 128-KB memory range. 15 0 = Disable 1 = Enable the following ranges for the Firmware Hub FFF80000h - FFFFFFFFh FFB80000h - FFBFFFFFh FWH_F0_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 14 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFF00000h - FFF7FFFFh FFB00000h - FFB7FFFFh FWH_E8_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 13 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE80000h - FFEFFFFh FFA80000h - FFAFFFFFh 378 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description FWH_E0_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 12 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE00000h - FFE7FFFFh FFA00000h - FFA7FFFFh FWH_D8_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 11 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD80000h - FFDFFFFFh FF980000h - FF9FFFFFh FWH_D0_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 10 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD00000h - FFD7FFFFh FF900000h - FF97FFFFh FWH_C8_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 9 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC80000h - FFCFFFFFh FF880000h - FF8FFFFFh FWH_C0_EN -- R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 8 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC00000h - FFC7FFFFh FF800000h - FF87FFFFh FWH_Legacy_F_EN -- R/W. This enables the decoding of the legacy 128-K range at F0000h - FFFFFh. 7 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub F0000h - FFFFFh FWH_Legacy_E_EN -- R/W. This enables the decoding of the legacy 128-K range at E0000h - EFFFFh. 6 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub E0000h - EFFFFh Reserved FWH_70_EN -- R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF70 0000h - FF7F FFFFh FF30 0000h - FF3F FFFFh 5:4 3 Intel (R) ICH7 Family Datasheet 379 LPC Interface Bridge Registers (D31:F0) Bit Description FWH_60_EN -- R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF60 0000h - FF6F FFFFh FF20 0000h - FF2F FFFFh FWH_50_EN -- R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF50 0000h - FF5F FFFFh FF10 0000h - FF1F FFFFh FWH_40_EN -- R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF40 0000h - FF4F FFFFh FF00 0000h - FF0F FFFFh 2 1 0 Note: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or SPI (Desktop and Mobile Only). The concept of Feature Space does not apply to SPIbased flash. The ICH7simply decodes these ranges as memory accesses when enabled for the SPI flash interface. 380 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.29 BIOS_CNTL--BIOS Control Register (LPC I/F--D31:F0) Offset Address: DCh Default Value: 00h Lockable: No Bit 7:5 4 Reserved Top Swap Status (TSS)-- RO: This bit provides a read-only path to view the state of the Top Swap bit that is at offset 3414h, bit 0. SPI Read Configuration (SRC)-- R/W: This 2-bit field controls two policies related to BIOS reads on the SPI interface: Bit 3- Prefetch Enable Bit 2- Cache Disable Settings are summarized below: Bits 3:2 3:2 (Desktop and Mobile Only) 00b Description No prefetching, but caching enabled. 64B demand reads load the read buffer cache with "valid" data, allowing repeated code fetches to the same line to complete quickly No prefetching and no caching. One-to-one correspondence of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. Prefetching and Caching enabled. This mode is used for long sequences of short reads to consecutive addresses (i.e., shadowing). Reserved. This is an invalid configuration, caching must be enabled when prefetching is enabled. Attribute: Size: Power Well: Description R/WLO, R/W, RO 8 bit Core 01b 10b 11b 3:2 (Ultra Mobile Only) Reserved BIOS Lock Enable (BLE) -- R/WLO. 1 0 = Setting the BIOSWE will not cause SMIs. 1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a PLTRST# BIOS Write Enable (BIOSWE) -- R/W. 0 = Only read cycles permitted to Firmware Hub or SPI flash. 1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMI code can update BIOS. NOTE: Writes to the Firmware Hub's Feature Space are not blocked when the BIOSWE is cleared in order to allow access to registers. The Feature Space is the second range that is located 4 MB below the BIOS range for each Firmware Hub. 0 Intel (R) ICH7 Family Datasheet 381 LPC Interface Bridge Registers (D31:F0) 10.1.30 FDCAP--Feature Detection Capability ID (LPC I/F--D31:F0) Offset Address: E0h-E1h Default Value: 0009h Attribute: Size: Power Well: Description Next Item Pointer (NEXT): Configuration offset of the next Capability Item. 00h indicates the last item in the Capability List. Capability ID: Indicates a Vendor Specific Capability RO 16 bit Core Bit 15:8 7:0 10.1.31 FDLEN--Feature Detection Capability Length (LPC I/F--D31:F0) Offset Address: E2h Default Value: 0Ch Attribute: Size: Power Well: Description Capability Length: Indicates the length of this Vendor Specific capability, as required by PCI Spec. RO 8 bit Core Bit 7:0 10.1.32 FDVER--Feature Detection Version (LPC I/F--D31:F0) Offset Address: E3h Default Value: 10h Attribute: Size: Power Well: Description Vendor-Specific Capability ID: A value of 1h in this 4-bit field identifies this Capability as Feature Detection Type. This field allows software to differentiate the Feature Detection Capability from other Vendor-Specific capabilities Capability Version: This field indicates the version of the Feature Detection capability RO 8 bit Core Bit 7:4 3:0 382 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.1.33 FDVCT--Feature Vector Register (LPC I/F--D31:F0) Offset Address: E4h-EBh Default Value: See Description Attribute: Size: Power Well: Description Reserved Intel(R) Active Management Technology Capability-- RO: 0 = Capable 1 = Disabled RO 64 bit Core Bit 63:33 32 (Desktop and Mobile Only) 32 (Ultra Mobile Only) 31:22 Reserved Reserved Intel(R) ICH7DH Only: Intel(R) Quick Resume Technology Capability-- RO: 0 = Capable 1 = Disabled ICH7 and ICH7R Only: Reserved 21 (Desktop Only) 21 (Mobile/ Ultra Mobile Only) 20:19 18 (Desktop and Mobile Only) 18 (Ultra Mobile) 17:10 9 (Mobile/ Utlra Mobile Only) 9 (Desktop Only) 8 7 (Desktop and Mobile Only) Reserved. Reserved SATA RAID 5 Capability-- RO: 0 = Capable 1 = Disabled Reserved Reserved Mobile Features Capability-- RO: 0 = Disabled 1 = Capable Reserved Reserved PCI Express* 6 x1 Capability-- RO: 0 = Capable 1 = Disabled - 4 PCI Express x1 Ports available Intel (R) ICH7 Family Datasheet 383 LPC Interface Bridge Registers (D31:F0) Bit 7 (Ultra Mobile Only) 6 5 (Desktop and Mobile Only) 5 (Ultra Mobile Only) 4 3 (Desktop and Mobile Only) 3 (Ultra Mobile Only) 2:0 Description Reserved Reserved SATA RAID 0/1/10 Capability-- RO: 0 = Capable 1 = Disabled Reserved Reserved SATA AHCI Capability-- RO: 0 = Capable 1 = Disabled Reserved Reserved 10.1.34 RCBA--Root Complex Base Address Register (LPC I/F--D31:F0) Offset Address: F0h Default Value: 00000000h Bit 31:14 13:1 0 Attribute: Size: Description R/W 32 bit Base Address (BA) -- R/W. Base Address for the root complex register block decode range. This address is aligned on a 16-KB boundary. Reserved Enable (EN) -- R/W. When set, this bit enables the range specified in BA to be claimed as the Root Complex Register Block. 384 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.2 DMA I/O Registers (LPC I/F--D31:F0) Table 10-2. DMA Registers (Sheet 1 of 2) Port 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 80h 81h 82h 83h 84h-86h 87h 88h 89h 8Ah 8Bh 8Ch-8Eh 8Fh C0h C2h C4h C6h C8h CAh CCh Alias 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 90h 91h -- 93h 94h-96h 97h 98h 99h 9Ah 9Bh 9Ch-9Eh 9Fh C1h C3h C5h C7h C9h CBh CDh Register Name Channel 0 DMA Base & Current Address Channel 0 DMA Base & Current Count Channel 1 DMA Base & Current Address Channel 1 DMA Base & Current Count Channel 2 DMA Base & Current Address Channel 2 DMA Base & Current Count Channel 3 DMA Base & Current Address Channel 3 DMA Base & Current Count Channel 0-3 DMA Command Channel 0-3 DMA Status Channel 0-3 DMA Write Single Mask Channel 0-3 DMA Channel Mode Channel 0-3 DMA Clear Byte Pointer Channel 0-3 DMA Master Clear Channel 0-3 DMA Clear Mask Channel 0-3 DMA Write All Mask Reserved Page Channel 2 DMA Memory Low Page Channel 3 DMA Memory Low Page Channel 1 DMA Memory Low Page Reserved Pages Channel 0 DMA Memory Low Page Reserved Page Channel 6 DMA Memory Low Page Channel 7 DMA Memory Low Page Channel 5 DMA Memory Low Page Reserved Page Refresh Low Page Channel 4 DMA Base & Current Address Channel 4 DMA Base & Current Count Channel 5 DMA Base & Current Address Channel 5 DMA Base & Current Count Channel 6 DMA Base & Current Address Channel 6 DMA Base & Current Count Channel 7 DMA Base & Current Address Default Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000001XXb 000000XXb Undefined Undefined Undefined 0Fh Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Type R/W R/W R/W R/W R/W R/W R/W R/W WO RO WO WO WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Intel (R) ICH7 Family Datasheet 385 LPC Interface Bridge Registers (D31:F0) Table 10-2. DMA Registers (Sheet 2 of 2) Port CEh D0h D4h D6h D8h DAh DCh DEh Alias CFh D1h D5h D7h D9h DBh DDh DFh Register Name Channel 7 DMA Base & Current Count Channel 4-7 DMA Command Channel 4-7 DMA Status Channel 4-7 DMA Write Single Mask Channel 4-7 DMA Channel Mode Channel 4-7 DMA Clear Byte Pointer Channel 4-7 DMA Master Clear Channel 4-7 DMA Clear Mask Channel 4-7 DMA Write All Mask Default Undefined Undefined Undefined 000001XXb 000000XXb Undefined Undefined Undefined 0Fh Type R/W WO RO WO WO WO WO WO R/W 10.2.1 DMABASE_CA--DMA Base and Current Address Registers (LPC I/F--D31:F0) I/O Address: Ch. #0 Ch. #2 Ch. #5 Ch. #7 Undef No = = = = 00h; Ch. #1 = 02h 04h; Ch. #3 = 06h C4h Ch. #6 = C8h CCh; Attribute: Size: R/W 16 bit (per channel), but accessed in two 8-bit quantities Default Value: Lockable: Bit Power Well: Core Description Base and Current Address -- R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned from the Current Address register. The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated. For transfers to/from a 16-bit slave (channel's 5-7), the address is shifted left one bit location. Bit 15 will be shifted into Bit 16. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. 15:0 386 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.2.2 DMABASE_CC--DMA Base and Current Count Registers (LPC I/F--D31:F0) I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Ch. #2 = 05h; Ch. #3 = 07h Ch. #5 = C6h; Ch. #6 = CAh Ch. #7 = CEh; Undefined No Attribute: Size: R/W 16-bit (per channel), but accessed in two 8-bit quantities Default Value: Lockable: Bit Power Well: Core Description Base and Current Count -- R/W. This register determines the number of transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Count register and copied to the Current Count register. On reads, the value is returned from the Current Count register. The actual number of transfers is one more than the number programmed in the Base Count Register (i.e., programming a count of 4h results in 5 transfers). The count is decrements in the Current Count register after each transfer. When the value in the register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in autoinitialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is generated. For transfers to/from an 8-bit slave (channels 0-3), the count register indicates the number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5-7), the count register indicates the number of words to be transferred. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. 15:0 10.2.3 DMAMEM_LP--DMA Memory Low Page Registers (LPC I/F--D31:F0) I/O Address: Ch. #0 = 87h; Ch. #1 = 83h Ch. #2 = 81h; Ch. #3 = 82h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Attribute: Undefined Size: No Power Well: Description DMA Low Page (ISA Address bits [23:16]) -- R/W. This register works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address register. Default Value: Lockable: Bit R/W 8-bit Core 7:0 Intel (R) ICH7 Family Datasheet 387 LPC Interface Bridge Registers (D31:F0) 10.2.4 DMACMD--DMA Command Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:5 Reserved. Must be 0. DMA Group Arbitration Priority -- WO. Each channel group is individually assigned either fixed or rotating arbitration priority. At part reset, each group is initialized in fixed priority. 0 = Fixed priority to the channel group 1 = Rotating priority to the group. 3 Reserved. Must be 0. DMA Channel Group Enable -- WO. Both channel groups are enabled following part reset. 2 0 = Enable the DMA channel group. 1 = Disable. Disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. Reserved. Must be 0. Ch. #0-3 = 08h; Ch. #4-7 = D0h Undefined No Attribute: Size: Power Well: Description WO 8-bit Core 4 1:0 10.2.5 DMASTA--DMA Status Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit Ch. #0-3 = 08h; Ch. #4-7 = D0h Undefined No Attribute: Size: Power Well: Description RO 8-bit Core 7:4 Channel Request Status -- RO. When a valid DMA request is pending for a channel, the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the request status for channels 0 through 3. 4 = Channel 0 5 = Channel 1 (5) 6 = Channel 2 (6) 7 = Channel 3 (7) Channel Terminal Count Status -- RO. When a channel reaches terminal count (TC), its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the TC bit response for channel 4 is irrelevant: 3:0 0 = Channel 0 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7) 388 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.2.6 DMA_WRSMSK--DMA Write Single Mask Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:3 Reserved. Must be 0. Channel Mask Select -- WO. 2 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. DMA Channel Select -- WO. These bits select the DMA Channel Mode Register to program. 1:0 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7) Ch. #0-3 = 0Ah; Ch. #4-7 = D4h 0000 01xx No Attribute: Size: Power Well: Description WO 8-bit Core Intel (R) ICH7 Family Datasheet 389 LPC Interface Bridge Registers (D31:F0) 10.2.7 DMACH_MODE--DMA Channel Mode Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit Ch. #0-3 = 0Bh; Ch. #4-7 = D6h 0000 00xx No Attribute: Size: Power Well: Description WO 8-bit Core DMA Transfer Mode -- WO. Each DMA channel can be programmed in one of four different modes: 7:6 00 = Demand mode 01 = Single mode 10 = Reserved 11 = Cascade mode Address Increment/Decrement Select -- WO. This bit controls address increment/ decrement during DMA transfers. 0 = Address increment. (default after part reset or Master Clear) 1 = Address decrement. Autoinitialize Enable -- WO. 4 0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear disables autoinitialization. 1 = DMA restores the Base Address and Count registers to the current registers following a terminal count (TC). DMA Transfer Type -- WO. These bits represent the direction of the DMA transfer. When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 3:2 00 = Verify - No I/O or memory strobes generated 01 = Write - Data transferred from the I/O devices to memory 10 = Read - Data transferred from memory to the I/O device 11 = Invalid DMA Channel Select -- WO. These bits select the DMA Channel Mode Register that will be written by bits [7:2]. 1:0 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7) 5 390 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.2.8 DMA Clear Byte Pointer Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit Ch. #0-3 = 0Ch; Ch. #4-7 = D8h xxxx xxxx No Attribute: Size: Power Well: Description WO 8-bit Core 7:0 Clear Byte Pointer -- WO. No specific pattern. Command enabled with a write to the I/O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command. This command precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. 10.2.9 DMA Master Clear Register (LPC I/F--D31:F0) I/O Address: Default Value: Bit 7:0 Ch. #0-3 = 0Dh; Ch. #4-7 = DAh xxxx xxxx Attribute: Size: Description WO 8-bit Master Clear -- WO. No specific pattern. Enabled with a write to the port. This has the same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and the Mask Register is set. 10.2.10 DMA_CLMSK--DMA Clear Mask Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:0 Ch. #0-3 = 0Eh; Ch. #4-7 = DCh xxxx xxxx No Attribute: Size: Power Well: Description WO 8-bit Core Clear Mask Register -- WO. No specific pattern. Command enabled with a write to the port. Intel (R) ICH7 Family Datasheet 391 LPC Interface Bridge Registers (D31:F0) 10.2.11 DMA_WRMSK--DMA Write All Mask Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:4 Reserved. Must be 0. Channel Mask Bits -- R/W. This register permits all four channels to be simultaneously enabled/disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register - Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal count (unless the channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status. Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked NOTE: Disabling channel 4 also disables channels 0-3 due to the cascade of channel's 0 - 3 through channel 4. Ch. #0-3 = 0Fh; Ch. #4-7 = DEh 0000 1111 No Attribute: Size: Power Well: Description R/W 8-bit Core 3:0 10.3 Timer I/O Registers (LPC I/F--D31:F0) Port 40h Aliases 50h Register Name Counter 0 Interval Time Status Byte Format Counter 0 Counter Access Port 41h 51h Counter 1 Interval Time Status Byte Format Counter 1 Counter Access Port 42h 52h Counter 2 Interval Time Status Byte Format Counter 2 Counter Access Port Timer Control Word 43h 53h Timer Control Word Register Counter Latch Command Default Value 0XXXXXXXb Undefined 0XXXXXXXb Undefined 0XXXXXXXb Undefined Undefined XXXXXXX0b X0h Type RO R/W RO R/W RO R/W WO WO WO 392 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.3.1 TCW--Timer Control Word Register (LPC I/F--D31:F0) I/O Address: Default Value: 43h All bits undefined Attribute: Size: WO 8 bits This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state. Bit Description Counter Select -- WO. The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1. 7:6 00 = Counter 0 select 01 = Counter 1 select 10 = Counter 2 select 11 = Read Back Command Read/Write Select -- WO. These bits are the read/write control bits. The actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 5:4 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB Counter Mode Selection -- WO. These bits select one of six possible modes of operation for the selected counter. Bit Value 000b 3:1 001b x10b x11b 100b 101b Mode Mode 0 Out signal on end of count (=0) Mode 1 Hardware retriggerable oneshot Mode 2 Rate generator (divide by n counter) Mode 3 Square wave output Mode 4 Software triggered strobe Mode 5 Hardware triggered strobe Binary/BCD Countdown Select -- WO. 0 0 = Binary countdown is used. The largest possible binary count is 216 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104 There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined. These register formats are described below: RDBK_CMD--Read Back Command (LPC I/F--D31:F0) The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write. The count and status remain latched until read, and further latch commands are ignored until the count is read. Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 Intel (R) ICH7 Family Datasheet 393 LPC Interface Bridge Registers (D31:F0) to 0. If both are latched, the first read operation from that counter returns the latched status. The next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent reads return an unlatched count. Bit 7:6 5 Description Read Back Command. Must be 11 to select the Read Back Command Latch Count of Selected Counters. 0 = Current count value of the selected counters will be latched 1 = Current count will not be latched Latch Status of Selected Counters. 4 0 = Status of the selected counters will be latched 1 = Status will not be latched Counter 2 Select. 1 = Counter 2 count and/or status will be latched Counter 1 Select. 1 = Counter 1 count and/or status will be latched Counter 0 Select. 1 = Counter 0 count and/or status will be latched. Reserved. Must be 0. 3 2 1 0 LTCH_CMD--Counter Latch Command (LPC I/F--D31:F0) The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read according to the programmed format, i.e., if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored. Bit Description Counter Selection. These bits select the counter for latching. If "11" is written, then the write is interpreted as a read back command. 7:6 00 = Counter 0 01 = Counter 1 10 = Counter 2 5:4 3:0 Counter Latch Command. 00 = Selects the Counter Latch Command. Reserved. Must be 0. 394 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.3.2 SBYTE_FMT--Interval Timer Status Byte Format Register (LPC I/F--D31:F0) I/O Address: Default Value: Counter 0 = 40h, Counter 1 = 41h, Counter 2 = 42h Bits[6:0] undefined, Bit 7=0 Attribute: Size: RO 8 bits per counter Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following: Bit Counter OUT Pin State -- RO. 7 0 = OUT pin of the counter is also a 0 1 = OUT pin of the counter is also a 1 Count Register Status -- RO. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. 0 = Count has been transferred from CR to CE and is available for reading. 1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading. Read/Write Selection Status -- RO. These bits reflect the read/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. 5:4 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB Mode Selection Status -- RO. These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = Mode 0 -- Out signal on end of count (=0) 3:1 001 = Mode 1 -- Hardware retriggerable one-shot x10 = Mode 2 -- Rate generator (divide by n counter) x11 = Mode 3 -- Square wave output 100 = Mode 4 -- Software triggered strobe 101 = Mode 5 -- Hardware triggered strobe Countdown Type Status -- RO. This bit reflects the current countdown type. 0 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown. Description 6 Intel (R) ICH7 Family Datasheet 395 LPC Interface Bridge Registers (D31:F0) 10.3.3 Counter Access Ports Register (LPC I/F--D31:F0) I/O Address: Default Value: Bit Counter 0 - 40h, Counter 1 - 41h, Counter 2 - 42h All bits undefined Attribute: Size: Description R/W 8 bit 7:0 Counter Port -- R/W. Each counter port address is used to program the 16-bit Count Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval Counter Control Register at port 43h. The counter port is also used to read the current count from the Count Register, and return the status of the counter programming following a Read Back Command. 10.4 10.4.1 8259 Interrupt Controller (PIC) Registers (LPC I/F--D31:F0) Interrupt Controller I/O MAP (LPC I/F--D31:F0) The interrupt controller registers are located at 20h and 21h for the master controller (IRQ 0-7), and at A0h and A1h for the slave controller (IRQ 8-13). These registers have multiple functions, depending upon the data written to them. Table 10-3 shows the different register possibilities for each address. Table 10-3. PIC Registers (LPC I/F--D31:F0) Port Aliases 24h, 28h, 20h 2Ch, 30h, 34h, 38h, 3Ch 25h, 29h, 21h 2Dh, 31h, 35h, 39h, 3Dh A4h, A8h, A0h ACh, B0h, B4h, B8h, BCh A5h, A9h, A1h ADh, B1h, B5h, B9h, BDh - - Register Name Master PIC ICW1 Init. Cmd Word 1 Master PIC OCW2 Op Ctrl Word 2 Master PIC OCW3 Op Ctrl Word 3 Master PIC ICW2 Init. Cmd Word 2 Master PIC ICW3 Init. Cmd Word 3 Master PIC ICW4 Init. Cmd Word 4 Master PIC OCW1 Op Ctrl Word 1 Slave PIC ICW1 Init. Cmd Word 1 Slave PIC OCW2 Op Ctrl Word 2 Slave PIC OCW3 Op Ctrl Word 3 Slave PIC ICW2 Init. Cmd Word 2 Slave PIC ICW3 Init. Cmd Word 3 Slave PIC ICW4 Init. Cmd Word 4 Slave PIC OCW1 Op Ctrl Word 1 Master PIC Edge/Level Triggered Slave PIC Edge/Level Triggered Default Value Undefined 001XXXXXb X01XXX10b Undefined Undefined 01h 00h Undefined 001XXXXXb X01XXX10b Undefined Undefined 01h 00h 00h 00h Type WO WO WO WO WO WO R/W WO WO WO WO WO WO R/W R/W R/W 4D0h 4D1h Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers section (Chapter 5.9). 396 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.4.2 ICW1--Initialization Command Word 1 Register (LPC I/F--D31:F0) Offset Address: Master Controller - 20h Slave Controller - A0h Default Value: All bits undefined Attribute: Size: WO 8 bit /controller A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. The Interrupt Mask register is cleared. 2. IRQ7 input is assigned priority 7. 3. The slave mode address is set to 7. 4. Special mask mode is cleared and Status Read is set to IRR. Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence. Bit 7:5 Description ICW/OCW Select -- WO. These bits are MCS-85 specific, and not needed. 000 = Should be programmed to "000" ICW/OCW Select -- WO. 4 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence. Edge/Level Bank Select (LTIM) -- WO. Disabled. Replaced by the edge/level triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h). ADI -- WO. 0 = Ignored for the Intel(R) ICH7. Should be programmed to 0. Single or Cascade (SNGL) -- WO. 0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode. ICW4 Write Required (IC4) -- WO. 0 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed. 3 2 1 Intel (R) ICH7 Family Datasheet 397 LPC Interface Bridge Registers (D31:F0) 10.4.3 ICW2--Initialization Command Word 2 Register (LPC I/F--D31:F0) Offset Address: Master Controller - 21h Slave Controller - A1h Default Value: All bits undefined Attribute: Size: WO 8 bit /controller ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller. Bit 7:3 Description Interrupt Vector Base Address -- WO. Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. Interrupt Request Level -- WO. When writing ICW2, these bits should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: Code 2:0 000b 001b 010b 011b 100b 101b 110b 111b Master Interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Slave Interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 10.4.4 ICW3--Master Controller Initialization Command Word 3 Register (LPC I/F--D31:F0) Offset Address: 21h Default Value: All bits undefined Bit 7:3 Attribute: Size: Description WO 8 bits 0 = These bits must be programmed to 0. Cascaded Interrupt Controller IRQ Connection -- WO. This bit indicates that the slave controller is cascaded on IRQ2. When IRQ8#-IRQ15 is asserted, it goes through the slave controller's priority resolver. The slave controller's INTR output onto IRQ2. IRQ2 then goes through the master controller's priority solver. If it wins, the INTR signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = This bit must always be programmed to a 1. 0 = These bits must be programmed to 0. 2 1:0 398 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.4.5 ICW3--Slave Controller Initialization Command Word 3 Register (LPC I/F--D31:F0) Offset Address: A1h Default Value: All bits undefined Bit 7:3 Attribute: Size: Description WO 8 bits 0 = These bits must be programmed to 0. Slave Identification Code -- WO. These bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. 2:0 10.4.6 ICW4--Initialization Command Word 4 Register (LPC I/F--D31:F0) Offset Address: Master Controller - 021h Slave Controller - 0A1h Default Value: 01h Bit 7:5 4 Attribute: Size: WO 8 bits Description 0 = These bits must be programmed to 0. Special Fully Nested Mode (SFNM) -- WO. 0 = Should normally be disabled by writing a 0 to this bit. 1 = Special fully nested mode is programmed. Buffered Mode (BUF) -- WO. 0 = Must be programmed to 0 for the Intel(R) ICH7. This is non-buffered mode. Master/Slave in Buffered Mode -- WO. Not used. 0 = Should always be programmed to 0. Automatic End of Interrupt (AEOI) -- WO. 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. Microprocessor Mode -- WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-based system. 3 2 1 0 Intel (R) ICH7 Family Datasheet 399 LPC Interface Bridge Registers (D31:F0) 10.4.7 OCW1--Operational Control Word 1 (Interrupt Mask) Register (LPC I/F--D31:F0) Offset Address: Master Controller - 021h Slave Controller - 0A1h Default Value: 00h Bit Attribute: Size: R/W 8 bits Description Interrupt Request Mask -- R/W. When a 1 is written to any bit in this register, the corresponding IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller. 7:0 10.4.8 OCW2--Operational Control Word 2 Register (LPC I/F--D31:F0) Offset Address: Master Controller - 020h Attribute: Slave Controller - 0A0h Size: Default Value: Bit[4:0]=undefined, Bit[7:5]=001 WO 8 bits Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization. Bit Description Rotate and EOI Codes (R, SL, EOI) -- WO. These three bits control the Rotate and End of Interrupt modes and combinations of the two. 000 = Rotate in Auto EOI Mode (Clear) 001 = Non-specific EOI command 010 = No Operation 7:5 011 = *Specific EOI Command 100 = Rotate in Auto EOI Mode (Set) 101 = Rotate on Non-Specific EOI Command 110 = *Set Priority Command 111 = *Rotate on Specific EOI Command *L0 - L2 Are Used 4:3 OCW2 Select -- WO. When selecting OCW2, bits 4:3 = "00" Interrupt Level Select (L2, L1, L0) -- WO. L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined below, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. 2:0 Code 000b 001b 010b 011b Interrupt Level IRQ0/8 IRQ1/9 IRQ2/10 IRQ3/11 Code 000b 001b 010b 011b Interrupt Level IRQ4/12 IRQ5/13 IRQ6/14 IRQ7/15 400 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.4.9 OCW3--Operational Control Word 3 Register (LPC I/F--D31:F0) Offset Address: Master Controller - 020h Attribute: Slave Controller - 0A0h Size: Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1 Bit 7 Reserved. Must be 0. Special Mask Mode (SMM) -- WO. 1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning. Enable Special Mask Mode (ESMM) -- WO. 5 4:3 0 = Disable. The SMM bit becomes a "don't care". 1 = Enable the SMM bit to set or reset the Special Mask Mode. OCW3 Select -- WO. When selecting OCW3, bits 4:3 = 01 Poll Mode Command -- WO. 2 0 = Disable. Poll Command is not issued. 1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle. An encoded byte is driven onto the data bus, representing the highest priority level requesting service. Register Read Command -- WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be "read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when programming this register. The selected register can be read repeatedly without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register Description WO 8 bits 6 1:0 Intel (R) ICH7 Family Datasheet 401 LPC Interface Bridge Registers (D31:F0) 10.4.10 ELCR1--Master Controller Edge/Level Triggered Register (LPC I/F--D31:F0) Offset Address: 4D0h Default Value: 00h Attribute: Size: R/W 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode. Bit IRQ7 ECL -- R/W. 7 0 = Edge. 1 = Level. IRQ6 ECL -- R/W. 6 0 = Edge. 1 = Level. IRQ5 ECL -- R/W. 5 0 = Edge. 1 = Level. IRQ4 ECL -- R/W. 4 0 = Edge. 1 = Level. IRQ3 ECL -- R/W. 3 2:0 0 = Edge. 1 = Level. Reserved. Must be 0. Description 402 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.4.11 ELCR2--Slave Controller Edge/Level Triggered Register (LPC I/F--D31:F0) Offset Address: 4D1h Default Value: 00h Attribute: Size: R/W 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level mode. Bit IRQ15 ECL -- R/W. 7 0 = Edge 1 = Level IRQ14 ECL -- R/W. 6 5 4 0 = Edge 1 = Level Reserved. Must be 0. IRQ12 ECL -- R/W. 0 = Edge 1 = Level IRQ11 ECL -- R/W. 3 0 = Edge 1 = Level IRQ10 ECL -- R/W. 2 0 = Edge 1 = Level IRQ9 ECL -- R/W. 1 0 0 = Edge 1 = Level Reserved. Must be 0. Description Intel (R) ICH7 Family Datasheet 403 LPC Interface Bridge Registers (D31:F0) 10.5 10.5.1 Advanced Programmable Interrupt Controller (APIC)(D31:F0) APIC Register Map (LPC I/F--D31:F0) The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space. The registers are shown in Table 10-4. Table 10-4. APIC Direct Registers (LPC I/F--D31:F0) Address FEC0_0000h FEC0_0010h FECO_0040h Mnemoni c IND DAT EOIR Index Data EOI Register Name Size 8 bits 32 bits 32 bits Type R/W R/W WO Table 10-5 lists the registers which can be accessed within the APIC via the Index Register. When accessing these registers, accesses must be done one DWord at a time. For example, software should not access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not attempt to recover from a bad programming model in this case. Table 10-5. APIC Indirect Registers (LPC I/F--D31:F0) Index 00 01 02-0F 10-11 12-13 ... 3E-3F 40-FF Mnemonic ID VER -- REDIR_TBL0 REDIR_TBL1 ... REDIR_TBL23 -- Register Name Identification Version Reserved Redirection Table 0 Redirection Table 1 ... Redirection Table 23 Reserved Size 32 bits 32 bits -- 64 bits 64 bits ... 64 bits -- Type R/W RO RO R/W, RO R/W, RO ... R/W, RO RO 10.5.2 IND--Index Register (LPC I/F--D31:F0) Memory Address FEC0_0000h Default Value: 00h Attribute: Size: R/W 8 bits The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 10-5. Software will program this register to select the desired APIC internal register . Bit 7:0 Description APIC Index -- R/W. This is an 8-bit pointer into the I/O APIC register table. 404 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.5.3 DAT--Data Register (LPC I/F--D31:F0) Memory Address FEC0_0010h Default Value: 00000000h Attribute: Size: R/W 32 bits This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in DWord quantities. Bit 7:0 Description APIC Data -- R/W. This is a 32-bit register for the data to be read or written to the APIC indirect register (Figure 10-5) pointed to by the Index register (Memory Address FEC0_0000h). 10.5.4 EOIR--EOI Register (LPC I/F--D31:F0) Memory Address FEC0h_0040h Default Value: N/A Attribute: Size: WO 32 bits The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will be cleared. Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which was prematurely reset will not be lost because if its input remained active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the ICH7. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Bit 31:8 Description Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Redirection Entry Clear -- WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared. Note: 7:0 Intel (R) ICH7 Family Datasheet 405 LPC Interface Bridge Registers (D31:F0) 10.5.5 ID--Identification Register (LPC I/F--D31:F0) Index Offset: Default Value: 00h 00000000h Attribute: Size: R/W 32 bits The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset. Bit 31:28 27:24 23:16 15 14:0 Reserved APIC ID -- R/W. Software must program this value before using the APIC. Reserved Scratchpad Bit. Reserved Description 10.5.6 VER--Version Register (LPC I/F--D31:F0) Index Offset: Default Value: 01h 00170020h Attribute: Size: RO 32 bits Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this APIC. Bit 31:24 Reserved Maximum Redirection Entries -- RO. This field is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range 0 through 239. In the Intel(R) ICH7 this field is hardwired to 17h to indicate 24 interrupts. PRQ -- RO. This bit indicate that the IOxAPIC does not implement the Pin Assertion Register. Reserved Version -- RO. This is a version number that identifies the implementation version. Description 23:16 15 14:8 7:0 406 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.5.7 REDIR_TBL--Redirection Table (LPC I/F--D31:F0) Index Offset: Default Value: 10h-11h (vector 0) through 3E-3Fh (vector 23) Bit 16 = 1,. All other bits undefined Attribute:R/W, RO Size: 64 bits each, (accessed as two 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC unit that the interrupt message was sent. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the destination.) Bit Description Destination -- R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In this case, bits 63:59 should be programmed by software to 0. If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of processors. Extended Destination ID (EDID) -- RO. These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address. Reserved Mask -- R/W. 0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device withdrawing the interrupt before it is posted to the processor. It is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. Trigger Mode -- R/W. This field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = Edge triggered. 1 = Level triggered. Remote IRR -- R/W. This bit is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received from a local APIC. 1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC. Interrupt Input Pin Polarity -- R/W. This bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = Active high. 1 = Active low. Delivery Status -- RO. This field contains the current status of the delivery of this interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. 1 = Pending. Interrupt has been injected, but delivery is not complete. 63:56 55:48 47:17 16 15 14 13 12 Intel (R) ICH7 Family Datasheet 407 LPC Interface Bridge Registers (D31:F0) Bit Description Destination Mode -- R/W. This field determines the interpretation of the Destination field. 11 0 = Physical. Destination APIC ID is identified by bits 59:56. 1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC. Delivery Mode -- R/W. This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are listed in the note below: Vector -- R/W. This field contains the interrupt vector for this interrupt. Values range between 10h and FEh. 10:8 7:0 NOTE: Delivery Mode encoding: 000 = 001 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode can be edge or level. Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all 0's for future compatibility: not supported Reserved NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be sent again: not supported INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt even if programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The INIT delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is reached again, the interrupt will be sent again: not supported Reserved ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is expected to supply the vector. Requires the interrupt to be programmed as edge triggered. 010 = 011 = 100 = 101 = 110 = 111 = 408 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.6 10.6.1 Real Time Clock Registers (LPC I/F--D31:F0) I/O Register Address Map (LPC I/F--D31:F0) The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A-D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed SRAM, and will be accessible even when the RTC module is disabled (via the RTC configuration register). Registers A-D do not physically exist in the RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 10-6. Table 10-6. RTC I/O Registers (LPC I/F--D31:F0) I/O Locations 70h and 74h 71h and 75h 72h and 76h 73h and 77h NOTES: If U128E bit = 0 Also alias to 72h and 76h Also alias to 73h and 77h Function Real-Time Clock (Standard RAM) Index Register Real-Time Clock (Standard RAM) Target Register Extended RAM Index Register (if enabled) Extended RAM Target Register (if enabled) 1. I/O locations 70h and 71h are the standard legacy location for the real-time clock. The map for this bank is shown in Table 10-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. Note that port 70h is not directly readable. The only way to read this register is through Alt Access mode. Although RTC Index bits 6:0 are readable from port 74h, bit 7 will always return 0. If the NMI# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. Intel (R) ICH7 Family Datasheet 409 LPC Interface Bridge Registers (D31:F0) 10.6.2 Indexed Registers (LPC I/F--D31:F0) The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70/71h or 72/73h), as shown in Table 10-7. Table 10-7. RTC (Standard) RAM Bank (LPC I/F--D31:F0) Index 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh-7Fh Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day of Week Day of Month Month Year Register A Register B Register C Register D 114 Bytes of User RAM Name 410 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.6.2.1 RTC_REGA--Register A (LPC I/F--D31:F0) RTC Index: Default Value: Lockable: 0A Undefined No Attribute: Size: Power Well: R/W 8-bit RTC None of the bits This register is used for general configuration of the RTC functions. are affected by RSMRST# or any other Intel(R) ICH7 reset signal. Bit Description Update In Progress (UIP) -- R/W. This bit may be monitored as a status flag. 7 0 = The update cycle will not start for at least 488 s. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. Division Chain Select (DV[2:0]) -- R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. DV2 corresponds to bit 6. 010 = Normal Operation 6:4 11X = Divider Reset 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid Rate Select (RS[3:0]) -- R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to 0. RS3 corresponds to bit 3. 0000 = Interrupt does not toggle 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 3:0 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms Intel (R) ICH7 Family Datasheet 411 LPC Interface Bridge Registers (D31:F0) 10.6.2.2 RTC_REGB--Register B (General Configuration) (LPC I/F--D31:F0) RTC Index: Default Value: Lockable: Bit 0Bh Attribute: U0U00UUU (U: Undefined) Size: No Power Well: Description R/W 8-bit RTC Update Cycle Inhibit (SET) -- R/W. Enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second. 1 = A current update cycle will abort and subsequent update cycles will not occur until SET is returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely. NOTE: This bit should be set then cleared early in BIOS POST after each powerup directly after coin-cell battery insertion. Periodic Interrupt Enable (PIE) -- R/W. This bit is cleared by RSMRST#, but not on any other reset. 6 0 = Disable. 1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register A. Alarm Interrupt Enable (AIE) -- R/W. This bit is cleared by RTCRST#, but not on any other reset. 5 0 = Disable. 1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or one a month. Update-Ended Interrupt Enable (UIE) -- R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the update cycle ends. Square Wave Enable (SQWE) -- R/W. This bit serves no function in the Intel(R) ICH7. It is left in this register bank to provide compatibility with the Motorola 146818B. The ICH7 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset. 7 4 3 412 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description Data Mode (DM) -- R/W. This bit specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary Hour Format (HOURFORM) -- R/W. This bit indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 2 1 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one. 1 = Twenty-four hour mode. Daylight Savings Enable (DSE) -- R/W. This bit triggers two special hour updates per year. The days for the hour adjustment are those specified in United States federal law as of 1987, which is different than previous years. This bit is not affected by RSMRST# nor any other reset signal. 0 0 = Daylight Savings Time updates do not occur. 1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to 3:00:00 AM. b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it is changed to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly. 10.6.2.3 RTC_REGC--Register C (Flag Register) (LPC I/F--D31:F0) RTC Index: Default Value: Lockable: 0Ch Attribute: 00U00000 (U: Undefined) Size: No Power Well: RO 8-bit RTC Writes to Register C have no effect. Bit 7 Description Interrupt Request Flag (IRQF) -- RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C. Periodic Interrupt Flag (PF) -- RO. This bit is cleared upon RSMRST# or a read of Register C. 6 0 = If no taps are specified via the RS bits in Register A, this flag will not be set. 1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1. Alarm Flag (AF) -- RO. 5 0 = This bit is cleared upon RTCRST# or a read of Register C. 1 = Alarm Flag will be set after all Alarm values match the current time. Update-Ended Flag (UF) -- RO. 4 3:0 0 = The bit is cleared upon RSMRST# or a read of Register C. 1 = Set immediately following an update cycle for each second. Reserved. Will always report 0. Intel (R) ICH7 Family Datasheet 413 LPC Interface Bridge Registers (D31:F0) 10.6.2.4 RTC_REGD--Register D (Flag Register) (LPC I/F--D31:F0) RTC Index: Default Value: Lockable: Bit 0Dh Attribute: 10UUUUUU (U: Undefined) Size: No Power Well: Description R/W 8-bit RTC Valid RAM and Time Bit (VRT) -- R/W. 7 0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = This bit is hardwired to 1 in the RTC power well. Reserved. This bit always returns a 0 and should be set to 0 for write cycles. Date Alarm -- R/W. These bits store the date of month alarm value. If set to 000000b, then a don't care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return 0's to mimic the functionality of the Motorola 146818B. These bits are not affected by any reset assertion. 6 5:0 414 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.7 Processor Interface Registers (LPC I/F--D31:F0) Table 10-8 is the register address map for the processor interface registers. Table 10-8. Processor Interface PCI Register Address Map (LPC I/F--D31:F0) Offset 61h 70h 92h F0h CF9h Mnemonic NMI_SC NMI_EN PORT92 COPROC_ERR RST_CNT Register Name NMI Status and Control NMI Enable Fast A20 and Init Coprocessor Error Reset Control Default 00h 80h 00h 00h 00h Type R/W, RO R/W (special) R/W R/W R/W 10.7.1 NMI_SC--NMI Status and Control Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 61h 00h No Attribute: Size: Power Well: Description R/W, RO 8-bit Core 7 SERR# NMI Source Status (SERR#_NMI_STS) -- RO. 1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0. NOTE: This bit is set by any of the Intel(R) ICH7 internal sources of SERR; this includes SERR assertions forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal functions that generate SERR#. IOCHK# NMI Source Status (IOCHK_NMI_STS) -- RO. 1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3 (IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h, this bit must be a 0. Timer Counter 2 OUT Status (TMR2_OUT_STS) -- RO. This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0. Refresh Cycle Toggle (REF_TOGGLE) -- RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0. IOCHK# NMI Enable (IOCHK_NMI_EN) -- R/W. 0 = Enabled. 1 = Disabled and cleared. 6 5 4 3 Intel (R) ICH7 Family Datasheet 415 LPC Interface Bridge Registers (D31:F0) Bit 2 Description PCI SERR# Enable (PCI_SERR_EN) -- R/W. 0 = SERR# NMIs are enabled. 1 = SERR# NMIs are disabled and cleared. Speaker Data Enable (SPKR_DAT_EN) -- R/W. 0 = SPKR output is a 0. 1 = SPKR output is equivalent to the Counter 2 OUT signal value. Timer Counter 2 Enable (TIM_CNT2_EN) -- R/W. 0 = Disable 1 = Enable 1 0 10.7.2 NMI_EN--NMI Enable (and Real Time Clock Index) Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: 70h 80h No Attribute: Size: Power Well: R/W (special) 8-bit Core Note: The RTC Index field is write-only for normal operation. This field can only be read in AltAccess Mode. Note, however, that this register is aliased to Port 74h (documented in), and all bits are readable at that address. Bits 7 0 = Enable NMI sources. 1 = Disable All NMI sources. Real Time Clock Index Address (RTC_INDX) -- R/W (special). This data goes to the RTC to select which register or CMOS RAM address is being accessed. Description NMI Enable (NMI_EN) -- R/W (special). 6:0 10.7.3 PORT92--Fast A20 and Init Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:2 Reserved Alternate A20 Gate (ALT_A20_GATE) -- R/W. This bit is Or'd with the A20GATE input signal to generate A20M# to the processor. 0 = A20M# signal can potentially go active. 1 = This bit is set when INIT# goes active. INIT_NOW -- R/W. When this bit transitions from a 0 to a 1, the Intel(R) ICH7 will force INIT# active for 16 PCI clocks. 92h 00h No Attribute: Size: Power Well: Description R/W 8-bit Core 1 0 416 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.7.4 COPROC_ERR--Coprocessor Error Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bits F0h 00h No Attribute: Size: Power Well: Description R/W 8-bits Core 7:0 Coprocessor Error (COPROC_ERR) -- R/W. Any value written to this register will cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1. Reads to this register always return 00h. 10.7.5 RST_CNT--Reset Control Register (LPC I/F--D31:F0) I/O Address: Default Value: Lockable: Bit 7:4 Reserved Full Reset (FULL_RST) -- R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with RSMRST# high), or after two TCO timeouts. 3 0 = Intel(R) ICH7 will keep SLP_S3#, SLP_S4# and SLP_S5# high. 1 = ICH7 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 - 5 seconds. NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response to SYSRESET#, PWROK#, and Watchdog timer reset sources. 2 Reset CPU (RST_CPU) -- R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register). System Reset (SYS_RST) -- R/W. This bit is used to determine a hard or soft reset to the processor. 0 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a soft reset by activating INIT# for 16 PCI clocks. 1 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a hard reset by activating PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however the SLP_S3#, SLP_S4# and SLP_S5# will NOT go active. The ICH7 main power well is reset when this bit is 1. It also resets the resume well bits (except for those noted throughout the datasheet). Reserved CF9h 00h No Attribute: Size: Power Well: Description R/W 8-bit Core 1 0 Intel (R) ICH7 Family Datasheet 417 LPC Interface Bridge Registers (D31:F0) 10.8 Power Management Registers (PM--D31:F0) The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved bit, the value should always be 0. Software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 10.8.1 Power Management PCI Configuration Registers (PM--D31:F0) Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0. It includes only those registers dedicated for power management. Some of the registers are only used for Legacy Power management schemes. Table 10-9. Power Management PCI Register Address Map (PM--D31:F0) Offset A0h A2h A4h A9h AAh ABh ADh B0h B1h-B2h B3h B8-BBh Mnemonic GEN_PMCON_1 GEN_PMCON_2 GEN_PMCON_3 Cx-STATE_CNF C4-TIMING_CNT BM_BREAK_EN MSC_FUN EL_STS EL_CNTL1 EL_CNTL2 GPI_ROUT Register Name General Power Management Configuration 1 General Power Management Configuration 2 General Power Management Configuration 3 Cx State Configuration (Mobile/Ultra Mobile Only). C4 Timing Control (Mobile/Ultra Mobile Only). BM_BREAK_EN Miscellaneous Functionality Intel(R) Quick Resume Technology Status Register (Digital Home Only) Intel Quick Resume Technology Control 1 Register (Digital Home Only) Intel Quick Resume Technology Control 2 Register (Digital Home Only) GPI Route Control Default 0000h 00h 00h 00h 00h 00h 00h 00h F000h 00h 0000000 0h Type R/W, RO, R/WO R/W, R/ WC R/W, R/ WC R/W R/W R/W R/W R/WC, RO R/W, RO, WO R/W, RO R/W 418 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.1.1 GEN_PMCON_1--General PM Configuration 1 Register (PM--D31:F0) Offset Address: A0h Default Value: 0000h Lockable: No Attribute: Size: Usage: Power Well: Description Reserved BIOS_PCI_EXP_EN -- R/W. This bit acts as a global enable for the SCI associated with the PCI Express* ports. 0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to go active. 1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to go active. R/W, RO, R/WO 16-bit ACPI, Legacy Core Bit 15:11 10 (Desktop and Mobile Only) 10 (Ultra Mobile Only) 9 8 7 (Desktop Only) 7 (Mobile/ Ultra Mobile Only) 6 Reserved PWRBTN_LVL -- RO. This bit indicates the current state of the PWRBTN# signal. 0 = Low. 1 = High. Reserved Reserved Enter C4 When C3 Invoked (C4onC3_EN) -- R/W. If this bit is set, then when software does a LVL3 read, the Intel(R) ICH7-M/ICH7-U transitions to the C4 state. i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32 processor. This may be used in various state machines where there are behavioral differences. CPU SLP# Enable (CPUSLP_EN) -- R/W. 0 = Disable. 1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor power. 5 (Desktop Only) 5 (Mobile/ Ultra Mobile Only) Reserved 4 SMI_LOCK -- R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by PLTRST#). Reserved 3:2 (Desktop Only) Intel (R) ICH7 Family Datasheet 419 LPC Interface Bridge Registers (D31:F0) Bit 3 (Mobile/ Ultra Mobile Only) Description Intel SpeedStep Enable (SS_EN) -- R/W. 0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be visible (reads to SS_CNT will return 00h and writes will have no effect). 1 = Intel SpeedStep technology logic is enabled. PCI CLKRUN# Enable (CLKRUN_EN) -- R/W. 0 = Disable. Intel(R) ICH7-M/ICH7-U drives the CLKRUN# signal low. 1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI# signals. NOTE: when the SLP_EN# bit is set, the ICH7 drives the CLKRUN# signal low regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue running during a transition to a sleep state. Periodic SMI# Rate Select (PER_SMI_SEL) -- R/W. Set by software to control the rate at which periodic SMI# is generated. 2 (Mobile/ Ultra Mobile Only) 1:0 00 = 1 minute 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds 10.8.1.2 GEN_PMCON_2--General PM Configuration 2 Register (PM--D31:F0) Offset Address: A2h Default Value: 00h Lockable: No Attribute: Size: Usage: Power Well: Description DRAM Initialization Bit -- R/W. This bit does not effect hardware functionality in any way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence. * * If the bit is 1, then the DRAM initialization was interrupted. This bit is reset by the assertion of the RSMRST# pin. R/W, R/WC 8-bit ACPI, Legacy Resume Bit 7 CPU PLL Lock Time (CPLT) -- R/W. This field indicates the amount of time that the processor needs to lock its PLLs. This is used wherever timing t270 (Chapter 23) applies. 00 01 10 11 = = = = min min min min 30.7 s (Default) 61.4 s 122.8 s 245.6 s 6:5 It is the responsibility of the BIOS to program the correct value in this field prior to the first transition to C3 or C4 states (or performing Intel SpeedStep(R) technology transitions). NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to these bits. NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write 420 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description System Reset Status (SRS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = SYS_RESET# button Not pressed. 1 = ICH7 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit and clear it, if it is set. NOTE: This bit is also reset by RSMRST# and CF9h resets. CPU Thermal Trip Status (CTS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an S0 or S1 state. 4 3 NOTES: 1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and reboot associated with the CPUTHRMTRIP# event. 2. The CF9h reset in the description refers to CF9h type core well reset which includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout. This type of reset will clear CTS bit. Minimum SLP_S4# Assertion Width Violation Status -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The ICH7 begins the timer when SLP_S4# is asserted during S4/S5 entry, or when the RSMRST# input is deasserted during G3 exit. Note that this bit is functional regardless of the value in the SLP_S4# Assertion Stretch Enable (D31:F0:Offset A4h:bit 3). NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before the default value is readable. CPU Power Failure (CPUPWR_FLR) -- R/WC. 0 = Software (typically BIOS) clears this bit by writing a 0 to it. 1 = Indicates that the VRMPWRGD signal from the processor's VRM went low while the system was in an S0 or S1 state. NOTE: VRMPWRGD is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH7. PWROK Failure (PWROK_FLR) -- R/WC. 0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state. 1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. The bit will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state. NOTE: See Chapter 5.14.11.3 for more details about the PWROK pin functionality. NOTE: In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD. 2 1 0 NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH7. Intel (R) ICH7 Family Datasheet 421 LPC Interface Bridge Registers (D31:F0) 10.8.1.3 GEN_PMCON_3--General PM Configuration 3 Register (PM--D31:F0) Offset Address: A4h Default Value: 00h Lockable: No Attribute: Size: Usage: Power Well: Description SWSMI_RATE_SEL -- R/W. This field indicates when the SWSMI timer will time out. Valid values are: 7:6 00 01 10 11 = = = = 1.5 ms 0.6 ms 16 ms 4 ms 32 ms 4 ms 64 ms 4 ms R/W, R/WC 8-bit ACPI, Legacy RTC Bit These bits are not cleared by any type of reset except RTCRST#. SLP_S4# Minimum Assertion Width -- R/W. This field indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely power-cycled. Valid values are: 11 10 01 00 = = = = 1 2 3 4 to to to to 2 3 4 5 seconds seconds seconds seconds 5:4 This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read when S0 is entered. 2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from deasserting within this minimum time period after asserting. RTCRST# forces this field to the conservative default state (00b) SLP_S4# Assertion Stretch Enable -- R/W. 3 0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK. 1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register. This bit is cleared by RTCRST# 422 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit 2 Description RTC Power Status (RTC_PWR_STS) -- R/W. This bit is set when RTCRST# indicates a weak or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the software clears it by writing a 0 back to this bit position. Power Failure (PWR_FLR) -- R/WC. This bit is in the RTC well, and is not cleared by any type of reset except RTCRST#. 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software clears this bit by writing a 1 to it. 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. AFTERG3_EN -- R/W. This bit determines what state to go to when power is re-applied after a power failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except writes to CF9h or RTCRST#. 1 0 0 = System will return to S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure. NOTE: Bit will be set when THRMTRIP#-based shutdown occurs. NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the ICH7. Intel (R) ICH7 Family Datasheet 423 LPC Interface Bridge Registers (D31:F0) 10.8.1.4 Cx-STATE_CNF--Cx State Configuration Register (PM--D31:F0) (Mobile/Ultra Mobile Only) Offset Address: Default Value: Lockable: Power Well: A9h 00h No Core Attribute: Size: Usage: R/W 8-bit ACPI, Legacy This register is used to enable new C-state related modes. Bit 7 6:5 SCRATCHPAD (SP) -- R/W. Reserved Popdown Mode Enable (PDME) -- R/W. This bit is used in conjunction with the PUME bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0. 0 = The Intel(R) ICH7-M/ICH7-U will not attempt to automatically return to a previous C3 or C4 state. 1 = When this bit is a 1 and ICH7-M/ICH7-U observes that there are no bus master requests, it can return to a previous C3 or C4 state. NOTE: This bit is separate from the PUME bit to cover cases where latency issues permit POPUP but not POPDOWN. Popup Mode Enable (PUME) -- R/W. When this bit is a 0, the ICH7-M/ICH7-U behaves like ICH5, in that bus master traffic is a break event, and it will return from C3/C4 to C0 based on a break event. See Chapter 5.14.5 for additional details on this mode. 3 0 = The ICH7 will treat Bus master traffic a break event, and will return from C3/C4 to C0 based on a break event. 1 = When this bit is a 1 and ICH7 observes a bus master request, it will take the system from a C3 or C4 state to a C2 state and auto enable bus masters. This will let snoops and memory access occur. Report Zero for BM_STS (BM_STS_ZERO_EN) -- R/W. 0 = The ICH7 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from PCI, PCI Express* and internal bus masters. 1 = When this bit is a 1, ICH7 will not set the BM_STS if there is bus master activity from PCI, PCI Express and internal bus masters. 2 NOTES: 1. If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the BM_STS bit will remain set. Software will still need to clear the BM_STS bit. 2. It is expected that if the PUME bit (this register, bit 3) is set, the BM_STS_ZERO_EN bit should also be set. Setting one without the other would mainly be for debug or errata workaround. 3. BM_STS will be set by LPC DMA (Mobile Only) or LPC masters, even if BM_STS_ZERO_EN is set. Reserved Description 4 1:0 424 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.1.5 C4-TIMING_CNT--C4 Timing Control Register (PM--D31:F0) (Mobile/Ultra Mobile Only) Offset Address: Default Value: Lockable: Power Well: AAh 00h No Core Attribute: Size: Usage: R/W 8-bit ACPI, Legacy This register is used to enable C-state related modes. Bit 7:4 Reserved DPRSLPVR to STPCPU -- R/W. This field selects the amount of time that the Intel(R) ICH7-M/ICH7-U waits for from the deassertion of DPRSLPVR to the deassertion of STP_CPU#. This provides a programmable time for the processor's voltage to stabilize when exiting from a C4 state. This changes the value for t266. 3:2 Bits 00b 01b 10b 11b t266min 95 s 22 s 34 s t266max 101 s 28 s 40 s Comment Default Value used for "Fast" VRMs Recommended Value Reserved Description DPSLP-TO-SLP -- R/W. This field selects the DPSLP# deassertion to CPU_SLP# deassertion time (t270). Normally this value is determined by the CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero, then the values in this register have higher priority. It is software's responsibility to program these fields in a consistent manner. 1:0 Bits 00b 01b 10b 11b t270 Use value in CPU_PLL_LOCK_TIME field (default is 30 s) 20 s 15 s (Recommended Value) 10 s Intel (R) ICH7 Family Datasheet 425 LPC Interface Bridge Registers (D31:F0) 10.8.1.6 BM_BREAK_EN Register (PM--D31:F0) (Mobile/Ultra Mobile Only) Offset Address: Default Value: Lockable: Power Well: Bit IDE_BREAK_EN -- R/W. 7 0 = Parallel IDE or Serial ATA traffic will not act as a break event. 1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STSZERO_EN and POPUP_EN bits are set. Parallel IDE or Serial ATA master activity will cause BM_STS to be set and will cause a break from C3/C4. PCIE_BREAK_EN -- R/W. 6 (Mobile Only) 6 (Ultra Mobile Only) 0 = PCI Express* traffic will not act as a break event. 1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set and will cause a break from C3/C4. ABh 00h No Core Attribute: Size: Usage: R/W 8-bit ACPI, Legacy Description Reserved PCI_BREAK_EN -- R/W. 5 0 = PCI traffic will not act as a break event. 1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. PCI master activity will cause BM_STS to be set and will cause a break from C3/C4. Reserved EHCI_BREAK_EN -- R/W. 2 0 = EHCI traffic will not act as a break event. 1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. EHCI master activity will cause BM_STS to be set and will cause a break from C3/C4. UHCI_BREAK_EN -- R/W. 1 0 = UHCI traffic will not act as a break event. 1 = USB traffic from any of the internal UHCIs acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause BM_STS to be set and will cause a break from C3/C4. ACAZ_BREAK_EN -- R/W. 0 = AC `97 or Intel(R) High Definition Audio traffic will not act as a break event. 1 = AC `97 or Intel High Definition Audio traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set. AC `97 or Intel High Definition Audio master activity will cause BM_STS to be set and will cause a break from C3/C4. NOTE: For ICH7-U Ultra Mobile, only Intel High Definition is supported, AC `97 is not supported. 4:3 0 426 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.1.7 MSC_FUN--Miscellaneous Functionality Register (PM--D31:F0) Offset Address: ADh Default Value: 00h Power Well: Resume Bit 7:2 1:0 Reserved USB Transient Disconnect Detect (TDD) -- R/W: This field prevents a short SingleEnded Zero (SE0) condition on the USB ports from being interpreted by the UHCI host controller as a disconnect. BIOS should set to 11b. Attribute: Size: R/W 8-bit Description 10.8.1.8 EL_STS--Intel(R) Quick Resume Technology Status Register (PM-- D31:F0) (ICH7DH Only) Offset Address: B0h Default Value: 00h Power Well: Resume Bit 7:5 Reserved EL_SCI_NOW_STS-- R/WC: This bit goes active when software writes a 1 to EL_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the Intel Quick Resume Technology (QRT) software to transition the reaction to an Intel QRT event from an SMI# handler to an SCI handler. This bit remains set until a 1 is written to this bit position. Once a 1 is written to this bit position, the logic will "re-arm" to allow the bit to be set on the next write of 1 to SCI_NOW_CNT (Offset B1h:Bit 8). EL_PB_SCI_STS -- R/WC: This bit goes active when the PWRBTN# pin goes from high-to-low (post-debounce). It can be enabled to cause an SCI that will allow the Intel QRT software to see when the power button has been pressed. It is a separate bit from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any indication to other (i.e. Intel QRT) software. The Intel QRT software clears EL_PB_SCI_STS by writing a 1 to this bit position. 2 Reserved EL_PB_SMI_STS -- R/WC: This bit goes active when the PWRBTN# pin goes from high-to-low (post-debounce). It can be enabled to cause an SMI# that will allow the Intel QRT software to see when the power button has been pressed. It is a separate bit from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any indication to other (i.e., Intel QRT) software. The Intel QRT software clears EL_PB_SMI_STS by writing a 1 to this bit position. 0 Reserved. Attribute: Size: R/WC, RO 8-bit Description 4 3 1 Intel (R) ICH7 Family Datasheet 427 LPC Interface Bridge Registers (D31:F0) 10.8.1.9 EL_CNT1--Intel(R) Quick Resume Technology Control 1 Register (PM-- D31:F0) (ICH7DH Only) Offset Address: B1h-B2h Default Value: F000h Power Well: Resume Bit 15:10 Reserved SMI_OPTION_CNT--R/W: 9 0 = Disable. Platform does Not generate an SMI when an Intel Quick Resume Technology (QRT) event occurs 1 = Enable. Platform generates an SMI when an Intel QRT event occurs (rather than generating an SCI). The SMI handler can cause the SCI by setting the SCI_NOW_CNT. SCI_NOW_CNT--WO: When software writes a 1 to this bit, it causes EL_SCI_NOW_STS (Offset B0:Bit 4) to assert (which can be enabled to cause an SCI). This allows the SMI handler to cause the SCI. PWRBTN_INT_EN--R/W: 0 = Disable. 1 = Enable. The Intel QRT logic is enabled to intercept the power button to cause the Intel QRT SMI or SCI, and not immediately setting the PWRBTN_STS bit. The Intel QRT software will later set the PWRBTN_STS bit by setting the PWRBTN_EVNT bit. NOTE: This bit is effective only in S0. PWRBTN_EVNT--WO: When this bit is set to 1 by software, the PWRBTN_STS bit is set to 1. This allows software to communicate PWR_BTN event to OS. 6 NOTES: 1. Power Button override still possible 2. Software does not need to clear this bit, as it is treated as an event EL_STATE1_CNT[1:0]--R/W: These bits controls the EL_STATE1 pin. The EL_STATE[1:0] pins can be used to control a multi color LED to indicate the platform power states to user. If EL_LED_OWN is 0 then these bits have no impact. 5:4 00 = Low 01 = High 10 = Blinking. Note that the blink rate is ~ 1 Hz 11 = Reserved. Software must not set this combination EL_STATE0_CNT[1:0]--R/W: These bits controls the EL_STATE0 pin. The EL_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform power states to user. If EL_LED_OWN is 0 then these bits have no impact. 3:2 00 = Low 01 = High 10 = Blinking. Note that the blink rate is ~ 1 Hz 11 = Reserved. Software must not set this combination 1 0 EL_LED_OWN--R/W: Software sets this bit to 1 to configure the multiplexed pins to be EL_STATE[1:0] rather than GPIO[28:27]. Reserved Attribute: Size: R/W, RO, WO 16-bit Description 8 7 428 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.1.10 EL_CNT2--Intel(R) Quick Resume Technology Control 2 Register (PM-- D31:F0) (ICH7DH Only) Offset Address: B3h Default Value: 00h Power Well: RTC Bit 7:1 Reserved Intel Quick Resume Technology Enable (EL_EN)--R/W: This bit enables Intel Quick Resume Technology. 0 0 = Disabled 1 = Enabled When this bit is 0, the R/W bits of Intel Quick Resume Technology Control Registers (EL_CNT1, EL_CNT2) scratchpad with no effect on hardware functions. Also, WO bits have no effect on hardware functions. BIOS software is expected to set this bit after booting. Default value for this bit is 0. Attribute: Size: R/W, RO 8-bit Description 10.8.1.11 GPIO_ROUT--GPIO Routing Control Register (PM--D31:F0) Offset Address: B8h - BBh Default Value: 00000000h Lockable: No Bit 31:30 Attribute: Size: Power Well: Description R/W 32-bit Resume GPIO15 Route -- R/W. See bits 1:0 for description. Same pattern for GPIO14 through GPIO3 5:4 3:2 GPIO2 Route -- R/W. See bits 1:0 for description. GPIO1 Route -- R/W. See bits 1:0 for description. GPIO0 Route -- R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect. If the system is in an S1-S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI. 00 = No effect. 01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10 = SCI (if corresponding GPE0_EN bit is also set) 11 = Reserved 1:0 Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register. Intel (R) ICH7 Family Datasheet 429 LPC Interface Bridge Registers (D31:F0) 10.8.2 APM I/O Decode Table 10-10 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location). Table 10-10. APM Register Map Address B2h B3h Mnemonic APM_CNT APM_STS Register Name Advanced Power Management Control Port Advanced Power Management Status Port Default 00h 00h Type R/W R/W 10.8.2.1 APM_CNT--Advanced Power Management Control Port Register I/O Address: Default Value: Lockable: Power Well: Bit 7:0 B2h 00h No Core Attribute: Size: Usage: R/W 8-bit Legacy Only Description Used to pass an APM command between the OS and the SMI handler. Writes to this port not only store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set. 10.8.2.2 APM_STS--Advanced Power Management Status Port Register I/O Address: Default Value: Lockable: Power Well: Bit 7:0 B3h 00h No Core Attribute: Size: Usage: R/W 8-bit Legacy Only Description Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not affected by any other register or function (other than a PCI reset). 430 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3 Power Management I/O Registers Table 10-11 shows the registers associated with ACPI and Legacy power management support. These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers are defined to support the ACPI 2.0 specification, and use the same bit names. Note: All reserved bits and registers will always return 0 when read, and will have no effect when written. Table 10-11. ACPI and Legacy I/O Register Map (Sheet 1 of 2) PMBASE + Offset 00h-01h 02h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-16h 14h 15h 16h 17h-1Fh 20h 20h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-39h 3Ah-3Bh 3Ch-41h 42h 43h 44h-45h 46h-4Fh Mnemonic PM1_STS PM1_EN PM1_CNT PM1_TMR -- PROC_CNT -- LV2 LV3 LV4 -- -- PM2_CNT GPE0_STS GPE0_EN SMI_EN SMI_STS ALT_GP_SMI_EN ALT_GP_SMI_ST S -- GPE_CNTL -- DEVACT_STS -- Register Name PM1 Status PM1 Enable PM1 Control PM1 Timer Reserved Processor Control Reserved (Desktop Only) Level 2 (Mobile/Ultra Mobile Only) Level 3 (Mobile/Ultra Mobile Only) Level 4 (Mobile/Ultra Mobile Only) Reserved Reserved (Desktop Only) PM2 Control (Mobile/ Ultra Mobile Only) General Purpose Event 0 Status General Purpose Event 0 Enables SMI# Control and Enable SMI Status Alternate GPI SMI Enable Alternate GPI SMI Status Reserved General Purpose Event Control Reserved Device Activity Status Reserved -- -- ACPI Pointer PM1a_EVT_BLK PM1a_EVT_BLK+2 PM1a_CNT_BLK PMTMR_BLK -- P_BLK -- P_BLK+4 P_BLK+5 P_BLK+6 -- -- PM2a_CNT_BLK GPE0_BLK GPE0_BLK+4 Default 0000h 0000h 00000000h xx000000h -- 00000000h -- 00h 00h 00h -- -- 00h 00000000h 00000000h 00000000h 00000000h 0000h 0000h -- 00h -- 0000h Type R/WC R/W R/W, WO RO -- R/W, RO, WO -- RO RO RO -- -- R/W R/WC R/W R/W, WO, R/W (special) R/WC, RO R/W R/WC -- RO, R/W -- R/WC Intel (R) ICH7 Family Datasheet 431 LPC Interface Bridge Registers (D31:F0) Table 10-11. ACPI and Legacy I/O Register Map (Sheet 2 of 2) PMBASE + Offset 50h Mnemonic -- Register Name Reserved (Desktop Only) Intel SpeedStep(R) Technology Control (Mobile/Ultra Mobile Only) Reserved C3-Residency Register (Mobile/Ultra Mobile Only) Reserved for TCO -- -- -- ACPI Pointer Default Type 50h SS_CNT 01h R/W (special) 51h-5Fh 54h-57h 60h-7Fh -- C3_RES -- -- 00000000h -- -- RO, R/W -- 10.8.3.1 PM1_STS--Power Management 1 Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 00h (ACPI PM1a_EVT_BLK) 0000h No Bits 0-7: Core, Bits 8-15: Resume, except Bit 11 in RTC Attribute: Size: Usage: R/WC 16-bit ACPI or Legacy If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register, then the ICH7 will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the ICH7 will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an SMI# or SCI. 432 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description Wake Status (WAK_STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, the Intel(R) ICH7 will transition the system to the ON state. 15 If the AFTERG3_EN bit is not set and a power failure (such as removed batteries on a mobile/Ultra Mobile platform) occurs without the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will not be set. If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the system will go into an S5 state when power returns, and a subsequent wake event will cause the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a Power Button press, or an enabled wake event that was preserved through the power failure (enable bit in the RTC well). PCI Express Wake Status (PCIEXPWAK_STS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during the write or the PME message received indication has not been cleared in the root port, then the bit will remain active (i.e. all inputs to this bit are levelsensitive). 1 = This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event. This wakeup event can be caused by the PCI Express WAKE# pin being active or receipt of a PCI Express PME message at a root port. This bit is set only when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independent of the state of the PCIEXP_WAKE_DIS bit. NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus, if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. 14 (Desktop and Mobile Only) 14 (Ultra Mobile Only) 13:12 Reserved Reserved Power Button Override Status (PRBTNOR_STS) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a Power Button Override occurs (i.e., the power button is pressed for at least 4 consecutive seconds), or due to the corresponding bit in the SMBus slave message. The power button override causes an unconditional transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this bit is still asserted when the global SCI_EN is set then an SCI will be generated. RTC Status (RTC_STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 11 10 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the RTC_STS bit will generate a wake event. Reserved 9 Intel (R) ICH7 Family Datasheet 433 LPC Interface Bridge Registers (D31:F0) Bit Description Power Button Status (PWRBTN__STS) -- R/WC. This bit is not affected by hard resets caused by a CF9 write. 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position. 1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other enable bit. In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1-S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are both set, a wake event is generated. NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. 8 7:6 Reserved Global Status (GBL _STS) -- R/WC. 0 = The SCI handler should then clear this bit by writing a 1 to the bit location. 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. Reserved Bus Master Status (BM_STS) -- R/WC. This bit will not cause a wake event, SCI or SMI#. 5 4 (Desktop Only) 4 (Mobile/ Ultra Mobile Only) 0 = Software clears this bit by writing a 1 to it. 1 = Set by the Intel(R) ICH7-M/ICH7-U when a bus master requests access to main memory. Bus master activity is detected by any of the PCI Requests being active, any internal bus master request being active, the BM_BUSY# signal being active, or REQ-C2 message received while in C3 or C4 state. NOTES: 1. If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0. LPC DMA (Mobile Only) and bus master activity will always set the BM_STS bit, even if the BM_STS_ZERO_EN bit is set. Reserved Timer Overflow Status (TMROF_STS) -- R/WC. 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location. 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). 3:1 0 434 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.2 PM1_EN--Power Management 1 Enable Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 02h (ACPI PM1a_EVT_BLK + 2) Attribute: 0000h Size: No Usage: Bits 0-7: Core, Bits 8-9, 11-15: Resume, Bit 10: RTC Description Reserved PCI Express Wake Disable(PCIEXPWAK_DIS) -- R/W. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit. 0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake the system. 1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from waking the system. R/W 16-bit ACPI or Legacy Bit 15 14 (Desktop and Mobile Only) 14 (Ultra Mobile Only) 13:11 Reserved Reserved RTC Event Enable (RTC_EN) -- R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override event. 10 0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes active. 1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active. Reserved. Power Button Enable (PWRBTN_EN) -- R/W. This bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by the assertion of the power button. The Power Button is always enabled as a Wake event. 0 = Disable. 1 = Enable. 9 8 7:6 Reserved. Global Enable (GBL_EN) -- R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h, bit 5) are set, an SCI is raised. 0 = Disable. 1 = Enable SCI on GBL_STS going active. Reserved. Timer Overflow Interrupt Enable (TMROF_EN) -- R/W. Works in conjunction with the SCI_EN bit (PMBASE + 04h, bit 0) as described below: TMROF_EN SCI_EN X 0 1 Effect when TMROF_STS is set No SMI# or SCI SMI# SCI 5 4:1 0 0 1 1 Intel (R) ICH7 Family Datasheet 435 LPC Interface Bridge Registers (D31:F0) 10.8.3.3 PM1_CNT--Power Management 1 Control I/O Address: Default Value: Lockable: Power Well: PMBASE + 04h (ACPI PM1a_CNT_BLK) 00000000h No Bits 0-7: Core, Bits 8-12: RTC, Bits 13-15: Resume Attribute: Size: Usage: R/W, WO 32-bit ACPI or Legacy Bit 31:14 13 Reserved. Description Sleep Enable (SLP_EN) -- WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. Sleep Type (SLP_TYP) -- R/W. This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#. Code 000b 001b Master Interrupt ON: Typically maps to S0 state. Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to assert CPUSLP# to put processor in sleep state: Typically, maps to S1 state. Reserved Reserved Reserved Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state. Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4 state. Soft Off Assert SLP S3# SLP S4# and SLP S5#: Typically maps to 12:10 010b 011b 100b 101b 110b 9:3 Reserved. Global Release (GBL_RLS) -- WO. 2 0 = This bit always reads as 0. 1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a corresponding enable and status bits to control its ability to receive ACPI events. Reserved Bus Master Reload (BM_RLD) -- R/W. This bit is treated as a scratchpad bit. This bit is reset to 0 by PLTRST# 0 = Bus master requests will not cause a break from the C3 state. 1 = Enable Bus Master requests (internal, external or BM_BUSY#) to cause a break from the C3 state. If software fails to set this bit before going to C3 state, the Intel(R) ICH7-M/ICH7-U will still return to a snoopable state from C3 or C4 states due to bus master activity. SCI Enable (SCI_EN) -- R/W. Selects the SCI interrupt or the SMI# interrupt for various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. 0 = These events will generate an SMI#. 1 = These events will generate an SCI. 1 (Desktop Only) 1 (Mobile/ Ultra Mobile Only) 0 436 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.4 PM1_TMR--Power Management 1 Timer Register I/O Address: Default Value: Lockable: Power Well: Bit 31:24 Reserved Timer Value (TMR_VAL) -- RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated. PMBASE + 08h (ACPI PMTMR_BLK) xx000000h No Core Attribute: Size: Usage: RO 32-bit ACPI Description 23:0 10.8.3.5 PROC_CNT--Processor Control Register I/O Address: Default Value: Lockable: Power Well: Bit 31:18 Reserved Throttle Status (THTL_STS) -- RO. 17 0 = No clock throttling is occurring (maximum processor performance). 1 = Indicates that the clock state machine is throttling the processor performance. This could be due to the THT_EN bit or the FORCE_THTL bit being set. Reserved Force Thermal Throttling (FORCE_THTL) -- R/W. Software can set this bit to force the thermal throttling function. 8 0 = No forced throttling. 1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no SMI# is generated. PMBASE + 10h (ACPI P_BLK) Attribute: 00000000h Size: No (bits 7:5 are write once)Usage: Core Description R/W, RO, WO 32-bit ACPI or Legacy 16:9 Intel (R) ICH7 Family Datasheet 437 LPC Interface Bridge Registers (D31:F0) Bit Description THRM_DTY -- WO. This write-once field determines the duty cycle of the throttling when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in the C0 state. For mobile/Ultra Mobile only, If in the C2, C3, or C4 state, no throttling occurs. Once the THRM_DTY field is written, any subsequent writes will have no effect until PLTRST# goes active. 7:5 THRM_DTY 000b 001b 010b 011b 100b 101b 110b 111b Throttle Mode 50% (Default) 87.5% 75.0% 62.5% 50% 37.5% 25% 12.5% PCI Clocks 512 896 768 640 512 384 256 128 4 THTL_EN -- R/W. When set and the system is in a C0 state, it enables a processorcontrolled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field. 0 = Disable 1 = Enable THTL_DTY -- R/W. This field determines the duty cycle of the throttling when the THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. THTL_DTY 000b 001b 010b 011b 100b 101b 110b 111b Reserved Throttle Mode 50% (Default) 87.5% 75.0% 62.5% 50% 37.5% 25% 12.5% PCI Clocks 512 896 768 640 512 384 256 128 3:1 0 438 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.6 LV2 -- Level 2 Register (Mobile/Ultra Mobile Only) I/O Address: Default Value: Lockable: Power Well: Bit PMBASE + 14h (ACPI P_BLK+4) 00h No Core Attribute: Size: Usage: RO 8-bit ACPI or Legacy Description Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a "enter a level 2 power state" (C2) to the clock control logic. This will cause the STPCLK# signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or FORCE_THTL) will be ignored. 7:0 NOTE: This register should not be used by Intel(R) iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C2 state when the "read to this register" instruction occurs. 10.8.3.7 LV3--Level 3 Register (Mobile/Ultra Mobile Only) I/O Address: Default Value: Lockable: Bit 7:0 PMBASE + 15h (ACPI P_BLK + 5) Attribute: 00h Size: No Usage: Power Well: Description RO 8-bit ACPI or Legacy Core Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a "enter a C3 power state" to the clock control logic. The C3 state persists until a break event occurs. NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and LVL3 registers (which is not permitted), the Intel(R) ICH7-M/ICH7-U will ignore the LVL3 read, and only perform a C2 transition. NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C3 state when the "read to this register" instruction occurs. 10.8.3.8 LV4--Level 4 Register (Mobile/Ultra Mobile Only) I/O Address: Default Value: Lockable: Bit 7:0 PMBASE + 16h (ACPI P_BLK + 6) Attribute: 00h Size: No Usage: Power Well: Description RO 8-bit ACPI or Legacy Core Reads to this register return all 0s, writes to this register have no effect. Reads to this register generate a "enter a C4 power state" to the clock control logic. The C4 state persists until a break event occurs. NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the C4 state when the "read to this register" instruction occurs. Intel (R) ICH7 Family Datasheet 439 LPC Interface Bridge Registers (D31:F0) 10.8.3.9 PM2_CNT--Power Management 2 Control Register (Mobile/Ultra Mobile Only) I/O Address: Default Value: Lockable: Power Well: Bit 7:1 Reserved Arbiter Disable (ARB_DIS) -- R/W. This bit is a scratchpad bit for legacy software compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state. When a transition to a C3 or C4 state occurs, Intel(R) ICH7-M/ICH7-U will automatically prevent any internal or external non-Isoch bus masters from initiating any cycles up to the (G)MCH. This blocking starts immediately upon the ICH7 sending the Go-C3 message to the (G)MCH. The blocking stops when the Ack-C2 message is received. Note that this is not really blocking, in that messages (such as from PCI Express*) are just queued and held pending. PMBASE + 20h (ACPI PM2_BLK) 00h No Core Attribute: Size: Usage: R/W 8-bit ACPI Description 0 10.8.3.10 GPE0_STS--General Purpose Event 0 Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 28h (ACPI GPE0_BLK) 00000000h No Resume Attribute: Size: Usage: R/WC 32-bit ACPI This register is symmetrical to the General Purpose Event 0 Enable Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit get set, the ICH7 will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the ICH7 will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#. Bit GPIOn_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the corresponding enable bit is set in the GPE0_EN register, then when the GPIO[n]_STS bit is set: * * If the system is in an S1-S5 state, the event will also wake the system. If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI. Description 31:16 NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16 corresponds to GPIO0. 15 Reserved USB4_STS -- R/WC. 14 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set when USB UHCI controller #4 needs to cause a wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit will generate a wake event. 440 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description PME_B0_STS -- R/WC. This bit will be set to 1 by the Intel(R) ICH7 when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be generated. If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. The default for this bit is 0. Writing a 1 to this bit position clears this bit. USB3_STS -- R/WC. 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set when USB UHCI controller #3 needs to cause a wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event. PME_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an SCI will be generated. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. Intel(R) ICH7DH Only: EL_SCI_STS -- R/WC. In Desktop Mode, when Intel Quick Resume Technology feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or EL_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit position. In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit will be treated as Reserved. ICH7 and ICH7R Only: Reserved 13 12 11 10 (Desktop Only) 10 (Mobile/ Ultra Mobile Only) BATLOW_STS -- R/WC. (Mobile/Ultra Mobile Only) Software clears this bit by writing a 1 to it. 0 = BATLOW# Not asserted 1 = Set by hardware when the BATLOW# signal is asserted. Intel (R) ICH7 Family Datasheet 441 LPC Interface Bridge Registers (D31:F0) Bit PCI_EXP_STS -- R/WC. Description 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that: * * The PME event message was received on one or more of the PCI Express* ports (Desktop and Mobile Only) An Assert PMEGPE message received from the (G)MCH via DMI 9 NOTES: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. 3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* Specification, Revision 1.0a. The window for this race condition is approximately 95-105 milliseconds. RI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. SMBus Wake Status (SMB_WAK_STS) -- R/WC. The SMBus controller can independently cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register). Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the ICH7's SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the ICH7's SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. NOTES: 1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be cleared by internal logic when a THRMTRIP# event happens or a Power Button Override event. However, THRMTRIP# or Power Button Override event will not clear SMB_WAK_STS if it is set due to SMBALERT# signal going active. 3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. TCOSCI_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = TOC logic did Not cause SCI. 1 = Set by hardware when the TCO logic causes an SCI. 8 7 6 442 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description AC97_STS -- R/WC. This bit will be set to 1 when the codecs are attempting to wake the system and the PME events for the codecs are armed for wakeup. A PME is armed by programming the appropriate PMEE bit in the Power Management Control and Status register at bit 8 of offset 54h in each AC '97 function. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit gets set only from the following two cases: 1. The PMEE bit for the function is set, and o The AC-link bit clock has been shut and the routed ACZ_SDIN line is high (for audio, if routing is disabled, no wake events are allowed). 2. For modem, if audio routing is disabled, then the wake event is an OR of all ACZ_SDIN lines. If routing is enabled, then the wake event for modem is the remaining non-routed ACZ_SDIN line), or o GPI Status Change Interrupt bit (NABMBAR + 30h, bit 0) is 1. NOTES: 1. This bit is not affected by a hard reset caused by a CF9h write. 2. This bit is also used for Intel(R) High Definition Audio when ICH7 is configured to use the Intel High Definition Audio host controller rather than the AC97 host controller. 3. For ICH7 Ultra Mobile, only Intel High Definition is supported, AC `97 is not supported. USB2_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = USB UHCI controller 2 does Not need to cause a wake. 1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event will be generated if the corresponding USB2_EN bit is set. USB1_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = USB UHCI controller 1 does Not need to cause a wake. 1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be generated if the corresponding USB1_EN bit is set. SWGPE_STS -- R/WC. The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit. HOT_PLUG_STS -- R/WC. 0 = This bit is cleared by writing a 1 to this bit position. 1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the HOT_PLUG_EN bit is set in the GEP0_EN register. 5 4 3 2 1 (Desktop and Mobile Only) 1 (Ultra Mobile Only) Reserved Thermal Interrupt Status (THRM_STS) -- R/WC. Software clears this bit by writing a 1 to it. 0 0 = THRM# signal Not driven active as defined by the THRM_POL bit 1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate a power management event (SCI or SMI#). Intel (R) ICH7 Family Datasheet 443 LPC Interface Bridge Registers (D31:F0) 10.8.3.11 GPE0_EN--General Purpose Event 0 Enables Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 2Ch (ACPI GPE0_BLK + 4) Attribute: 00000000h Size: No Usage: Bits 0-7, 9, 12, 14-31 Resume, Bits 8, 10-11, 13 RTC R/W 32-bit ACPI This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register should be cleared to 0 based on a Power Button Override or processor Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#. Bit Description GPIn_EN -- R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a SCI, and/or wake event. These bits are cleared by RSMRST#. NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16 corresponds to GPIO0. Reserved USB4_EN -- R/W. 14 0 = Disable. 1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event. Break events are handled via the USB interrupt. PME_B0_EN -- R/W. 0 = Disable 1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. PME_B0_STS can be a wake event from the S1-S4 states, or from S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit defaults to 0. NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes. USB3_EN -- R/W. 12 0 = Disable. 1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event. Break events are handled via the USB interrupt. PME_EN -- R/W. 11 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1 - S4 state or from S5 (if entered via SLP_EN, but not power button override). ICH7DH Only: 10 (Desktop Only) EL_SCI_EN -- R/W. In Desktop Mode with Intel Quick Resume Technology feature enabled, this bit enables the EL_SCI_STS signal to cause an SCI (depending on the SCI_EN bit) when it is asserted. In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit will be treated as Reserved. ICH7 and ICH7R Only: Reserved 31:16 15 13 444 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit 10 (Mobile/ Ultra Mobile Only) 9 (Desktop and Mobile Only) 9 (Ultra Mobile Only) Description BATLOW_EN -- R/W. (Mobile/Ultra Mobile Only) 0 = Disable. 1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event. PCI_EXP_EN -- R/W. 0 = Disable SCI generation upon PCI_EXP_STS bit being set. 1 = Enables Intel(R) ICH7 to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI due to wake/PME events. Reserved. Must be programmed to 0. 8 RI_EN -- R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by a CF9h write. 0 = Disable. 1 = Enables the setting of the RI_STS to generate a wake event. Reserved TCOSCI_EN -- R/W. 0 = Disable. 1 = Enables the setting of the TCOSCI_STS to generate an SCI. AC97_EN -- R/W. 0 = Disable. 1 = Enables the setting of the AC97_STS to generate a wake event. NOTE: This bit is also used for Intel(R) High Definition Audio when the Intel High Definition Audio host controller is enabled rather than the AC97 host controller. USB2_EN -- R/W. 0 = Disable. 1 = Enables the setting of the USB2_STS to generate a wake event. USB1_EN -- R/W. 0 = Disable. 1 = Enables the setting of the USB1_STS to generate a wake event. SWGPE_EN-- R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware will set SWGPE_STS (acts as a level input) If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1, then an SMI# will be generated 7 6 5 4 3 2 Intel (R) ICH7 Family Datasheet 445 LPC Interface Bridge Registers (D31:F0) Bit 1 (Desktop and Mobile Only) 1 (Ultra Mobile Only) HOT_PLUG_EN -- R/W. Description 0 = Disables SCI generation upon the HOT_PLUG_STS bit being set. 1 = Enables the Intel(R) ICH7 to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events. Reserved THRM_EN -- R/W. 0 0 = Disable. 1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the THRM_STS bit and generate a power management event (SCI or SMI). 446 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.12 SMI_EN--SMI Control and Enable Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 30h 00000000h No Core Attribute: Size: Usage: R/W, R/W (special), WO 32 bit ACPI or Legacy Note: This register is symmetrical to the SMI status register. Bit 31:26 Reserved Intel(R) ICH7DH Only: EL_SMI_EN -- R/W. 0 = Disable 25 1 = Software sets this bit to enable Intel Quick Resume Technology logic to cause SMI# ICH7 and ICH7R and Mobile/Ultra Mobile Only: Reserved 24:19 18 Reserved INTEL_USB2_EN -- R/W. 0 = Disable 1 = Enables Intel-Specific USB2 SMI logic to cause SMI#. LEGACY_USB2_EN -- R/W. 17 16:15 0 = Disable 1 = Enables legacy USB2 logic to cause SMI#. Reserved PERIODIC_EN -- R/W. 14 0 = Disable. 1 = Enables the Intel(R) ICH7 to generate an SMI# when the PERIODIC_STS bit (PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h). TCO_EN -- R/W. 0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs. 1 = Enables the TCO logic to generate SMI#. NOTE: This bit cannot be written once the TCO_LOCK bit is set. 12 Reserved MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) -- R/W. 11 0 = Disable. 1 = Enables ICH7 to trap accesses to the microcontroller range (62h or 66h) and generate an SMI#. Note that "trapped' cycles will be claimed by the ICH7 on PCI, but not forwarded to LPC. Reserved Description 13 10:8 Intel (R) ICH7 Family Datasheet 447 LPC Interface Bridge Registers (D31:F0) Bit Description BIOS Release (BIOS_RLS) -- WO. 0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect. 1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place. Software SMI# Timer Enable (SWSMI_TMR_EN) -- R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by software. APMC_EN -- R/W. 0 = Disable. Writes to the APM_CNT register will not cause an SMI#. 1 = Enables writes to the APM_CNT register to cause an SMI#. SLP_SMI_EN -- R/W. 0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit. 1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the system will not transition to the sleep state based on that write to the SLP_EN bit. LEGACY_USB_EN -- R/W. 0 = Disable. 1 = Enables legacy USB circuit to cause SMI#. BIOS_EN -- R/W. 0 = Disable. 1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit (D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set. End of SMI (EOS) -- R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for the Intel(R) ICH7 to assert SMI# low to the processor after SMI# has been asserted previously. 0 = Once the ICH7 asserts SMI# low, the EOS bit is automatically cleared. 1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit. NOTE: ICH7 is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent SMI require EOS bit is set. GBL_SMI_EN -- R/W. 0 = No SMI# will be generated by ICH7. This bit is reset by a PCI reset event. 1 = Enables the generation of SMI# in the system upon any enabled SMI event. NOTE: When the SMI_LOCK bit is set, this bit cannot be changed. 7 6 5 4 3 2 1 0 448 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.13 SMI_STS--SMI Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 34h 00000000h No Core Attribute: Size: Usage: RO, R/WC 32-bit ACPI or Legacy Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH7 will cause an SMI# (except bits 8-10 and 12, which do not need enable bits since they are logic ORs of other registers that have enable bits). The ICH7 uses the same GPE0_EN register (I/ O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec. Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as SCI generalpurpose events at boot, and exit from sleeping states. BIOS should define a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits. Bit 31:27 26 (Desktop and Mobile Only) 26 (Ultra Mobile Only) 25 (Desktop Only) 25 (Mobile Only) 24:22 Reserved SPI_STS -- RO. This bit will be set if the SPI logic is generating an SMI#. This bit is read only because the sticky status and enable bits associated with this function are located in the SPI registers. Description Reserved Intel(R) ICH7DH Only: EL_SMI_STS -- RO. This bit will be set if the Intel Quick Resume Technology logic is generating an SMI#. Writing a 1 to this bit clears this bit to `0'. ICH7 and ICH7R Only: Reserved. Reserved Reserved MONITOR_STS -- RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). See Section 7.1.36 through Section 7.1.39 for details on the specific cause of the SMI. PCI_EXP_SMI_STS -- RO. PCI Express* SMI event occurred. This could be due to a PCI Express PME event or Hot-Plug event. 21 20 (Desktop and Mobile Only) 20 (Ultra Mobile Only) 19 Reserved Reserved Intel (R) ICH7 Family Datasheet 449 LPC Interface Bridge Registers (D31:F0) Bit Description INTEL_USB2_STS -- RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. LEGACY_USB2_STS -- RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. SMBus SMI Status (SMBUS_SMI_STS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least 15.63 us after the initial assertion of this bit before clearing it. 1 = Indicates that the SMI# was caused by: 1. The SMBus Slave receiving a message that an SMI# should be caused, or 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or 4. The ICH7 detecting the SMLINK_SLAVE_SMI command while in the S0 state. SERIRQ_SMI_STS -- RO. 0 = SMI# was not caused by the SERIRQ decoder. 1 = Indicates that the SMI# was caused by the SERIRQ decoder. NOTE: This is not a sticky bit PERIODIC_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the Intel(R) ICH7 generates an SMI#. TCO_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = SMI# not caused by TCO logic. 1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event. Device Monitor Status (DEVMON_STS) -- RO. 0 = SMI# not caused by Device Monitor. 1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky, so writes to this bit will have no effect. Microcontroller SMI# Status (MCSMI_STS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = Indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = Set if there has been an access to the power management microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this implementation assumes that the Microcontroller is on LPC. If this bit is set, and the MCSMI_EN bit is also set, the ICH7 will generate an SMI#. 18 17 16 15 14 13 12 11 450 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) Bit Description GPI_STS -- RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not routed to cause an SMI# will have no effect on this bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion. GPE0_STS -- RO. This bit is a logical OR of the bits 14:10, 8:2, and 0 in the GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the GPE0_EN register (PMBASE + 2Ch). 0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event. PM1_STS_REG -- RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset PMBASE+00h) that can cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event. Reserved SWSMI_TMR_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = Software SMI# Timer has Not expired. 1 = Set by the hardware when the Software SMI# Timer expires. APM_STS -- R/WC. Software clears this bit by writing a 1 to it. 0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set. 1 = SMI# was generated by a write access to the APM Control register with the APMC_EN bit set. SLP_SMI_STS -- R/WC. Software clears this bit by writing a 1 to the bit location. 0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. 1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. LEGACY_USB_STS -- RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. BIOS_STS -- R/WC. 0 = No SMI# generated due to ACPI software requesting attention. 1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase + 30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when software writes a 1 to its bit position. Reserved 10 9 8 7 6 5 4 3 2 1:0 Intel (R) ICH7 Family Datasheet 451 LPC Interface Bridge Registers (D31:F0) 10.8.3.14 ALT_GP_SMI_EN--Alternate GPI SMI Enable Register I/O Address: Default Value: Lockable: Power Well: Bit PMBASE +38h 0000h No Resume Attribute: Size: Usage: R/W 16-bit ACPI or Legacy Description Alternate GPI SMI Enable -- R/W. These bits are used to enable the corresponding GPIO to cause an SMI#. For these bits to have any effect, the following must be true. 15:0 * * * The corresponding bit in the ALT_GP_SMI_EN register is set. The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI. The corresponding GPIO must be implemented. NOTE: Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to GPIO0. 10.8.3.15 ALT_GP_SMI_STS--Alternate GPI SMI Status Register I/O Address: Default Value: Lockable: Power Well: Bit PMBASE +3Ah 0000h No Resume Attribute: Size: Usage: R/WC 16-bit ACPI or Legacy Description Alternate GPI SMI Status -- R/WC. These bits report the status of the corresponding GPIOs. 0 = Inactive. Software clears this bit by writing a 1 to it. 1 = Active These bits are sticky. If the following conditions are true, then an SMI# will be generated and the GPE0_STS bit set: * * * The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI. The corresponding GPIO must be implemented. 15:0 All bits are in the resume well. Default for these bits is dependent on the state of the GPIO pins. 452 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.16 GPE_CNTL-- General Purpose Control Register I/O Address: Default Value: Lockable: Power Well: Bit 7:2 Reserved SWGPE_CTRL-- R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of 1 will clear SWGPE_STS to 0. THRM#_POL -- R/W. This bit controls the polarity of the THRM# pin needed to set the THRM_STS bit. 0 = Low value on the THRM# signal will set the THRM_STS bit. 1 = HIGH value on the THRM# signal will set the THRM_STS bit. PMBASE +42h 00h No Resume Attribute: Size: Usage: R/W 8-bit ACPI or Legacy Description 1 0 Intel (R) ICH7 Family Datasheet 453 LPC Interface Bridge Registers (D31:F0) 10.8.3.17 DEVACT_STS -- Device Activity Status Register I/O Address: Default Value: Lockable: Power Well: PMBASE +44h 0000h No Core Attribute: Size: Usage: R/WC 16-bit Legacy Only Each bit indicates if an access has occurred to the corresponding device's trap range, or for bits 6:9 if the corresponding PCI interrupt is active. This register is used in conjunction with the Periodic SMI# timer to detect any system activity for legacy power management. The periodic SMI# timer indicates if it is the right time to read the DEVACT_STS register (PMBASE + 44h). Note: Software clears bits that are set in this register by writing a 1 to the bit position. Bit 15:13 Reserved KBC_ACT_STS -- R/WC. KBC (60/64h). 12 0 = Indicates that there has been no access to this device's I/O range. 1 = This device's I/O range has been accessed. Clear this bit by writing a 1 to the bit location. Reserved PIRQDH_ACT_STS -- R/WC. PIRQ[D or H]. 9 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQCG_ACT_STS -- R/WC. PIRQ[C or G]. 8 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQBF_ACT_STS -- R/WC. PIRQ[B or F]. 7 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. PIRQAE_ACT_STS -- R/WC. PIRQ[A or E]. 6 0 = The corresponding PCI interrupts have not been active. 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. Reserved IDE_ACT_STS -- R/WC. IDE Primary Drive 0 and Drive 1. 0 0 = Indicates that there has been no access to this device's I/O range. 1 = This device's I/O range has been accessed. The enable bit is in the ATC register (D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit location. Description 11:10 5:1 454 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.8.3.18 SS_CNT-- Intel SpeedStep(R) Technology Control Register (Mobile/Ultra Mobile Only) I/O Address: Default Value Lockable: Power Well: PMBASE +50h 01h No Core Attribute: Size: Usage: R/W (special) 8-bit ACPI/Legacy Note: Writes to this register will initiate an Intel SpeedStep technology transition that involves a temporary transition to a C3-like state in which the STPCLK# signal will go active. An Intel SpeedStep technology transition always occur on writes to the SS_CNT register, even if the value written to SS_STATE is the same as the previous value (after this "transition" the system would still be in the same Intel SpeedStep technology state). If the SS_EN bit is 0, then writes to this register will have no effect and reads will return 0. Bit 7:1 Reserved SS_STATE (Intel SpeedStep(R) technology State) -- R/W (Special). When this bit is read, it returns the last value written to this register. By convention, this will be the current Intel SpeedStep technology state. Writes to this register causes a change to the Intel SpeedStep technology state indicated by the value written to this bit. If the new value for SS_STATE is the same as the previous value, then transition will still occur. 0 = High power state. 1 = Low power state NOTE: This is only a convention because the transition is the same regardless of the value written to this bit. Description 0 10.8.3.19 C3_RES-- C3 Residency Register (Mobile/Ultra Mobile Only) I/O Address: Default Value Lockable: Power Well: PMBASE +54h 00000000h No Core Attribute: Size: Usage: R/W/RO 32-bit ACPI/Legacy The value in this field increments at the same rate as the Power Management Timer. This field increments while STP_CPU# is active (i.e. the CPU is in a C3 or C4 state). This field will roll over in the same way as the Power Management Timer, however the most significant bit is NOT sticky. Bit 31:24 Reserved C3_RESIDENCY -- RO. The value in this field increments at the same rate as the Power Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automatically resets to 0 at the point when the Lvl3 or Lvl4 read occurs. If the C3_RESIDENCY_MODE bit is set, the register does not reset when the Lvl3 or Lvl4 read occurs. In either mode, it increments while STP_CPU# is active (i.e., the processor is in a C3 or C4 state). This field will roll over in the same way as the PM Timer, however the most significant bit is NOT sticky. Software is responsible for reading this field before performing the Lvl3/4 transition. Software must also check for rollover if the maximum time in C3/C4 could be exceeded. NOTE: Hardware reset is the only reset of this counter field. Description 23:0 Intel (R) ICH7 Family Datasheet 455 LPC Interface Bridge Registers (D31:F0) 10.9 System Management TCO Registers (D31:F0) The TCO logic is accessed via registers mapped to the PCI configuration space (Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device 31:Function 0 PCI Configuration registers. TCO Register I/O Map The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is, PMBASE + 60h in the PCI configuration space. The following table shows the mapping of the registers within that 32-byte range. Each register is described in the following sections. Table 10-12. TCO I/O Register Address Map TCOBASE + Offset 00h-01h 02h 03h 04h-05h 06h-07h Mnemonic TCO_RLD TCO_DAT_IN TCO_DAT_OUT TCO1_STS TCO2_STS Register Name TCO Timer Reload and Current Value TCO Data In TCO Data Out TCO1 Status TCO2 Status Default 0000h 00h 00h 0000h 0000h Type R/W R/W R/W R/WC, RO R/W, R/WC R/W, R/W (special), R/WC R/W R/W R/W -- R/W -- R/W -- 08h-09h TCO1_CNT TCO1 Control 0000h 0Ah-0Bh 0Ch-0Dh 0Eh 0Fh 10h 11h 12h-13h 14h-1Fh TCO2_CNT TCO_MESSAGE1, TCO_MESSAGE2 TCO_WDCNT -- SW_IRQ_GEN -- TCO_TMR -- TCO2 Control TCO Message 1 and 2 Watchdog Control Reserved Software IRQ Generation Reserved TCO Timer Initial Value Reserved 0008h 00h 00h -- 11h -- 0004h -- 10.9.1 TCO_RLD--TCO Timer Reload and Current Value Register I/O Address: Default Value: Lockable: Bit 15:10 9:0 Reserved TCO Timer Value -- R/W. Reading this register will return the current count of the TCO timer. Writing any value to this register will reload the timer to prevent the timeout. TCOBASE +00h 0000h No Attribute: Size: Power Well: Description R/W 16-bit Core 456 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.9.2 TCO_DAT_IN--TCO Data In Register I/O Address: Default Value: Lockable: Bit 7:0 TCOBASE +02h 00h No Attribute: Size: Power Well: Description R/W 8-bit Core TCO Data In Value -- R/W. This data register field is used for passing commands from the OS to the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h). 10.9.3 TCO_DAT_OUT--TCO Data Out Register I/O Address: Default Value: Lockable: Bit TCOBASE +03h 00h No Attribute: Size: Power Well: Description R/W 8-bit Core 7:0 TCO Data Out Value -- R/W. This data register field is used for passing commands from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL bits. 10.9.4 TCO1_STS--TCO1 Status Register I/O Address: Default Value: Lockable: TCOBASE +04h 0000h No Attribute: Size: Power Well: R/WC, RO 16-bit Core (Except bit 7, in RTC) Bit 15:13 Reserved DMISERR_STS -- R/WC. 12 Description 0 = Software clears this bit by writing a 1 to it. 1 = Intel(R) ICH7 received a DMI special cycle message via DMI indicating that it wants to cause an SERR#. The software must read the (G)MCH to determine the reason for the SERR#. Reserved DMISMI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH7 received a DMI special cycle message via DMI indicating that it wants to cause an SMI. The software must read the (G)MCH to determine the reason for the SMI. DMISCI_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = ICH7 received a DMI special cycle message via DMI indicating that it wants to cause an SCI. The software must read the (G)MCH to determine the reason for the SCI. 11 10 9 Intel (R) ICH7 Family Datasheet 457 LPC Interface Bridge Registers (D31:F0) Bit BIOSWR_STS -- R/WC. Description 0 = Software clears this bit by writing a 1 to it. 1 = ICH7 sets this bit and generates and SMI# to indicate an invalid attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set. NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will not be set. NEWCENTURY_STS -- R/WC. This bit is in the RTC well. 0 = Cleared by writing a 1 to the bit position or by RTCRST# going active. 1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00. Setting this bit will cause an SMI# (but not a wake event). NOTE: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when RTC power has not been maintained). Software can determine if RTC power has not been maintained by checking the RTC_PWR_STS bit (D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a legal value and then clear the NEWCENTURY_STS bit. The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered. 8 7 6:4 3 Reserved TIMEOUT -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by ICH7 to indicate that the SMI was caused by the TCO timer reaching 0. TCO_INT_STS -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register (TCOBASE + 03h). SW_TCO_SMI -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h). NMI2SMI_STS -- RO. 0 = Cleared by clearing the associated NMI status bit. 1 = Set by the ICH7 when an SMI# occurs because an event occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set). 2 1 0 458 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.9.5 TCO2_STS--TCO2 Status Register I/O Address: Default Value: Lockable: TCOBASE +06h 0000h No Attribute: Size: Power Well: R/W, R/WC 16-bit Resume (Except Bit 0, in RTC) Bit 15:5 Reserved Description SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) -- R/WC. Allow the software to go directly into pre-determined sleep state. This avoids race conditions. Software clears this bit by writing a 1 to it. 4 0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3-S5 states. 1 = Intel(R) ICH7 sets this bit to 1 when it receives the SMI message on the SMLink's Slave Interface. Reserved BOOT_STS -- R/WC. 0 = Cleared by ICH7 based on RSMRST# or by software writing a 1 to this bit. Note that software should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit. 1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the first instruction. If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the ICH7 will reboot using the `safe' multiplier (1111). This allows the system to recover from a processor frequency multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an invalid multiplier. SECOND_TO_STS -- R/WC. 1 0 = Software clears this bit by writing a 1 to it, or by a RSMRST#. 1 = ICH7 sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout occurred before the TCO_RLD register was written. If this bit is set and the NO_REBOOT config bit is 0, then the ICH7 will reboot the system after the second timeout. The reboot is done by asserting PLTRST#. Intruder Detect (INTRD_DET) -- R/WC. 0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion. 1 = Set by ICH7 to indicate that an intrusion was detected. This bit is set even if the system is in G3 state. NOTE: This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microseconds before it is read as a 0. Software must be aware of this recovery time when reading this bit after clearing it. NOTE: If the INTRUDER# signal is active when the software attempts to clear the INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah, bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes inactive and then active again, there will not be further SMI's (because the INTRD_SEL bits would select that no SMI# be generated). NOTE: If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. 3 2 0 Intel (R) ICH7 Family Datasheet 459 LPC Interface Bridge Registers (D31:F0) 10.9.6 TCO1_CNT--TCO1 Control Register I/O Address: Default Value: Lockable: Bit 15:13 Reserved TCO_LOCK -- R/W (special). When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0. This bit defaults to 0. TCO Timer Halt (TCO_TMR_HLT) -- R/W. 11 0 = The TCO Timer is enabled to count. 1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On LAN event messages from being transmitted on the SMLINK (but not Alert On LAN* heartbeat messages). SEND_NOW -- R/W (special). 0 = The Intel(R) ICH7 will clear this bit when it has completed sending the message. Software must not set this bit to 1 again until the ICH7 has set it back to 0. 1 = ICH7 sends an Alert On LAN Event message over the SMLINK interface, with the Software Event bit set. Setting the SEND_NOW bit causes the ICH7 integrated LAN controller to reset, which can have unpredictable side-effects. Unless software protects against these side effects, software should not attempt to set this bit. NMI2SMI_EN -- R/W. 0 = Normal NMI functionality. 1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table: 9 NMI_EN 0b 0b 1b 1b NMI_NOW -- R/WC. 8 0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit. Another NMI will not be generated until the bit is cleared. 1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to the NMI handler. Reserved GBL_SMI_EN 0b 1b 0b 1b Description No SMI# at all because GBL_SMI_EN = 0 SMI# will be caused due to NMI events No SMI# at all because GBL_SMI_EN = 0 No SMI# due to NMI because NMI_EN = 1 TCOBASE +08h 0000h No Attribute: Size: Power Well: Description R/W, R/W (special), R/WC 16-bit Core 12 10 7:0 460 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.9.7 TCO2_CNT--TCO2 Control Register I/O Address: Default Value: Lockable: Bit 15:6 Reserved OS_POLICY -- R/W. OS-based software writes to these bits to select the policy that the BIOS will use after the platform resets due the WDT. The following convention is recommended for the BIOS and OS: 00 = Boot normally 5:4 01 = Shut down 10 = Don't load OS. Hold in pre-boot state and use LAN to determine next step 11 = Reserved NOTE: These are just scratchpad bits. They should not be reset when the TCO logic resets the platform due to Watchdog Timer. GPIO11_ALERT_DISABLE -- R/W. At reset (via RSMRST# asserted) this bit is set and GPIO11 alerts are disabled. 3 0 = Enable. 1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus slave. INTRD_SEL -- R/W. This field selects the action to take if the INTRUDER# signal goes active. 2:1 00 = No interrupt or SMI# 01 = Interrupt (as selected by TCO_INT_SEL). 10 = SMI 11 = Reserved 0 Reserved TCOBASE +0Ah 0008h No Attribute: Size: Power Well: Description R/W 16-bit Resume 10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers I/O Address: Default Value: Lockable: Bit 7:0 TCOBASE +0Ch (Message 1) TCOBASE +0Dh (Message 2) 00h No Attribute: R/W Size: 8-bit Power Well: Resume Description TCO_MESSAGE[n] -- R/W. The value written into this register will be sent out via the SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this register to indicate its boot progress which can be monitored externally. Intel (R) ICH7 Family Datasheet 461 LPC Interface Bridge Registers (D31:F0) 10.9.9 TCO_WDCNT--TCO Watchdog Control Register Offset Address: TCOBASE + 0Eh Default Value: 00h Power Well: Resume Bit Attribute: Size: R/W 8 bits Description Watchdog Status (WDSTATUS) -- R/W. The value written to this register will be sent in the Alert On LAN message on the SMLINK interface. It can be used by the BIOS or system management software to indicate more details on the boot progress. This register will be reset to the default of 00h based on RSMRST# (but not PCI reset). 7:0 10.9.10 SW_IRQ_GEN--Software IRQ Generation Register Offset Address: TCOBASE + 10h Default Value: 11h Power Well: Core Bit 7:2 1 Reserved IRQ12_CAUSE -- R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by the Intel(R) ICH7's SERIRQ logic. This bit must be a 1 (default) if the ICH7 is expected to receive IRQ12 assertions from a SERIRQ device. IRQ1_CAUSE -- R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by the ICH7's SERIRQ logic. This bit must be a 1 (default) if the ICH7 is expected to receive IRQ1 assertions from a SERIRQ device. Attribute: Size: R/W 8 bits Description 0 10.9.11 TCO_TMR--TCO Timer Initial Value Register I/O Address: Default Value: Lockable: Bit 15:10 Reserved TCO Timer Initial Value -- R/W. Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of 1 tick (0.6s). The TCO Timer will only count down in the S0 state. TCOBASE +12h 0004h No Attribute: Size: Power Well: Description R/W 16-bit Core 9:0 462 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.10 General Purpose I/O Registers (D31:F0) The control for the general purpose I/O signals is handled through a separate 64-byte I/O space. The base offset for this space is selected by the GPIOBASE register. GPIO Register I/O Address Map Table 10-13. Registers to Control GPIO Address Map GPIOBASE + Offset Mnemonic Register Name General Registers 1F3FF7FFh (desktop only) / 1F2AF7FFh (mobile/Ultra Mobile only) E0E8FFFFh -- 02FE0000h -- Default Access 00h-03h GPIO_USE_SEL GPIO Use Select R/W 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h GP_IO_SEL -- GP_LVL GPIO Input/Output Select Reserved GPIO Level for Input or Output Reserved Output Control Registers R/W -- R/W -- 14h-17h 18h-1Bh 1Ch-1Fh -- GPO_BLINK -- Reserved GPIO Blink Enable Reserved Input Control Registers -- 00040000h -- -- R/W -- 20-2Bh 2C-2Fh -- GPI_INV Reserved GPIO Signal Invert -- 00000000h 000300FFh (desktop only) / 000300FEh (mobile/Ultra Mobile only) 000000F0h 00030003h -- R/W 30h-33h GPIO_USE_SEL2 GPIO Use Select 2 [63:32] R/W 34h-37h 38h-3Bh GP_IO_SEL2 GP_LVL2 GPIO Input/Output Select 2 [63:32] GPIO Level for Input or Output 2 [63:32] R/W R/W Intel (R) ICH7 Family Datasheet 463 LPC Interface Bridge Registers (D31:F0) 10.10.1 GPIO_USE_SEL--GPIO Use Select Register Offset Address: GPIOBASE + 00h Attribute: Default Value: 1F3FF7FFh (Desktop only) Size: 1F2AF7FFh (Mobile/Ultra Mobile only) Lockable: No Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description GPIO_USE_SEL[31:0] -- R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. NOTES: 1. The following bits are always 1 because they are unmuxed: 6:10,12:15, 24:25 2. The following bits are not implemented because they are determined by the Desktop Only /Mobile Only/Ultra Mobile configuration: 16, 18, 20, 32 3. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no effect. 4. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as their default function. After just a PLTRST#, the GPIO in the core well are configured as their default function. 5. When configured to GPIO mode, the multiplexing logic will present the inactive state to native logic that uses the pin as an input. 6. All GPIOs are reset to the default state by CF9h reset except GPIO24 31:0 10.10.2 GP_IO_SEL--GPIO Input/Output Select Register Offset Address: GPIOBASE +04h Default Value: E0E8FFFFh Lockable: No Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description GP_IO_SEL[31:0] -- R/W. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode. 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. 31:0 464 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.10.3 GP_LVL--GPIO Level for Input or Output Register Offset Address: GPIOBASE +0Ch Default Value: 02FE0000h Lockable: No Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description GP_LVL[31:0]-- R/W: If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. 31:0 If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low.) and writes will have no effect. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode. 10.10.4 GPO_BLINK--GPO Blink Enable Register Offset Address: GPIOBASE +18h Default Value: 00040000h Lockable: No Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description GP_BLINK[31:0] -- R/W. The setting of this bit has no effect if the corresponding GPIO signal is programmed as an input. 0 = The corresponding GPIO will function normally. 1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate of approximately once per second. The high and low times have approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set. The value of the corresponding GP_LVL bit remains unchanged during the blink process, and does not effect the blink in any way. The GP_LVL bit is not altered when programmed to blink. It will remain at its previous value. These bits correspond to GPIO in the Resume well. These bits revert to the default value based on RSMRST# or a write to the CF9h register (but not just on PLTRST#). 31:0 NOTE: (Desktop Only) GPIO18 will blink by default immediately after reset. This signal could be connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful POST). Intel (R) ICH7 Family Datasheet 465 LPC Interface Bridge Registers (D31:F0) 10.10.5 GPI_INV--GPIO Signal Invert Register Offset Address: GPIOBASE +2Ch Default Value: 00000000h Lockable: No Attribute: Size: Power Well: R/W 32-bit Core for 0:7, 16:23, Resume for 8:15, 24:31 Bit Description GP_INV[n] -- R/W. Input Inversion: This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters. When set to 1, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is reported in the GP_LVL register. These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by the Intel(R) ICH7. In the S3, S4 or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will be reset to their default values by RSMRST# or by a write to the CF9h register. 0 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input pin to be high. 1 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input pin to be low. 31:0 10.10.6 GPIO_USE_SEL2--GPIO Use Select 2 Register[63:32] Offset Address: GPIOBASE +30h Attribute: Default Value: 000300FFh (Desktop Only) Size: 000300FEh (Mobile/Ultra Mobile Only) Lockable: No Power Well: R/W 32-bit CPU I/O for 17, Core for 16, 7:0 Bit Description GPIO_USE_SEL2[49:48, 39:32] Bits[17:16, 7:0]-- R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. 17:16, 7:0 After a full reset (RSMRST#), all multiplexed signals in the resume and core wells are configured as a GPIO rather than as their native function. After just a PLTRST#, the GPIO in the core well are configured as GPIO. NOTES: 1. The following bits are not implemented because there is no corresponding GPIO: 31:18, 15:8. 2. The following bits are not implemented because they are determined by the Desktop/Mobile/Ultra Mobile configuration: 0 466 Intel (R) ICH7 Family Datasheet LPC Interface Bridge Registers (D31:F0) 10.10.7 GP_IO_SEL2--GPIO Input/Output Select 2 Register[63:32] Offset Address: GPIOBASE +34h Default Value: 000000F0h Lockable: No Attribute: Size: Power Well: R/W 32-bit CPU I/O for 17, Core for 16, 7:0 Bit 31:18, 15:8 17:16, 7:0 Always 0. No corresponding GPIO. Description GP_IO_SEL2[49:48, 39:32] -- R/W. 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an input. 10.10.8 GP_LVL2--GPIO Level for Input or Output 2 Register[63:32] Offset Address: GPIOBASE +38h Default Value: 00030003h Lockable: No Attribute: Size: Power Well: R/W 32-bit CPU I/O for 17, Core for 16:0 Bit 31:18, 15:8 Reserved. Read-only 0 GP_LVL[49:48, 39:32] -- R/W. Description 17:16, 7:0 If GPIO[n] is programmed to be an output (via the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the state of the input signal (1 = high, 0 = low.) and writes will have no effect. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The value reported in this register is undefined when programmed as native mode. Intel (R) ICH7 Family Datasheet 467 LPC Interface Bridge Registers (D31:F0) 468 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11 11.1 Note: UHCI Controllers Registers PCI Configuration Registers (USB--D29:F0/F1/F2/F3) Register address locations that are not shown in Table 11-1 and should be treated as Reserved (see Section 6.2 for details). Table 11-1. UHCI Controller PCI Register Address Map (USB--D29:F0/F1/F2/F3) Offset 00-01h 02-03h 04-05h 06-07h 08h Mnemonic VID DID PCICMD PCISTS RID Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Master Latency Timer Header Type Base Address Subsystem Vendor Identification Subsystem Identification Interrupt Line Interrupt Pin Serial Bus Release Number USB Legacy Keyboard/Mouse Control USB Resume Enable Core Well Policy Function 0 Function 1 Function 2 Function 3 Default Default Default Default 8086h 8086h 8086h See register description 0000h 0280h See register description 00h 03h 0Ch 00h 00h 8086h See register description 0000h 0280h See register description 00h 03h 0Ch 00h 00h Type RO RO R/W, RO R/WC, RO RO See register See register description description 0000h 0280h See register description 00h 03h 0Ch 00h 80h 00000001h 0000h 0000h 00h 0000h 0280h See register description 00h 03h 0Ch 00h 00h 09h 0Ah 0Bh 0Dh 0Eh 20-23h 2C-2Dh 2E-2Fh 3Ch 3Dh PI SCC BCC MLT HEADTYP BASE SVID SID INT_LN INT_PN RO RO RO RO RO R/W, RO R/WO R/WO R/W RO 00000001h 00000001h 00000001h 0000h 0000h 00h 0000h 0000h 00h 0000h 0000h 00h See See See See register register register register description. description. description. description. 10h 10h 10h 10h 60h USB_RELNUM RO R/W, RO R/WC R/W R/W C0-C1h C4h C8h USB_LEGKEY USB_RES CWP 2000h 00h 00h 2000h 00h 00h 2000h 00h 00h 2000h 00h 00h NOTE: Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register Intel (R) ICH7 Family Datasheet 469 UHCI Controllers Registers 11.1.1 VID--Vendor Identification Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 15:0 00h-01h 8086h Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel 11.1.2 DID--Device Identification Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: 02h-03h UHCI #1 = See bit description UHCI #2 = See bit description UHCI #3 = See bit description UHCI #4 = See bit description Attribute: Size: RO 16 bits Bit 15:0 Description Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 USB universal host controllers. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 11.1.3 PCICMD--PCI Command Register (USB--D29:F0/F1/F2/ F3) Address Offset: Default Value: Bit 15:11 Reserved Interrupt Disable -- R/W. 10 0 = Enable. The function is able to generate its interrupt to the interrupt controller. 1 = Disable. The function is not capable of generating interrupts. NOTE: The corresponding Interrupt Status bit is not affected by the interrupt enable. 9 8 7 6 5 4 3 2 1 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. SERR# Enable -- RO. Reserved as 0. Wait Cycle Control (WCC) -- RO. Hardwired to 0. Parity Error Response (PER) -- RO. Hardwired to 0. VGA Palette Snoop (VPS) -- RO. Hardwired to 0. Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. Special Cycle Enable (SCE) -- RO. Hardwired to 0. Bus Master Enable (BME) -- R/W. 0 = Disable 1 = Enable. Intel(R) ICH7 can act as a master on the PCI bus for USB transfers. Memory Space Enable (MSE) -- RO. Hardwired to 0. I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 0 = Disable 1 = Enable accesses to the USB I/O registers. The Base Address register for USB should be programmed before this bit is set. 04h-05h 0000h Attribute: Size: Description R/W, RO 16 bits 470 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.1.4 PCISTS--PCI Status Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: 06h-07h 0280h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE) -- R/WC. 15 0 = No parity error detected. 1 = Set when a data parity error data parity error is detected on writes to the UHCI register space or on read completions returned to the host controller. Reserved as 0b. Read Only. Received Master Abort (RMA) -- R/WC. 13 12 0 = No master abort generated by USB. 1 = USB, as a master, generated a master abort. Reserved. Always read as 0. Signaled Target Abort (STA) -- R/WC. 11 0 = Intel(R) ICH7 did Not terminate transaction for USB function with a target abort. 1 = USB function is targeted with a transaction that the ICH7 terminates with a target abort. DEVSEL# Timing Status (DEV_STS) -- RO. This 2-bit field defines the timing for DEVSEL# assertion. These read only bits indicate the ICH7's DEVSEL# timing when performing a positive decode. ICH7 generates DEVSEL# with medium timing for USB. Data Parity Error Detected (DPED) -- RO. Hardwired to 0. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. User Definable Features (UDF) -- RO. Hardwired to 0. 66 MHz Capable -- RO. Hardwired to 0. Capabilities List -- RO. Hardwired to 0. Interrupt Status -- RO. This bit reflects the state of this function's interrupt at the input of the enable/disable logic. 3 0 = Interrupt is de-asserted. 1 = Interrupt is asserted. The value reported in this bit is independent of the value in the Interrupt Enable bit. 2:0 Reserved 14 10:9 8 7 6 5 4 11.1.5 RID--Revision Identification Register (USB--D29:F0/F1/F2/F3) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. Intel (R) ICH7 Family Datasheet 471 UHCI Controllers Registers 11.1.6 PI--Programming Interface Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:0 Programming Interface -- RO. 00h = No specific register level programming interface defined. 09h 00h Attribute: Size: Description RO 8 bits 11.1.7 SCC--Sub Class Code Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:0 Sub Class Code (SCC) -- RO. 03h = USB host controller. 0Ah 03h Attribute: Size: Description RO 8 bits 11.1.8 BCC--Base Class Code Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:0 Base Class Code (BCC) -- RO. 0Ch = Serial Bus controller. 0Bh 0Ch Attribute: Size: Description RO 8 bits 472 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.1.9 MLT--Master Latency Timer Register (USB--D29:F0/F1/F2/F3) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer (MLT) -- RO. The USB controller is implemented internal to the Intel(R) ICH7 and not arbitrated as a PCI device. Therefore the device does not require a Master Latency Timer. 11.1.10 HEADTYP--Header Type Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: 0Eh FN 0: 80h FN 1: 00h FN 2: 00h FN 3: 00h Attribute: Size: RO 8 bits For functions 1, 2, and 3, this register is hardwired to 00h. For function 0, bit 7 is determined by the values in the USB Function Disable bits (11:8 of the Function Disable register Chipset Config Registers:Offset 3418h). Bit Multi-Function Device -- RO. 0 = Single-function device. 1 = Multi-function device. Since the upper functions in this device can be individually hidden, this bit is based on the function-disable bits in Chipset Config Space: Offset 3418h as follows: D29:F7_Disa ble (bit 15) 0b X X X 1 D29:F3_Disa ble (bit 11) X 0b X X 1 D29:F2_Disa ble (bit10) X X 0b X 1 D29:F1_Disa ble (bit 9) X X X 0b 1 Multi-Function Device (this bit) 1 1 1 1 0 Description 7 6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout. Intel (R) ICH7 Family Datasheet 473 UHCI Controllers Registers 11.1.11 BASE--Base Address Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 31:16 15:5 4:1 0 Reserved Base Address -- R/W. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. This gives 32 bytes of relocatable I/O space. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate that the base address field in this register maps to I/O space. 20h-23h 00000001h Attribute: Size: Description R/W, RO 32 bits 11.1.12 SVID -- Subsystem Vendor Identification Register (USB--D29:F0/F1/F2/F3) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem Vendor ID (SVID) -- R/WO. BIOS sets the value in this register to identify the Subsystem Vendor ID. The USB_SVID register, in combination with the USB Subsystem ID register, enables the operating system to distinguish each subsystem from the others. NOTE: The software can write to this register only once per core well reset. Writes should be done as a single, 16-bit cycle. 11.1.13 SID -- Subsystem Identification Register (USB--D29:F0/F1/F2/F3) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem ID (SID) -- R/WO. BIOS sets the value in this register to identify the Subsystem ID. The SID register, in combination with the SVID register (D29:F0/F1/F2/ F3:2C), enables the operating system to distinguish each subsystem from other(s). The value read in this register is the same as what was written to the IDE_SID register. NOTE: The software can write to this register only once per core well reset. Writes should be done as a single, 16-bit cycle. 474 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.1.14 INT_LN--Interrupt Line Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:0 3Ch 00h Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- RO. This data is not used by the Intel(R) ICH7. It is to communicate to software the interrupt line that the interrupt pin is connected to. 11.1.15 INT_PN--Interrupt Pin Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: 3Dh Attribute: Function 0: See Description Size: Function 1: See Description Function 2: See Description Function 3: See Description Description Interrupt Line (INT_LN) -- RO. This value tells the software which interrupt pin each USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the Interrupt Pin default values that are programmed in the memorymapped configuration space as follows: 7:0 Function 0 Function 1 Function 2 Function 3 D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0) D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4) D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8) D29IP.U3P (Chipset Config Registers:Offset 3108:bits 15:12) RO 8 bits Bit NOTE: This does not determine the mapping to the PIRQ pins. 11.1.16 USB_RELNUM--Serial Bus Release Number Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:0 Serial Bus Release Number -- RO. 10h = USB controller supports the USB Specification, Release 1.0. 60h 10h Attribute: Size: Description RO 8 bits Intel (R) ICH7 Family Datasheet 475 UHCI Controllers Registers 11.1.17 USB_LEGKEY--USB Legacy Keyboard/Mouse Control Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: C0h-C1h 2000h Attribute: Size: R/W, R/WC, RO 16 bits This register is implemented separately in each of the USB UHCI functions. However, the enable and status bits for the trapping logic are OR'd and shared, respectively, since their functionality is not specific to any one host controller. Bit Description SMI Caused by End of Pass-Through (SMIBYENDPS) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred 14 Reserved PCI Interrupt Enable (USBPIRQEN) -- R/W. This bit is used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note that, when disabled, it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 = Disable 1 = Enable SMI Caused by USB Interrupt (SMIBYUSB) -- RO. This bit indicates if an interrupt event occurred from this controller. The interrupt from the controller is taken before the enable in bit 13 has any effect to create this read-only bit. Note that even if the corresponding enable bit is not set in Bit 4, this bit may still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit will have no effect. 1 = Event Occurred. SMI Caused by Port 64 Write (TRAPBY64W) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 64 Read (TRAPBY64R) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 60 Write (TRAPBY60W) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. 15 13 12 11 10 9 476 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers Bit Description SMI Caused by Port 60 Read (TRAPBY60R) -- R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI at End of Pass-Through Enable (SMIATENDPS) -- R/W. This bit enables SMI at the end of a pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to be serviced later. 0 = Disable 1 = Enable Pass Through State (PSTATE) -- RO. 0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence. A20Gate Pass-Through Enable (A20PASSEN) -- R/W. 0 = Disable. 1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the SMI status bits. SMI on USB IRQ Enable (USBSMIEN) -- R/W. 0 = Disable 1 = Enable. USB interrupt will cause an SMI event. SMI on Port 64 Writes Enable (64WEN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 11 will cause an SMI event. SMI on Port 64 Reads Enable (64REN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 10 will cause an SMI event. SMI on Port 60 Writes Enable (60WEN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 9 will cause an SMI event. SMI on Port 60 Reads Enable (60REN) -- R/W. 0 = Disable 1 = Enable. A 1 in bit 8 will cause an SMI event. 8 7 6 5 4 3 2 1 0 Intel (R) ICH7 Family Datasheet 477 UHCI Controllers Registers 11.1.18 USB_RES--USB Resume Enable Register (USB--D29:F0/F1/F2/F3) Address Offset: Default Value: Bit 7:2 Reserved PORT1EN -- R/W. Enable port 1 of the USB controller to respond to wakeup events. 1 0 = The USB controller will not look at this port for a wakeup event. 1 = The USB controller will monitor this port for remote wakeup and connect/ disconnect events. PORT0EN -- R/W. Enable port 0 of the USB controller to respond to wakeup events. 0 0 = The USB controller will not look at this port for a wakeup event. 1 = The USB controller will monitor this port for remote wakeup and connect/ disconnect events. C4h 00h Attribute: Size: Description R/W 8 bits 11.1.19 CWP--Core Well Policy Register (USB--D29:F0/F1/F2/F3) Address Offset: C8h Default Value: 00h Bit 7:1 Reserved Static Bus Master Status Policy Enable (SBMSPE) -- R/W. 0 = The UHCI host controller dynamically sets the Bus Master status bit (Power Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory accesses that are scheduled. For mobile/Ultra Mobile only, the default setting provides a more accurate indication of snoopable memory accesses in order to help with software-invoked entry to C3 and C4 power states. 1 = The UHCI host controller statically forces the Bus Master Status bit in power management space to 1 whenever the HCHalted bit (USB Status Register, Base+02h, bit 5) is cleared. NOTE: The PCI Power Management registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). Attribute: Size: Description R/W 8 bits 0 478 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.2 USB I/O Registers Some of the read/write register bits that deal with changing the state of the USB hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. This allows the software to poll the state of the port and wait until it is in the proper state before proceeding. A host controller reset, global reset, or port reset will immediately terminate a transfer on the affected ports and disable the port. This affects the USBCMD register, bit 4 and the PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail. Table 11-2. USB I/O Registers BASE + Offset 00-01h 02-03h 04-05h 06-07h 08-0Bh 0Ch 0D-0Fh 10-11h 12-13h Mnemonic USBCMD USBSTS USBINTR FRNUM FRBASEADD SOFMOD -- PORTSC0 PORTSC1 Register Name USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start of Frame Modify Reserved Port 0 Status/Control Port 1 Status/Control Default 0000h 0020h 0000h 0000h Undefined 40h -- 0080h 0080h Type R/W R/WC R/W R/W (see Note 1) R/W R/W -- R/WC, RO, R/W (see Note 1) R/WC, RO, R/W (see Note 1) NOTES: 1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects. Intel (R) ICH7 Family Datasheet 479 UHCI Controllers Registers 11.2.1 USBCMD--USB Command Register I/O Offset: Default Value: Base + (00h-01h) 0000h Attribute: Size: R/W 16 bits The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. The table following the bit description provides additional information on the operation of the Run/Stop and Debug bits. Bit 15:7 Reserved Loop Back Test Mode -- R/W. 8 0 = Disable loop back test mode. 1 = Intel(R) ICH7 is in loop back test mode. When both ports are connected together, a write to one port will be seen on the other port and the data will be stored in I/O offset 18h. Max Packet (MAXP) -- R/W. This bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. This value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the SOF counter. Use of reclamation packets larger than the programmed size will cause a Babble error if executed during the critical window at frame end. The Babble error results in the offending endpoint being stalled. Software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes Configure Flag (CF) -- R/W. This bit has no effect on the hardware. It is provided only as a semaphore service for software. 6 0 = Indicates that software has not completed host controller configuration. 1 = HCD software sets this bit as the last action in its process of configuring the host controller. Software Debug (SWDBG) -- R/W. The SWDBG bit must only be manipulated when the controller is in the stopped state. This can be determined by checking the HCHalted bit in the USBSTS register. 5 0 = Normal Mode. 1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after the completion of each USB transaction. The next transaction is executed when software sets the Run/Stop bit back to 1. Force Global Resume (FGR) -- R/W. 0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal. At that time all USB devices should be ready for bus activity. The 1 to 0 transition causes the port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed. 1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1 when a resume event (connect, disconnect, or K-state) is detected while in global suspend mode. Description 7 4 480 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers Bit Description Enter Global Suspend Mode (EGSM) -- R/W. 0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = Host controller enters the Global Suspend mode. No USB transactions occur during this time. The Host controller is able to receive resume signals from USB and interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit. Global Reset (GRESET) -- R/W. 0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified in Chapter 7 of the USB Specification. 1 = Global Reset. The host controller sends the global reset signal on the USB and then resets all its logic, including the internal hub registers. The hub registers are reset to their power on state. Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the host controller does not send the Global Reset on USB. Host Controller Reset (HCRESET) -- R/W. The effects of HCRESET on Hub registers are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of the host controller including the Connect/ Disconnect state machine (one for each port). When the Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the PORTSC (D29:F0/F1/F2/F3:BASE + 10h) to get set. The disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the connect and lowspeed detect will take place, and bits 0 and 8 of the PORTSC will change accordingly. 0 = Reset by the host controller when the reset process is complete. 1 = Reset. When this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. Run/Stop (RS) -- R/W. When set to 1, the ICH7 proceeds with execution of the schedule. The ICH7 continues execution as long as this bit is set. When this bit is cleared, the ICH7 completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. The host controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus errors. 0 = Stop 1 = Run NOTE: This bit should only be cleared if there are no active Transaction Descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. 3 2 1 0 Intel (R) ICH7 Family Datasheet 481 UHCI Controllers Registers Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation SWDBG (Bit 5) Run/Stop (Bit 0) Description If executing a command, the host controller completes the command and then stops. The 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the FRNUM register. (While Run/ Stop=0, the FRNUM register (D29:F0/F1/F2/F3:BASE + 06h) can be reprogrammed). Execution of the command list resumes from Start Of Frame using the frame list pointer selected by the current value in the FRNUM register. The host controller remains running until the Run/Stop bit is cleared (by software or hardware). If executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. All status are preserved. The host controller begins execution of the command list from where it left off when the Run/Stop bit is set. Execution of the command list resumes from where the previous execution stopped. The Run/Stop bit is set to 0 by the host controller when a TD is being fetched. This causes the host controller to stop again after the execution of the TD (single step). When the host controller has completed execution, the HC Halted bit in the Status Register is set. 0 0 0 1 1 0 1 1 When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1), the single stepping software debug operation is as follows: To Enter Software Debug Mode: 1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0. 2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1. 3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame List Single Step Loop. 4. HCD sets Run/Stop bit to 1. 5. Host controller executes next active TD, sets Run/Stop bit to 0, and stops. 6. HCD reads the USBCMD register to check if the single step execution is completed (HCHalted=1). 7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end Software Debug mode. 8. HCD ends Software Debug mode by setting SWDBG bit to 0. 9. HCD sets up normal command list and Frame List table. 10. HCD sets Run/Stop bit to 1 to resume normal schedule execution. In Software Debug mode, when the Run/Stop bit is set, the host controller starts. When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS register (bit 5) is set. The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed. When the last active TD in a frame has been executed, the host controller waits until the next SOF is sent and then fetches the first TD of the next frame before halting. 482 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers This HCHalted bit can also be used outside of Software Debug mode to indicate when the host controller has detected the Run/Stop bit and has completed the current transaction. Outside of the Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the Run/Stop bit is set the host controller starts over again from the frame list location pointed to by the Frame List Index (see FRNUM Register description) rather than continuing where it stopped. 11.2.2 USBSTS--USB Status Register I/O Offset: Default Value: Base + (02h-03h) 0020h Attribute: Size: R/WC 16 bits This register indicates pending interrupts and various states of the host controller. The status resulting from a transaction on the serial bus is not indicated in this register. Bit 15:6 Reserved HCHalted -- R/WC. 5 0 = Software clears this bit by writing a 1 to it. 1 = The host controller has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). Default. Host Controller Process Error -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The host controller has detected a fatal error. This indicates that the host controller suffered a consistency check failure while processing a Transfer Descriptor. An example of a consistency check failure would be finding an invalid PID field while processing the packet header portion of the TD. When this error occurs, the host controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2/ F3:BASE + 00h, bit 0) to prevent further schedule execution. A hardware interrupt is generated to the system. Host System Error -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = A serious error occurred during a host system access involving the host controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system. Resume Detect (RSM_DET) -- R/WC. 2 0 = Software clears this bit by writing a 1 to it. 1 = The host controller received a "RESUME" signal from a USB device. This is only valid if the Host controller is in a global suspend state (Command register, D29:F0/ F1/F2/F3:BASE + 00h, bit 3 = 1). USB Error Interrupt -- R/WC. 1 0 = Software clears this bit by writing a 1 to it. 1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit (D29:F0/F1/F2/F3:BASE + 04h, bit 2) set, both this bit and Bit 0 are set. USB Interrupt (USBINT) -- R/WC. 0 0 = Software clears this bit by writing a 1 to it. 1 = The host controller sets this bit when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is detected (actual length field in TD is less than maximum length field in TD), and short packet detection is enabled in that TD. Description 4 3 Intel (R) ICH7 Family Datasheet 483 UHCI Controllers Registers 11.2.3 USBINTR--USB Interrupt Enable Register I/O Offset: Default Value: Base + (04h-05h) 0000h Attribute: Size: R/W 16 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors (host controller processor error, (D29:F0/F1/F2/ F3:BASE + 02h, bit 4, USBSTS Register) cannot be disabled by the host controller. Interrupt sources that are disabled in this register still appear in the Status Register to allow the software to poll for events. Bit 15:5 4 3 Reserved Scratchpad (SP) -- R/W. Short Packet Interrupt Enable -- R/W. 0 = Disabled. 1 = Enabled. Interrupt on Complete Enable (IOC) -- R/W. 2 0 = Disabled. 1 = Enabled. Resume Interrupt Enable -- R/W. 1 0 = Disabled. 1 = Enabled. Timeout/CRC Interrupt Enable -- R/W. 0 0 = Disabled. 1 = Enabled. Description 11.2.4 FRNUM--Frame Number Register I/O Offset: Default Value: Base + (06-07h) 0000h Attribute: Size: R/W (Writes must be Word Writes) 16 bits Bits [10:0] of this register contain the current frame number that is included in the frame SOF packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are used to select a particular entry in the Frame List during scheduled execution. This register is updated at the end of each frame time. This register must be written as a word. Byte writes are not supported. This register cannot be written unless the host controller is in the STOPPED state as indicated by the HCHalted bit (D29:F0/F1/F2/F3:BASE + 02h, bit 5). A write to this register while the Run/Stop bit is set (D29:F0/F1/F2/F3:BASE + 00h, bit 0) is ignored. Bit 15:11 Reserved Frame List Current Index/Frame Number -- R/W. This field provides the frame number in the SOF Frame. The value in this register increments at the end of each time frame (approximately every 1 ms). In addition, bits [9:0] are used for the Frame List current index and correspond to memory address signals [11:2]. Description 10:0 484 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.2.5 FRBASEADD--Frame List Base Address Register I/O Offset: Default Value: Base + (08h-0Bh) Undefined Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the host controller. When written, only the upper 20 bits are used. The lower 12 bits are written as 0's (4-KB alignment). The contents of this register are combined with the frame number counter to enable the host controller to step through the Frame List in sequence. The two least significant bits are always 00. This requires DWord-alignment for all list entries. This configuration supports 1024 Frame List entries. Bit 31:12 11:0 Description Base Address -- R/W. These bits correspond to memory address signals [31:12], respectively. Reserved Intel (R) ICH7 Family Datasheet 485 UHCI Controllers Registers 11.2.6 SOFMOD--Start of Frame Modify Register I/O Offset: Default Value: Base + (0Ch) 40h Attribute: Size: R/W 8 bits This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only the 7 least significant bits are used. When a new value is written into these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be used to adjust out any offset from the clock source that generates the clock that drives the SOF counter. This register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. Using this register, the frame length can be adjusted across the full range required by the USB specification. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by USB system software at any time. Its value will take effect from the beginning of the next frame. This register is reset upon a host controller reset or global reset. Software must maintain a copy of its value for reprogramming if necessary. Bit 7 Reserved SOF Timing Value -- R/W. Guidelines for the modification of frame time are contained in Chapter 7 of the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF frame length) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The following table indicates what SOF Timing Value to program into this field for a certain frame period. Frame Length (# 12 MHz Clocks) (decimal) 6:0 11936 11937 -- 11999 12000 12001 -- 12062 12063 SOF Timing Value (this register) (decimal) 0 1 -- 63 64 65 -- 126 127 Description 486 Intel (R) ICH7 Family Datasheet UHCI Controllers Registers 11.2.7 PORTSC[0,1]--Port Status and Control Register I/O Offset: Default Value: Port 0/2/4/6: Base + (10h-11h) Port 1/3/5/7: Base + (12h-13h) 0080h Attribute: R/WC, RO, R/W (Word writes only) Size: 16 bits Note: For Function 0, this applies to ICH7 USB ports 0 and 1; for Function 1, this applies to ICH7 USB ports 2 and 3; for Function 2, this applies to ICH7 USB ports 4 and 5; and for Function 3, this applies to ICH7 USB ports 6 and 7. After a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, Port disabled, and the bus line status is 00 (singleended 0). Port Reset and Enable Sequence When software wishes to reset a USB device it will assert the Port Reset bit in the Port Status and Control register. The minimum reset signaling time is 10 mS and is enforced by software. To complete the reset sequence, software clears the port reset bit. The Intel UHCI controller must re-detect the port connect after reset signaling is complete before the controller will allow the port enable bit to de set by software. This time is approximately 5.3 uS. Software has several possible options to meet the timing requirement and a partial list is enumerated below: * Iterate a short wait, setting the port enable bit and reading it back to see if the enable bit is set. * Poll the connect status bit and wait for the hardware to recognize the connect prior to enabling the port. * Wait longer than the hardware detect time after clearing the port reset and prior to enabling the port. Bit 15:13 Reserved -- RO. Suspend -- R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows: Bits [12,2] X,0 0, 1 1, 1 Hub State Disable Enable Suspend Description 12 When in suspend state, downstream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 1 = Port in suspend state. 0 = Port not in suspend state. NOTE: Normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. However, in the case of a specific error condition (out transaction with babble), the Intel(R) ICH7 may Overcurrent Indicator -- R/WC. Set by hardware. 11 0 = Software clears this bit by writing a 1 to it. 1 = Overcurrent pin has gone from inactive to active on this port. Intel (R) ICH7 Family Datasheet 487 UHCI Controllers Registers Bit 10 Description Overcurrent Active -- RO. This bit is set and cleared by hardware. 0 = Indicates that the overcurrent pin is inactive (high). 1 = Indicates that the overcurrent pin is active (low). Port Reset -- R/W. 0 = Port is not in Reset. 1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling. Low Speed Device Attached (LS) -- RO. 0 = Full speed device is attached. 1 = Low speed device is attached to this port. Reserved -- RO. Always read as 1. Resume Detect (RSM_DET) -- R/W. Software sets this bit to a 1 to drive resume signaling. The host controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while the port is in the Suspend state. The ICH7 will then reflect the K-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are `11'). Writing a 0 (from 1) causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed. 0 = No resume (K-state) detected/driven on port. 1 = Resume detected/driven on port. 9 8 7 6 5:4 Line Status -- RO. These bits reflect the D+ (bit 4) and D- (bit 5) signals lines' logical levels. These bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at EOF2 time (See Chapter 11 of the USB Specification). Port Enable/Disable Change -- R/WC. For the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). 0 = No change. Software clears this bit by writing a 1 to the bit location. 1 = Port enabled/disabled status has changed. Port Enabled/Disabled (PORT_EN) -- R/W. Ports can be enabled by host software only. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the USB. 0 = Disable 1 = Enable Connect Status Change -- R/WC. This bit indicates that a change has occurred in the port's Current Connect Status (see bit 0). The hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. If, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting" an alreadyset bit (i.e., the bit will remain set). However, the hub transfers the change bit only once when the host controller requests a data transfer to the Status Change endpoint. System software is responsible for determining state change history in such a case. 0 = No change. Software clears this bit by writing a 1 to it. 1 = Change in Current Connect Status. Current Connect Status -- RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. 1 = Device is present on port. 3 2 1 0 488 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) SATA is not supported on ICH7-U Ultra Mobile. Note: 12.1 Note: PCI Configuration Registers (SATA-D31:F2) Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 12-1. SATA Controller PCI Register Address Map (SATA-D31:F2) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h Mnemonic VID DID PCICMD PCISTS RID Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Default 8086h See register description. 0000h 02B0h See register description. See register description. See register description 01h 00h 00000001h 00000001h 00000001h 00000001h 00000001h 00000000h 0000h 0000h 80h 00h Type RO RO R/W, RO R/WC, RO RO See register description See register description RO RO R/W, RO R/W, RO R/W, RO R/W, RO R/W, RO See register description R/WO R/WO RO R/W 09h PI Programming Interface 0Ah 0Bh 0Dh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 2Ch-2Dh 2Eh-2Fh 34h 3Ch SCC BCC PMLT PCMD_BAR PCNL_BAR SCMD_BAR SCNL_BAR BAR ABAR SVID SID CAP INT_LN Sub Class Code Base Class Code Primary Master Latency Timer Primary Command Block Base Address Primary Control Block Base Address Secondary Command Block Base Address Secondary Control Block Base Address Legacy Bus Master Base Address AHCI Base Address Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Interrupt Line Intel (R) ICH7 Family Datasheet 489 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Table 12-1. SATA Controller PCI Register Address Map (SATA-D31:F2) (Sheet 2 of 2) Offset 3Dh 40h-41h 42h-43h 44h 48h 4Ah-4Bh 54h-57h 70h-71h 72h-73h 74h-75h 80h-81h 82h-83h 84h-87h 88h-89h 90h 92h-93h 94h-97h A0h A4h A8h-ABh ACh-AFh C0h C4h D0h-D3h E0h-E3h E4h-E7h E8h-EBh Mnemonic INT_PN IDE_TIMP IDE_TIMS SIDETIM SDMA_CNT SDMA_TIM IDE_CONFIG PID PC PMCS MSICI MSIMC MSIMA MSIMD MAP PCS SIR SIRI STRD SCAP0 SCAP1 ATC ATS SP BFCS BFTD1 BFTD2 Register Name Interrupt Pin Primary IDE Timing Secondary IDE Timing Slave IDE Timing Synchronous DMA Control Synchronous DMA Timing IDE I/O Configuration PCI Power Management Capability ID PCI Power Management Capabilities PCI Power Management Control and Status Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Message Data Address Map Port Control and Status SATA Initialization Register SATA Indexed Registers Index SATA Indexed Register Data SATA Capability Register 0 SATA Capability Register 1 APM Trapping Control ATM Trapping Status Scratch Pad BIST FIS Control/Status BIST FIS Transmit Data, DW1 BIST FIS Transmit Data, DW2 Default See register description. 0000h 0000h 00h 00h 0000h 00000000h See register description 4002h 0000h 7005h 0000h 00000000h 0000h 00h 0000h 00000000h 00h XXXXXXXXh 00100012h 00000048h 00h 00h 00000000h 00000000h 00000000h 00000000h Type RO R/W R/W R/W R/W R/W R/W RO RO R/W, RO, R/WC RO RO, R/W RO, R/W R/W R/W R/W, RO, R/WC R/W R/W R/W RO RO R/W R/WC R/W R/W, R/WC R/W R/W NOTE: The ICH7 SATA controller is not arbitrated as a PCI device; therefore, it does not need a master latency timer. 490 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.1 VID--Vendor Identification Register (SATA--D31:F2) Offset Address: 00h-01h Default Value: 8086h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 bit Core Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 12.1.2 DID--Device Identification Register (SATA--D31:F2) Offset Address: 02h-03h Default Value: See bit description Lockable: No Bit Attribute: Size: Power Well: Description RO 16 bit Core 15:0 Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 SATA controller. NOTE: The value of this field will change dependent upon the value of the MAP Register. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update and Section 12.1.33 12.1.3 PCICMD--PCI Command Register (SATA-D31:F2) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable -- R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 10 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. Fast Back to Back Enable (FBE) -- RO. Reserved as 0. SERR# Enable (SERR_EN) -- RO. Reserved as 0. Wait Cycle Control (WCC) -- RO. Reserved as 0. Parity Error Response (PER) -- R/W. 6 0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected. 1 = Enabled. SATA controller will generate PERR# when a data parity error is detected. VGA Palette Snoop (VPS) -- RO. Reserved as 0. Postable Memory Write Enable (PMWE) -- RO. Reserved as 0. Special Cycle Enable (SCE) -- RO. Reserved as 0. Attribute: Size: Description RO, R/W 16 bits 9 8 7 5 4 3 Intel (R) ICH7 Family Datasheet 491 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 2 Description Bus Master Enable (BME) -- R/W. This bit controls the ICH7's ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the generation of completions for split transaction commands. Intel(R) ICH7R/ICH7DH/ICH7-M/ICH7-M DH Only: Memory Space Enable (MSE) -- R/W / RO. This bit controls access to the SATA controller's target memory space (for AHCI). NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO). Software is responsible for clearing this bit before entering combined mode. ICH7 Only: For the 82801GB ICH7, this bit is RO as 0, unless the SCRAE bit (offset 94h:bit 9) is set. I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the Bus Master I/O registers. 1 = Enable. Note that the Base Address register for the Bus Master registers should be programmed before this bit is set. 1 0 12.1.4 PCISTS -- PCI Status Register (SATA-D31:F2) Address Offset: 06h-07h Default Value: 02B0h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 14 13 12 11 10:9 Description Detected Parity Error (DPE) -- R/WC. 0 = No parity error detected by SATA controller. 1 = SATA controller detects a parity error on its interface. Signaled System Error (SSE) -- RO. Reserved as 0. Received Master Abort (RMA) -- R/WC. 0 = Master abort Not generated. 1 = SATA controller, as a master, generated a master abort. Reserved as 0 -- RO. Signaled Target Abort (STA) -- RO. Reserved as 0. DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Hardwired; Controls the device select time for the SATA controller's PCI interface. Data Parity Error Detected (DPED) -- RO. For Intel(R) ICH7, this bit can only be set on read completions received from SiBUS where there is a parity error. 8 0 = Data parity error Not detected. 1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. Fast Back to Back Capable (FB2BC) -- RO. Reserved as 1. User Definable Features (UDF) -- RO. Reserved as 0. 66MHz Capable (66MHZ_CAP) -- RO. Reserved as 1. 7 6 5 492 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 4 Description Capabilities List (CAP_LIST) -- RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. Interrupt Status (INTS) -- RO. Reflects the state of INTx# messages. 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]). 1 = Interrupt is to be asserted Reserved 3 2:0 12.1.5 RID--Revision Identification Register (SATA--D31:F2) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. Intel(R) 12.1.6 12.1.6.1 PI--Programming Interface Register (SATA-D31:F2) When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h Address Offset: 09h Default Value: See bit description Bit 7 6:4 Attribute: Size: Description R/W, RO 8 bits This read-only bit is a 1 to indicate that the ICH7 supports bus master operation Reserved. Will always return 0. Secondary Mode Native Capable (SNC) -- RO. 0 = Secondary controller only supports legacy mode. 1 = Secondary controller supports both legacy and native modes. When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When MAP.MV is 00b, this bit reports as a 1. 3 Intel (R) ICH7 Family Datasheet 493 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description Secondary Mode Native Enable (SNE) -- R/W / RO. Determines the mode that the secondary channel is operating in. 0 = Secondary controller operating in legacy (compatibility) mode 1 = Secondary controller operating in native PCI mode. 2 When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is readonly (RO). Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b, this bit is read/write (R/W). If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by software. While in theory these bits can be programmed separately, such a configuration is not supported by hardware. Primary Mode Native Capable (PNC) -- RO. 0 = Primary controller only supports legacy mode. 1 = Primary controller supports both legacy and native modes. When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When MAP.MV is 00b, this bit reports as a 1 Primary Mode Native Enable (PNE) -- R/W / RO. Determines the mode that the primary channel is operating in. 0 = Primary controller operating in legacy (compatibility) mode. 1 = Primary controller operating in native PCI mode. 1 0 When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is readonly (RO). Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b, this bit is read/write (R/W). If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by software. While in theory these bits can be programmed separately, such a configuration is not supported by hardware. 12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h Address Offset: 09h Default Value: 00h Bit 7:0 Interface (IF) -- RO. When configured as RAID, this register becomes read only 0. Attribute: Size: Description RO 8 bits 12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h Address Offset: 09h Default Value: 01h Bit 7:0 Interface (IF) -- RO. Indicates the SATA Controller supports AHCI, rev 1.0. Attribute: Size: Description RO 8 bits 494 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.7 SCC--Sub Class Code Register (SATA-D31:F2) Address Offset: 0Ah Default Value: See bit description Bit Sub Class Code (SCC) This field specifies the sub-class code of the controller, per the table below: Intel(R) ICH7 Desktop Only: SCC Register Attribute RO ICH7-M Only: MAP.SMS (D31:F2:Offset 90h:bit 7:6) 7:0 00b 01b SCC Register Value 01h (IDE Controller) 06h (AHCI Controller) Scc Register Value 01h (IDE Controller) Attribute: Size: Description RO 8 bits Intel(R) Matrix Storage Technology Enabled ICH7 components Only (ICH7R, ICH7DH, and ICH7-M DH): MAP.SMS (D31:F2:Offset 90h:bit 7:6) 00b 01b 10b SCC Register Value 01h (IDE Controller) 06h (AHCI Controller) 04h (RAID Controller) 12.1.8 BCC--Base Class Code Register (SATA-D31:F2SATA-D31:F2) Address Offset: 0Bh Default Value: 01h Bit 7:0 Base Class Code (BCC) -- RO. 01h = Mass storage device Attribute: Size: Description RO 8 bits 12.1.9 PMLT--Primary Master Latency Timer Register (SATA-D31:F2) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) -- RO. 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. Intel (R) ICH7 Family Datasheet 495 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.10 PCMD_BAR--Primary Command Block Base Address Register (SATA-D31:F2) Address Offset: 10h-13h Default Value: 00000001h Attribute: Size: Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:3 2:1 0 NOTE: This 8-byte I/O space is used in native mode for the Primary Controller's Command Block. 12.1.11 PCNL_BAR--Primary Control Block Base Address Register (SATA-D31:F2) Address Offset: 14h-17h Default Value: 00000001h Attribute: Size: Description Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:2 1 0 NOTE: This 4-byte I/O space is used in native mode for the Primary Controller's Command Block. 12.1.12 SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) Address Offset: 18h-1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Reserved Base Address -- R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller's Command Block. 496 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.13 SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) Address Offset: 1Ch-1Fh Default Value: 00000001h Bit 31:16 15:2 1 0 Reserved Base Address -- R/W. This field provides the base address of the I/O space (4 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller's Command Block. 12.1.14 BAR -- Legacy Bus Master Base Address Register (SATA-D31:F2) Address Offset: 20h-23h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16byte IO space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit 31:16 15:4 3:1 0 Reserved Base Address -- R/W. This field provides the base address of the I/O space (16 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 to indicate a request for I/O space. Description 12.1.15 12.1.15.1 ABAR -- AHCI Base Address Register (SATA-D31:F2) Non AHCI Capable (Intel(R) ICH7 Feature Supported Components Only) Address Offset: 24h-27h Default Value: 00000000h Bit 31:0 Reserved Attribute: Size: Description RO 32 bits Intel (R) ICH7 Family Datasheet 497 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.15.2 AHCI Capable (Intel(R) ICH7R, ICH7DH, and Mobile Only) Address Offset: 24h-27h Default Value: 00000000h Attribute: Size: R/W, RO 32 bits This register allocates space for the memory registers defined in Section 12.3. For nonACHI capable ICH7 components (ICH7), this register is reserved and read only, unless the SCRAE bit (offset 94h:bit 9) is set, in which case the register follows the definition given in Section 12.1.15.2. Bit 31:10 9:4 3 2:1 0 Description Base Address (BA) -- R/W. Base address of register memory space (aligned to 1 KB) Reserved Prefetchable (PF) -- RO. Indicates that this range is not pre-fetchable Type (TP) -- RO. Indicates that this range can be mapped anywhere in 32-bit address space. Resource Type Indicator (RTE) -- RO. Hardwired to 0 to indicate a request for register memory space. NOTES: 1. .When the MAP.MV register is programmed for combined mode (00b), this register is RO. Software is responsible for clearing this bit before entering combined mode. 2. The ABAR register must be set to a value of 0001_0000h or greater. 12.1.16 SVID--Subsystem Vendor Identification Register (SATA-D31:F2) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description R/WO 16 bits Core Subsystem Vendor ID (SVID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. 12.1.17 SID--Subsystem Identification Register (SATA-D31:F2) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description R/WO 16 bits Core Subsystem ID (SID) -- R/WO. Value is written by BIOS. No hardware action taken on this value. 498 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.18 CAP--Capabilities Pointer Register (SATA-D31:F2) Address Offset: 34h Default Value: 80h Bit Attribute: Size: Description RO 8 bits 7:0 Capabilities Pointer (CAP_PTR) -- RO. Indicates that the first capability pointer offset is 80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in configuration space indicates that the SATA function and PATA functions are combined (values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of 01). 12.1.19 INT_LN--Interrupt Line Register (SATA-D31:F2) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line -- R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. 12.1.20 INT_PN--Interrupt Pin Register (SATA-D31:F2) Address Offset: 3Dh Default Value: See Register Description Bit 7:0 Attribute: Size: RO 8 bits Description Interrupt Pin -- RO. This reflects the value of D31IP.SIP (Chipset Config Registers:Offset 3100h: bits 11:8). 12.1.21 IDE_TIMP -- Primary IDE Timing Register (SATA-D31:F2) Address Offset: Primary: 40h-41h Secondary: 42h-43h Default Value: 0000h Attribute: Size: R/W 16 bits This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It also controls operation of the buffer for PIO transfers. Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Intel (R) ICH7 Family Datasheet 499 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description IDE Decode Enable (IDE) -- R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the Intel(R) ICH7 to decode the associated Command Blocks (1F0-1F7h for primary, 170-177h for secondary) and Control Block (3F6h for primary and 376h for secondary). This bit effects the IDE decode ranges for both legacy and native-Mode decoding. NOTE: This bit affects SATA operation in both combined and non-combined ATA modes. See Section 5.17 for more on ATA modes of operation. Drive 1 Timing Register Enable (SITRE) -- R/W. 15 14 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1 IORDY Sample Point (ISP) -- R/W. The setting of these bits determines the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point. 13:12 00 01 10 11 = = = = 5 clocks 4 clocks 3 clocks Reserved 11:10 Reserved Recovery Time (RCT) -- R/W. The setting of these bits determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle. 9:8 00 01 10 11 = = = = 4 3 2 1 clocks clocks clocks clock Drive 1 DMA Timing Enable (DTE1) -- R/W. 7 0 = Disable. 1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 1 Prefetch/Posting Enable (PPE1) -- R/W. 6 0 = Disable. 1 = Enable Prefetch and posting to the IDE data port for this drive. Drive 1 IORDY Sample Point Enable (IE1) -- R/W. 5 0 = Disable IORDY sampling for this drive. 1 = Enable IORDY sampling for this drive. Drive 1 Fast Timing Bank (TIME1) -- R/W. 4 0 = Accesses to the data port will use compatible timings for this drive. 1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register. Drive 0 DMA Timing Enable (DTE0) -- R/W. 3 0 = Disable 1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 0 Prefetch/Posting Enable (PPE0) -- R/W. 2 0 = Disable prefetch and posting to the IDE data port for this drive. 1 = Enable prefetch and posting to the IDE data port for this drive. 500 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 1 Description Drive 0 IORDY Sample Point Enable (IE0) -- R/W. 0 = Disable IORDY sampling is disabled for this drive. 1 = Enable IORDY sampling for this drive. Drive 0 Fast Timing Bank (TIME0) -- R/W. 0 = Accesses to the data port will use compatible timings for this drive. 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time 0 12.1.22 IDE_TIMS -- Slave IDE Timing Register (SATA-D31:F2) Address Offset: 44h Default Value: 00h Attribute: Size: R/W 8 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Bit Description Secondary Drive 1 IORDY Sample Point (SISP1) -- R/W. This field determines the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved Secondary Drive 1 Recovery Time (SRCT1) -- R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/ IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks Primary Drive 1 IORDY Sample Point (PISP1) -- R/W. This field determines the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved Primary Drive 1 Recovery Time (PRCT1) -- R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/ IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 7:6 5:4 3:2 1:0 Intel (R) ICH7 Family Datasheet 501 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.23 SDMA_CNT--Synchronous DMA Control Register (SATA-D31:F2) Address Offset: 48h Default Value: 00h Attribute: Size: R/W 8 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation unless otherwise noted. Bit 7:4 3 Reserved Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) -- R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for secondary channel drive 1 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) -- R/W. 2 0 = Disable (default) 1 = Enable Synchronous DMA mode for secondary drive 0. Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) -- R/W. 1 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 1 Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) -- R/W. 0 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 0 Description 502 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.24 SDMA_TIM--Synchronous DMA Timing Register (SATA-D31:F2) Address Offset: 4Ah-4Bh Default Value: 0000h Attribute: Size: R/W 16 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise noted. Bit 15:14 Reserved Secondary Drive 1 Cycle Time (SCT1) -- R/W. For Ultra ATA mode. The setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-toSTOP (RP) time is also determined by the setting of these bits. SCB1 = 0 (33 MHz clk) 13:12 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 11:10 Reserved Secondary Drive 0 Cycle Time (SCT0) -- R/W. For Ultra ATA mode. The setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-toSTOP (RP) time is also determined by the setting of these bits. SCB1 = 0 (33 MHz clk) 9:8 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 7:6 Reserved SCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved SCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved Description Intel (R) ICH7 Family Datasheet 503 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description Primary Drive 1 Cycle Time (PCT1) -- R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved 5:4 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 3:2 Reserved Primary Drive 0 Cycle Time (PCT0) -- R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved 1:0 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 12.1.25 IDE_CONFIG--IDE I/O Configuration Register (SATA-D31:F2) Address Offset: 54h-57h Default Value: 00000000h Attribute: Size: R/W 32 bits Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise noted. Bit 31:24 23:20 Reserved Scratchpad (SP2). Intel(R) ICH7 does not perform any actions on these bits. SEC_SIG_MODE -- R/W. These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support. 19:18 If the SRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 01 10 11 = = = = Normal (Enabled) Tri-state (Disabled) Drive low (Disabled) Reserved Description 504 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description PRIM_SIG_MODE -- R/W. These bits are used to control mode of the Primary IDE signal pins for mobile swap bay support. 17:16 If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 01 10 11 = = = = Normal (Enabled) Tri-state (Disabled) Drive low (Disabled) Reserved 15 Fast Secondary Drive 1 Base Clock (FAST_SCB1) -- R/W. This bit is used in conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/ 100 timings for the Secondary Slave drive. 0 = Disable Ultra ATA/100 timing for the Secondary Slave drive. 1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register). Fast Secondary Drive 0 Base Clock (FAST_SCB0) -- R/W. This bit is used in conjunction with the SCT0 bits (D31:F2:4Ah, bits 9:8) to enable/disable Ultra ATA/100 timings for the Secondary Master drive. 0 = Disable Ultra ATA/100 timing for the Secondary Master drive. 1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register). Fast Primary Drive 1 Base Clock (FAST_PCB1) -- R/W. This bit is used in conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. 1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register). Fast Primary Drive 0 Base Clock (FAST_PCB0) -- R/W. This bit is used in conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100 timings for the Primary Master drive. 0 = Disable Ultra ATA/100 timing for the Primary Master drive. 1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register). Reserved Scratchpad (SP1). ICH7 does not perform any action on these bits. Secondary Drive 1 Base Clock (SCB1) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Secondary Drive 0 Base Clock (SCBO) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 1 Base Clock (PCB1) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Primary Drive 0 Base Clock (PCB0) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings 14 13 12 11:8 7:4 3 2 1 0 Intel (R) ICH7 Family Datasheet 505 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.26 PID--PCI Power Management Capability Identification Register (SATA-D31:F2) Address Offset: 70h-71h Default Value: XX01h Bits Next Capability (NEXT) -- RO. 15:8 00h -- if SCC = 01h (IDE mode). A8h -- for all other values of SCC to point to the next capability structure. This field is changed to 00h if the SCRD bit (D31:F2;Offset 94h bit-30) is set. 7:0 Capability ID (CID) -- RO. Indicates that this pointer is a PCI power management. Attribute: Size: Description RO 16 bits 12.1.27 PC--PCI Power Management Capabilities Register (SATA-D31:F2) Address Offset: 72h-73h Default Value: 4002h Attribute: Size: Description PME Support (PME_SUP) -- RO. Indicates PME# can be generated from the D3HOT state in the SATA host controller. D2 Support (D2_SUP) -- RO. Hardwired to 0. The D2 state is not supported D1 Support (D1_SUP) -- RO. Hardwired to 0. The D1 state is not supported Auxiliary Current (AUX_CUR) -- RO. PME# from D3COLD state is not supported, therefore this field is 000b. Device Specific Initialization (DSI) -- RO. Hardwired to 0 to indicate that no devicespecific initialization is required. Reserved PME Clock (PME_CLK) -- RO. Hardwired to 0 to indicate that PCI clock is not required to generate PME#. Version (VER) -- RO. Hardwired to 010 to indicates support for Revision 1.1 of the PCI Power Management Specification. RO 16 bits f Bits 15:11 10 9 8:6 5 4 3 2:0 506 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.28 PMCS--PCI Power Management Control and Status Register (SATA-D31:F2) Address Offset: 74h-75h Default Value: 0000h Bits 15 14:9 8 7:2 Attribute: Size: Description RO, R/W, R/WC 16 bits PME Status (PMES) -- R/WC. Bit is set when a PME event is to be requested, and if this bit and PMEE is set, a PME# will be generated from the SATA controller. Reserved PME Enable (PMEE) -- R/W. 0 = Disable. 1 = Enable. SATA controller generates PME# form D3HOT on a wake event. Reserved Power State (PS) -- R/W. These bits are used both to determine the current power state of the SATA controller and to set a new power state. 1:0 00 = D0 state 11 = D3HOT state When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. 12.1.29 MSICI--Message Signaled Interrupt Capability Identification (SATA-D31:F2) Address Offset: 80h-81h Default Value: 7005h Bits 15:8 7:0 Attribute: Size: Description RO 16 bits Next Pointer (NEXT): Indicates the next item in the list is the PCI power management pointer. Capability ID (CID): Capabilities ID indicates MSI. 12.1.30 MSIMC--Message Signaled Interrupt Message Control (SATA-D31:F2) Address Offset: 82h-83h Default Value: 0000h Bits 15:8 7 Reserved 64 Bit Address Capable (C64): Capable of generating a 32-bit message only. Attribute: Size: Description R/W, RO 16 bits Intel (R) ICH7 Family Datasheet 507 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bits Description Multiple Message Enable (MME): When this field is cleared to `000' (and MSIE is set), only a single MSI message will be generated for all SATA ports, and bits [15:0] of the message vector will be driven from MD[15:0]. When this field is set to `001' (and MSIE is set), two MSI messages will be generated. Bit [15:1] of the message vectors will be driven from MD[15:1] and bit [0] of the message vector will be driven dependent on which SATA port is the source of the interrupt: `0' for port 0, and `1' for ports 1, 2 and 3. When this field is set to `010' (and MSIE is set), four message will be generated, one for each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:2], while bits[1:0] will be driven dependent on which SATA port is the source of the interrupt: `00' for port 0, `01' for port 1, `10' for port 2, and `11' for port 3. MME Value Driven on MSI Memory Write Bits[15:2] MD[15:2] MD[15:2] Bit[1] MD[1] MD[1] Port 0: 0 010 MD[15:2] Port 1: 0 Port 2: 1 Port 3: 1 011-111 Reserved Bit[0] MD[0] Ports 0: 0 Ports 1,2,3: 1 Port 0: 0 Port 1: 1 Port 2: 0 Port 3: 1 6:4 000 001 Values `011b' to `111b' are reserved. If this field is set to one of these reserved values, the results are undefined. 3:1 0 Multiple Message Capable (MMC): Indicates that the ICH7 SATA controller supports four interrupt messages. MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used to generate interrupts. 12.1.31 MSIMA-- Message Signaled Interrupt Message Address (SATA-D31:F2) Address Offset: 84h-87h Default Value: 00000000h Bits 31:2 1:0 Attribute: Size: Description RO, R/W 32 bits Address (ADDR): Lower 32 bits of the system specified message address, always DWord aligned. Reserved 508 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.32 MSIMD--Message Signaled Interrupt Message Data (SATA-D31:F2) Address Offset: 88h-89h Default Value: 0000h Bits Attribute: Size: Description R/W 16 bits 15:0 Data (DATA)-- R/W: This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word of the data bus of the MSI memory write transaction. Note that when the MME field is set to `001' or `010', bit [0] and bits [1:0] respectively of the MSI memory write transaction will be driven based on the source of the interrupt rather than from MD[1:0]. See the description of the MME field. 12.1.33 MAP--Address Map Register (SATA-D31:F2) Address Offset: 90h Default Value: 00h Bits Attribute: Size: Description R/W 8 bits SATA Mode Select (SMS) -- R/W: Software programs these bits to control the mode in which the SATA HBA should operate: 00b 01b 10b 11b 7:6 = = = = IDE mode AHCI mode RAID mode Reserved NOTES: 1. The SATA Function Device ID will change based on the value of this register. 2. When combined mode is used (MV Not equal to `0'), only IDE mode is allowed. IDE mode can be selected when AHCI and/or RAID are enabled 3. AHCI mode may only be selected when MV = 0 4. RAID mode may only be selected when MV = 0 5. Programming these bits with values that are invalid (e.g, selecting RAID when in combined mode) will result in indeterministic behavior by the hardware. Reserved. Map Value -- R/W. Map Value (MV): The value in the bits below indicate the address range the SATA ports responds to, and whether or not the PATA and SATA functions are combined. When in combined mode, the AHCI memory space is not available and AHCI may not be used. 5:2 1:0 00 = Non-combined. P0 is primary master, P2 is the primary slave. P1 is secondary master, P3 is the secondary slave (desktop only). P0 is primary master, P2 is the primary slave (mobile only). 01 = Combined. IDE is primary. P1 is secondary master, P3 is the secondary slave. (desktop only) 10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary 11 = Reserved Intel (R) ICH7 Family Datasheet 509 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.34 PCS--Port Control and Status Register (SATA-D31:F2) Address Offset: 92h-93h Default Value: 0000h Attribute: Size: R/W, R/WC, RO 16 bits This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space. Bits 15:8 Reserved. Description Port 3 Present (P3P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P3E. This bit is not cleared upon surprise 7 (Desktop removal of a device. Only) 0 = No device detected. 1 = The presence of a device on Port 3 has been detected. 7 (Mobile Reserved Only) Port 2 Present (P2P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P2E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 2 has been detected. Port 1 Present (P1P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P1E. This bit is not cleared upon surprise 5 (Desktop removal of a device. Only) 0 = No device detected. 1 = The presence of a device on Port 1 has been detected. 5 (Mobile Reserved Only) Port 0 Present (P0P) -- RO. The status of this bit may change at any time. This bit is cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal of a device. 0 = No device detected. 1 = The presence of a device on Port 0 has been detected. Port 3 Enabled (P3E) -- R/W. 3 0 = Disabled. The port is in the `off' state and cannot detect any devices. (Desktop 1 = Enabled. The port can transition between the on, partial, and slumber states and Only) can detect devices. NOTE: This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1) 3 (Mobile Reserved Only) Port 2 Enabled (P2E) -- R/W. 2 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1) 6 4 Port 1 Enabled (P1E) -- R/W. 1 0 = Disabled. The port is in the `off' state and cannot detect any devices. (Desktop 1 = Enabled. The port can transition between the on, partial, and slumber states and Only) can detect devices. NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1) 1 (Mobile Reserved Only) 510 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bits Port 0 Enabled (P0E) -- R/W. 0 Description 0 = Disabled. The port is in the `off' state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1) 12.1.35 SIR--SATA Initialization Register Address Offset: 94h-97h Default Value: 00000000h Attribute: Size: Description Reserved SATA Capability Registers Disable (SCRD). When this bit is set, the SATA Capability Registers are disabled. That is, SATA Capability Registers 0 and 1 are both changed to Read Only with the value of 00000000h. Also, the Next Capability bits in the PCI Power Management Capability Information Register (D31:F2;Offset 70h bits 15:8) are changed to 00h, to indicate that the PCI Power Management Capability structure is the last PCI capability structure in the SATA controller. When this bit is cleared, the SATA Capability Registers are enabled. Reserved SATA Clock Request Enabled (SCRE) -- R/W. 28 0 = SATA Clock Request protocol is disabled. SATACLKREQ# pin when in native function will always output '0' to keep the SATA clock running. 1 = SATA Clock Request protocol is enabled. SATACLKREQ# pin when in native function will behave as the Serial ATA clock request to the system clock chip. Reserved R/W 32 bits . Bit 31:29 30 29 27:24 (Desktop Only) 27:24 (Mobile Only) 23 22:10 SATA Initialization Field 3 (SIF3) -- R/W. BIOS shall always program this register to the value 0Ah. All other values are reserved. SATA Initialization Field 2 (SIF2) -- R/W. BIOS shall always program this register to the value 1b. All other values are reserved. Reserved SCR Access Enable (SCRAE) -- R/W. In non-AHCI mode, this bit allows access to the SATA SCR registers (SStatus, SControl, and SError registers). 0 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1) remain as defined. 1 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1) are forced to be read/write. 9 NOTES: 1. Using this mode only allows access to AHCI registers PxSSTS, PxSCTL, PxSERR. All other AHCI space is reserved when this bit is set. 2. Proper use of this bit requires: * * ABAR must be programmed to a valid BAR; MSE must be set before software can access AHCI space. The Port Implemented bit (D31:F2, Offset ABAR+0Ch) for the corresponding port has to be set to allow access to the AHCI port specific PxSSTS, PxSCTL, and PxSERR registers. Intel (R) ICH7 Family Datasheet 511 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 8:0 Description SATA Initialization Field 1 (SIF1) -- R/W. BIOS shall always program this register to the value 180h. All other values are reserved. 12.1.36 SIRI--SATA Indexed Registers Index Address Offset: A0h Default Value: 00h Attribute: Size: Description Index (IDX) -- R/W. This field contains a 6-bit index pointer into the SATA Indexed Register space. Data is written into and read from the SIRD register (D31:F2:A4h). Reserved R/W 8 bits . Bit 7:2 1:0 SATA Indexed Registers Index 00h-03h 04h-1Bh 1Ch-1Fh 20h-73h 74h-77h 78h-FFh Name SATA TX Termination Test Register 1 (STTT1) Reserved SATA Test Mode Enable Register (STME) Reserved SATA TX Termination Test Register 2 (STTT2) Reserved 12.1.37 STRD--SATA Indexed Register Data Address Offset: A4h Default Value: XXXXXXXXh Attribute: Size: Description Data (DTA) -- R/W. This field contains a 32-bit data value that is written to the register pointed to by SIRI (D31:F2;A0h) or read from the register pointed to by SIRI. R/W 32 bits . Bit 31:0 512 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.37.1 STTT1--SATA Indexed Registers Index 00h (SATA TX Termination Test Register 1) Address Offset: Index 00h-03h Default Value: 00000000h Attribute: Size: Description Reserved. Port 1 TX Termination Test Enable -- R/W: 0 = Port 1 TX termination port testing is disabled. 1 1 = Enables testing of Port 1 TX termination. NOTE: This bit only to be used for system board testing. Port 0 TX Termination Test Enable -- R/W: 0 = Port 0 TX termination port testing is disabled. 0 1 = Enables testing of Port 0 TX termination. NOTE: This bit only to be used for system board testing. R/W 32 bits . Bit 31:2 12.1.37.2 STME--SATA Indexed Registers Index C1h (SATA Test Mode Enable Register) Address Offset: Index 1Ch-1Fh Default Value: 00000000h Attribute: Size: Description Reserved. SATA Test Mode Enable Bit -- R/W: 0 = Entrance to Intel(R) ICH7 SATA test modes are disabled. 18 1 = This bit allows entrance to ICH7 SATA test modes when set. NOTE: This bit only to be used for system board testing. 17:0 Reserved. R/W 32 bits . Bit 31:19 Intel (R) ICH7 Family Datasheet 513 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.37.3 STTT2 -- SATA Indexed Registers Index 74h (SATA TX Termination Test Register 2) Address Offset: Index 74h - 77h Default Value: 00000000h Attribute: Size: Description Reserved. Port 3 TX Termination Test Enable -- R/W: 0 = Port 3 TX termination port testing is disabled. 17 1 = Enables testing of Port 3 TX termination. NOTE: This bit only to be used for system board testing. Port 2 TX Termination Test Enable -- R/W: 0 = Port 2 TX termination port testing is disabled. 16 1 = Enables testing of Port 2 TX termination. NOTE: This bit only to be used for system board testing. 15:0 Reserved. R/W 32 bits . Bit 31:18 12.1.38 SCAP0--SATA Capability Register 0 (SATA-D31:F2) Address Offset: A8h-ABh Default Value: 00100012h Attribute: Size: RO 32 bits This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set. Bit 31:24 23:20 19:16 15:8 7:0 Reserved Major Revision (MAJREV) -- RO: Major revision number of the SATA Capability Pointer implemented. Minor Revision (MINREV) -- RO: Minor revision number of the SATA Capability Pointer implemented. Next Capability Pointer (NEXT) -- RO: Points to the next capability structure. 00h indicates this is the last capability pointer. Capability ID (CAP)-- RO: This value of 12h has been assigned by the PCI SIG to designate the SATA Capability Structure. Description 514 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.39 SCAP1--SATA Capability Register 1 (SATA-D31:F2) Address Offset: ACh-AFh Default Value: 00000048h Attribute: Size: RO 32 bits This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set. Bit 31:16 Reserved BAR Offset (BAROFST) -- RO: Indicates the offset into the BAR where the Index/Data pair are located (in DWord granularity). The Index and Data I/O registers are located at offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h. 000h = 0h offset 15:4 001h = 4h offset 002h = 8h offset 003h = Bh offset 004h = 10h offset ... FFFh = 3FFFh offset (max 16KB) BAR Location (BARLOC) -- RO: Indicates the absolute PCI Configuration Register address of the BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside within the space defined by LBAR in the SATA controller. A value of 8h indicates offset 20h, which is LBAR. 0000 - 0011b = reserved 0100b = 10h => BAR0 3:0 0101b = 14h => BAR1 0110b = 18h => BAR2 0111b = 1Ch => BAR3 1000b = 20h => LBAR 1001b = 24h => BAR5 1010 - 1110b = reserved 1111b = Index/Data pair in PCI Configuration space. This is not supported in Intel(R) ICH7. Description Intel (R) ICH7 Family Datasheet 515 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.40 ATC--APM Trapping Control Register (SATA-D31:F2) Address Offset: C0h Default Value: 00h Attribute: Size: Description Reserved Secondary Slave Trap (SST) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 170h-177h and 376h. The active device on the secondary interface must be device 1 for the trap and/or SMI# to occur. Secondary Master Trap (SMT) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 170h-177h and 376h. The active device on the secondary interface must be device 0 for the trap and/or SMI# to occur. Primary Slave Trap (PST) -- R/W. Enables trapping and SMI# assertion on legacy I/ O accesses to 1F0h-1F7h and 3F6h. The active device on the primary interface must be device 1 for the trap and/or SMI# to occur. Primary Master Trap (PMT) -- R/W. Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h. The active device on the primary interface must be device 0 for the trap and/or SMI# to occur. R/W 8 bits . Bit 7:4 3 2 1 0 12.1.41 ATS--APM Trapping Status Register (SATA-D31:F2) Address Offset: C4h Default Value: 00h Attribute: Size: Description Reserved Secondary Slave Trap (SST) -- R/WC. Indicates that a trap occurred to the secondary slave device. Secondary Master Trap (SPT) -- R/WC. Indicates that a trap occurred to the secondary master device. Primary Slave Trap (PST) -- R/WC. Indicates that a trap occurred to the primary slave device. Primary Master Trap (PMT) -- R/WC. Indicates that a trap occurred to the primary master device. R/WC 8 bits . Bit 7:4 3 2 1 0 12.1.42 SP -- Scratch Pad Register (SATA-D31:F2) Address Offset: D0h Default Value: 00000000h Attribute: Size: Description Data (DT) -- R/W. This is a read/write register that is available for software to use. No hardware action is taken on this register. R/W 32 bits . Bit 31:0 516 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.43 BFCS--BIST FIS Control/Status Register (SATA-D31:F2) Address Offset: E0h-E3h Default Value: 00000000h Bits 31:14 Reserved Attribute: Size: Description R/W, R/WC 32 bits Port 3 BIST FIS Initiate (P3BFI) -- R/W. When a rising edge is detected on this bit field, the Intel(R) ICH7 initiates a BIST FIS to the device on Port 3, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 3 is present and ready (not partial/ 13 slumber state). After a BIST FIS is successfully completed, software must disable and (Desktop re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST Only) FISes or to return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully. 13 (Mobile Only) Reserved. Port 2 BIST FIS Initiate (P2BFI) -- R/W. When a rising edge is detected on this bit field, the ICH7 initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully BIST FIS Successful (BFS) -- R/WC. 11 0 = Software clears this bit by writing a 1 to it. 1 = BIST FIS transmitted by ICH7 received an R_OK completion status from the device. NOTE: This bit must be cleared by software prior to initiating a BIST FIS. BIST FIS Failed (BFF) -- R/WC. 10 0 = Software clears this bit by writing a 1 to it. 1 = BIST FIS transmitted by ICH7 received an R_ERR completion status from the device. NOTE: This bit must be cleared by software prior to initiating a BIST FIS. Port 1 BIST FIS Initiate (P1BFI) -- R/W. When a rising edge is detected on this bit field, the ICH7 initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is present and ready (not partial/slumber state). 9 After a BIST FIS is successfully completed, software must disable and re-enable the (Desktop port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to Only) return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully 12 Intel (R) ICH7 Family Datasheet 517 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bits 9 (Mobile Only) Reserved. Description 8 Port 0 BIST FIS Initiate (P0BFI) -- R/W. When a rising edge is detected on this bit field, the ICH7 initiates a BIST FIS to the device on Port 0, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 0 is present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS eventually completes successfully BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST FIS Pattern Definition in any BIST FIS transmitted by the ICH7. This field is not port specific; its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or port 3. The specific bit definitions are: 7:2 Bit 7: T - Far End Transmit mode Bit 6: A - Align Bypass mode Bit 5: S - Bypass Scrambling Bit 4: L - Far End Retimed Loopback Bit 3: F - Far End Analog Loopback Bit 2: P - Primitive bit for use with Transmit mode 1:0 Reserved 12.1.44 BFTD1--BIST FIS Transmit Data1 Register (SATA-D31:F2) Address Offset: E4h-E7h Default Value: 00000000h Bits Attribute: Size: Description R/W 32 bits 31:0 BIST FIS Transmit Data 1 -- R/W. The data programmed into this register will form the contents of the second DWord of any BIST FIS initiated by the Intel(R) ICH7. This register is not port specific; its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST FIS is set to indicate "Far-End Transmit mode", this register's contents will be transmitted as the BIST FIS 2nd DW regardless of whether or not the "T" bit is indicated in the BFCS register (D31:F2:E0h). 518 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.1.45 BFTD2--BIST FIS Transmit Data2 Register (SATA-D31:F2) Address Offset: E8h-EBh Default Value: 00000000h Bits Attribute: Size: Description R/W 32 bits 31:0 BIST FIS Transmit Data 2 -- R/W. The data programmed into this register will form the contents of the third DWord of any BIST FIS initiated by the Intel(R) ICH7. This register is not port specific; its contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST FIS is set to indicate "Far-End Transmit mode", this register's contents will be transmitted as the BIST FIS 3rd DW regardless of whether or not the "T" bit is indicated in the BFCS register (D31:F2:E0h). 12.2 Bus Master IDE I/O Registers (D31:F2) The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register, located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no effect (but should not be attempted). These registers are only used for legacy operation. Software must not use these registers when running AHCI. The description of the I/O registers is shown in Table 12-2. Table 12-2. Bus Master IDE I/O Register Address Map BAR+ Offset 00 01 02 03 04-07 08 09 0Ah 0Bh 0Ch- 0Fh 10h 14h Mnemonic BMICP -- BMISP -- BMIDP BMICS -- BMISS -- BMIDS AIR AIDR Register Command Register Primary Reserved Bus Master IDE Status Register Primary Reserved Bus Master IDE Descriptor Table Pointer Primary Command Register Secondary Reserved Bus Master IDE Status Register Secondary Reserved Bus Master IDE Descriptor Table Pointer Secondary AHCI Index Register AHCI Index Data Register Default 00h -- 00h -- xxxxxxxxh 00h -- 00h -- xxxxxxxxh 00000000 h xxxxxxxxh Type R/W RO R/W, R/ WC, RO RO R/W R/W RO R/W, R/ WC, RO RO R/W R/W, RO R/W Intel (R) ICH7 Family Datasheet 519 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.2.1 BMIC[P,S]--Bus Master IDE Command Register (D31:F2) Address Offset: Primary: BAR + 00h Secondary: BAR + 08h Default Value: 00h Bit 7:4 Reserved. Returns 0. Read / Write Control (R/WC) -- R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Returns 0. Start/Stop Bus Master (START) -- R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. NOTE: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the drive in a Attribute: Size: Description R/W 8 bits 3 2:1 0 520 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.2.2 BMIS[P,S]--Bus Master IDE Status Register (D31:F2) Address Offset: Primary: BAR + 02h Secondary: BAR + 0Ah Default Value: 00h Bit Attribute: Size: Description R/W, R/WC, RO 8 bits PRD Interrupt Status (PRDIS) -- R/WC. 7 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set. Drive 1 DMA Capable -- R/W. 6 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The Intel(R) ICH7 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Drive 0 DMA Capable -- R/W. 5 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH7 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Reserved. Returns 0. Interrupt -- R/WC. 2 0 = Software clears this bit by writing a 1 to it. 1 = Set when a device FIS is received with the `I' bit set, provided that software has not disabled interrupts via the IEN bit of the Device Control Register (see chapter 5 of the Serial ATA Specification, Revision 1.0a). Error -- R/WC. 1 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. Bus Master IDE Active (ACT) -- RO. 0 = This bit is cleared by the ICH7 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH7 when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the ICH7 when the Start bit is written to the Command register. 4:3 0 Intel (R) ICH7 Family Datasheet 521 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.2.3 BMID[P,S]--Bus Master IDE Descriptor Table Pointer Register (D31:F2) Address Offset: Primary: BAR + 04h-07h Attribute: Secondary: BAR + 0Ch-0Fh Default Value: All bits undefined Size: Bit 31:2 1:0 Description Address of Descriptor Table (ADDR) -- R/W. The bits in this field correspond to A[31:2]. The Descriptor Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in memory. Reserved R/W 32 bits 12.2.4 AIR--AHCI Index Register (D31:F2) Address Offset: Primary: BAR + 10h Default Value: 00000000h Bit 31:10 9:2 1:0 Reserved Index (INDEX)-- R/W: This Index register is used to select the DWord offset of the Memory Mapped AHCI register to be accessed. A DWord, Word or Byte access is specified by the active byte enables of the I/O access to the Data register. Reserved Attribute: Size: Description R/W, RO 32 bits 12.2.5 AIDR--AHCI Index Data Register (D31:F2) Address Offset: Primary: BAR + 14h Default Value: All bits undefined Bit Attribute: Size: Description R/W 32 bits 31:0 Data (DATA)-- R/W: This Data register is a "window" through which data is read or written to the AHCI memory mapped registers. A read or write to this Data register triggers a corresponding read or write to the memory mapped register pointed to by the Index register. The Index register must be setup prior to the read or write to this Data register. Note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. Since this is not a physical register, the "default" value is the same as the default value of the register pointed to by Index. 522 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3 Note: AHCI Registers (D31:F2) (Intel(R) ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) These registers are AHCI-specific and available only on ICH7 components that support AHCI (not on the 82801GB ICH7) and when the ICH7 is properly configured. The Serial ATA Status, Control, and Error registers are special exceptions and may be accessed on all ICH7 components if properly configured (see section Section 12.1.35 for details). The memory mapped registers within the SATA controller exist in non-cacheable memory space. Additionally, locked accesses are not supported. If software attempts to perform locked transactions to the registers, indeterminate results may occur. Register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. The registers are divided into two sections - generic host control and port control. The port control registers are the same for all ports, and there are as many registers banks as there are ports. Table 12-3. AHCI Register Address Map ABAR + Offset 00-1Fh 20h-FFh 100h-17Fh 180h-1FFh 200h-27Fh 280h-2FFh 300h-3FFh Mnemon ic GHC -- P0PCR P1PCR P2PCR P3PCR -- Generic Host Control Reserved Port 0 port control registers Port 1 port control registers (Intel(R) ICH7R and ICH7DH Only) Registers are not available and software must not read or write registers. (Mobile Only) Port 2 port control registers Port 3 port control registers (ICH7R and ICH7DH Only) Registers are not available and software must not read or write registers. (Mobile Only) Reserved Register Intel (R) ICH7 Family Datasheet 523 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.1 AHCI Generic Host Control Registers (D31:F2) Table 12-4. Generic Host Controller Register Address Map ABAR + Offset Mnemonic Register Default DE22FF03h (Intel(R) ICH7R and ICH7DH Only) DE12FF03h (Mobile Only) 00000000h 00000000h 00000000h 00010100h Type 00-03 CAP Host Capabilities R/WO, RO 04-07 08-0Bh 0Ch-0Fh 10h-13h GHC IS PI VS Global ICH7 Control Interrupt Status Ports Implemented AHCI Version R/W R/WC, RO R/WO, RO RO 12.3.1.1 CAP--Host Capabilities Register (D31:F2) Address Offset: ABAR + 00h-03h Attribute: Default Value: DE22FF03h (Desktop Only) Size: DE12FF03h (Mobile Only) R/WO, RO 32 bits All bits in this register that are R/WO are reset only by PLTRST#. Bit Description Supports 64-bit Addressing (S64A) -- RO. Indicates that the SATA controller can access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry are read/write. Supports Command Queue Acceleration (SCQA) -- RO. Hardwired to 1 to indicate that the SATA controller supports SATA command queuing via the DMA Setup FIS. The Intel(R) ICH7 handles DMA Setup FISes natively, and can handle auto-activate optimization through that FIS. Supports SNotification Register (SSNTF): -- RO. The ICH7 SATA Controller does not support the SNotification register. Supports Interlock Switch (SIS) -- R/WO. Indicates whether the SATA controller supports interlock switches on its ports for use in Hot-Plug operations. This value is loaded by platform BIOS prior to OS initialization. If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space. Supports Staggered Spin-up (SSS) -- R/WO. Indicates whether the SATA controller supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by platform BIOS prior to OS initialization. 0 = Staggered spin-up not supported. 1 = Staggered spin-up supported. Supports Aggressive Link Power Management (SALP) -- R/WO. Indicates the SATA controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. 0 = Aggressive link power management not supported. 1 = Aggressive link power management supported. 31 30 29 28 27 26 524 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 25 Description Supports Activity LED (SAL) -- RO. Indicates that the SATA controller supports a single output pin (SATALED#) which indicates activity. Supports Command List Override (SCLO) -- R/WO. When set to 1, indicates that the HBA supports the PxCMD.CLO bit and it's associated function. When cleared to '0', The HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation. Interface Speed Support (ISS) -- R/WO. Indicates the maximum speed the SATA controller can support on its ports. 2h =3.0 Gb/s. Interface Speed Support (ISS) -- RO. Indicates the maximum speed the SATA controller can support on its ports. 1h =1.5 Gb/s. Supports Non-Zero DMA Offsets (SNZO) -- RO. Reserved, as per the AHCI Revision 1.0 specification Supports Port Selector Acceleration -- RO. Port Selectors not supported. Supports Port Multiplier (PMS) -- R/WO. ICH7 does not support port multiplier. BIOS/SW shall write this bit to `0' during AHCI initialization. Supports Port Multiplier FIS Based Switching (PMFS) -- RO. Reserved, as per the AHCI Revision 1.0 specification. NOTE: Port Multiplier not supported by ICH7. 24 23:20 (Desktop Only) 23:20 (Mobile) Only 19 18 17 16 15 14 13 12:8 7:5 4:0 PIO Multiple DRQ Block (PMD) -- R/WO. The SATA controller supports PIO Multiple DRQ Command Block Slumber State Capable (SSC) -- RO. The SATA controller supports the slumber state. Partial State Capable (PSC) -- RO. The SATA controller supports the partial state. Number of Command Slots (NCS) -- RO. Hardwired to 1Fh to indicate support for 32 slots. Reserved. Returns 0. Number of Ports (NPS) -- RO. Hardwired to 3h to indicate support for 4 ports. Note that the number of ports indicated in this field may be more than the number of ports indicated in the PI (ABAR + 0Ch) register. Intel (R) ICH7 Family Datasheet 525 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.1.2 GHC--Global ICH7 Control Register (D31:F2) Address Offset: ABAR + 04h-07h Default Value: 00000000h Bit Attribute: Size: Description R/W 32 bits 31 AHCI Enable (AE) -- R/W. When set, indicates that an AHCI driver is loaded and the controller will be talked to via AHCI mechanisms. This can be used by an Intel(R) ICH7 that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the controller will not be talked to as legacy. When set, software will only talk to the ICH7 using AHCI. The ICH7 will not have to allow command processing via both AHCI and legacy mechanisms. When cleared, software will only talk to the ICH7 using legacy mechanisms. Software shall set this bit to 1 before accessing other AHCI registers. Reserved. Returns 0. Interrupt Enable (IE) -- R/W. This global bit enables interrupts from the ICH7. 0 = All interrupt sources from all ports are disabled. 1 = Interrupts are allowed from the AHCI controller. HBA Reset (HR) -- R/W. Resets ICH7 AHCI controller. 0 = No effect 1 = Causes an internal reset of the ICH7 AHCI controller. All state machines that relate to data transfers and queuing return to an idle condition, and all ports are reinitialized via COMRESET. NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host Controller Interface specification. 30:2 1 0 526 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.1.3 IS--Interrupt Status Register (D31:F2) Address Offset: ABAR + 08h-0Bh Default Value: 00000000h Attribute: Size: R/WC, RO 32 bits This register indicates which of the ports within the controller have an interrupt pending and require service. Bit 31:4 3 (Mobile Only) 3 (Intel(R) ICH7R and ICH7DH Only) Reserved. Returns 0. Reserved. Returns 0. Interrupt Pending Status Port[3] (IPS[3]) -- R/WC. 0 = No interrupt pending. 1 = Port 3 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[2] (IPS[2]) -- R/WC 2 0 = No interrupt pending. 1 = Port 2 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Reserved. Returns 0. Interrupt Pending Status Port[1] (IPS[1]) -- R/WC. 0 = No interrupt pending. 1 = Port 1has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Interrupt Pending Status Port[0] (IPS[0]) -- R/WC. 0 0 = No interrupt pending. 1 = Port 0 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. Description 1 (Mobile Only) 1 (ICH7R and ICH7DH Only) Intel (R) ICH7 Family Datasheet 527 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.1.4 PI--Ports Implemented Register (D31:F2) Address Offset: ABAR + 0Ch-0Fh Default Value: 00000000h Attribute: Size: R/WO, RO 32 bits This register indicates which ports are exposed to the ICH7. It is loaded by platform BIOS. It indicates which ports that the device supports are available for software to use. For ports that are not available, software must not read or write to registers within that port. Bit 31:4 3 (Intel(R) ICH7R and ICH7DH Only) 3 (Mobile Only) 2 1 (ICH7R and ICH7DH Only) 1 (Mobile Only) 0 Reserved. Returns 0. Ports Implemented Port 3 (PI3) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 3 (PI3) -- RO. 0 = The port is not implemented. Ports Implemented Port 2 (PI2)-- R/WO. 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 1 (PI1) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. Ports Implemented Port 1 (PI1) -- RO. 0 = The port is not implemented. Ports Implemented Port 0 (PI0) -- R/WO. 0 = The port is not implemented. 1 = The port is implemented. Description 12.3.1.5 VS--AHCI Version (D31:F2) Address Offset: ABAR + 10h-13h Default Value: 00010100h Attribute: Size: RO 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number. Example: Version 3.12 would be represented as 00030102h. The current version of the specification is 1.10 (00010100h). Bit 31:16 15:0 Description Major Version Number (MJR) -- RO. Indicates the major version is 1 Minor Version Number (MNR) -- RO. Indicates the minor version is 10. 528 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2 Port Registers (D31:F2) Table 12-5. Port [3:0] DMA Register Address Map (Sheet 1 of 2) ABAR + Offset 100h-103h 104h-107h 108h-10Bh 10Ch-10Fh 110h-113h 114h-117h 118h-11Ch 11Ch-11Fh 120h-123h 124h-127h 128h-12Bh 12Ch-12Fh 130h-133h 134h-137h 138h-13Bh 13Ch-17Fh 180h-1FFh (Mobile Only) 180h-183h 184h-187h 188h-18Bh 18Ch-18Fh 190h-193h 194h-197h 198h-19Ch 19Ch-19Fh 1A0h-1A3h 1A4h-1A7h 1A8h-1ABh 1ACh-1AFh 1B0h-1B3h 1B4h-1B7h 1B8h-1BBh 1BCh-1FFh 200h-203h 204h-207h 208h-20Bh Mnemonic P0CLB P0CLBU P0FB P0FBU P0IS P0IE P0CMD -- P0TFD P0SIG P0SSTS P0SCTL P0SERR P0SACT P0CI -- -- P1CLB P1CLBU P1FB P1FBU P1IS P1IE P1CMD -- P1TFD P1SIG P1SSTS P1SCTL P1SERR P1SACT P1CI -- P2CLB P2CLBU P2FB Register Port 0 Command List Base Address Port 0 Command List Base Address Upper 32-Bits Port 0 FIS Base Address Port 0 FIS Base Address Upper 32-Bits Port 0 Interrupt Status Port 0 Interrupt Enable Port 0 Command Reserved Port 0 Task File Data Port 0 Signature Port 0 Serial ATA Status Port 0 Serial ATA Control Port 0 Serial ATA Error Port 0 Serial ATA Active Port 0 Command Issue Reserved Reserved Registers are not available and software must not read from or write to registers. Port 1 Command List Base Address Port 1 Command List Base Address Upper 32-Bits Port 1 FIS Base Address Port 1 FIS Base Address Upper 32-Bits Port 1 Interrupt Status Port 1 Interrupt Enable Port 1 Command Reserved Port 1 Task File Data Port 1 Signature Port 1 Serial ATA Status Port 1 Serial ATA Control Port 1 Serial ATA Error Port 1 Serial ATA Active Port 1 Command Issue Reserved Port 2 Command List Base Address Port 2 Command List Base Address Upper 32-Bits Port 2 FIS Base Address Intel (R) ICH7 Family Datasheet 529 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Table 12-5. Port [3:0] DMA Register Address Map (Sheet 2 of 2) ABAR + Offset 20Ch-20Fh 210h-213h 214h-217h 218h-21Ch 21Ch-21Fh 220h-223h 224h-227h 228h-22Bh 22Ch-22Fh 230h-233h 234h-237h 238h-23Bh 23Ch-27Fh 280h-2FFh (Mobile Only) 280h-283h 284h-287h 288h-28Bh 28Ch-28Fh 290h-293h 294h-297h 298h-29Ch 29Ch-29Fh 2A0h-2A3h 2A4h-2A7h 2A8h-2ABh 2ACh-2AFh 2B0h-2B3h 2B4h-2B7h 2B8h-2BBh 2BCh-2FFh Mnemonic P2FBU P2IS P2IE P2CMD -- P2TFD P2SIG P2SSTS P2SCTL P2SERR P2SACT P2CI -- -- P3CLB P3CLBU P3FB P3FBU P3IS P3IE P3CMD -- P3TFD P3SIG P3SSTS P3SCTL P3SERR P3SACT P3CI -- Register Port 2 FIS Base Address Upper 32-Bits Port 2 Interrupt Status Port 2 Interrupt Enable Port 2 Command Reserved Port 2 Task File Data Port 2 Signature Port 2 Serial ATA Status Port 2 Serial ATA Control Port 2 Serial ATA Error Port 2 Serial ATA Active Port 2 Command Issue Reserved Reserved Registers are not available and software must not read from or write to registers. Port 3 Command List Base Address Port 3 Command List Base Address Upper 32-Bits Port 3 FIS Base Address Port 3 FIS Base Address Upper 32-Bits Port 3 Interrupt Status Port 3 Interrupt Enable Port 3 Command Reserved Port 3 Task File Data Port 3 Signature Port 3 Serial ATA Status Port 3 Serial ATA Control Port 3 Serial ATA Error Port 3 Serial ATA Active Port 3 Command Issue Reserved 530 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.1 PxCLB--Port [3:0] Command List Base Address Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: Undefined Bit + + + + 100h Attribute: R/W, RO 180h (ICH7R and ICH7DH Only) 200h 280h (ICH7R and ICH7DH Only) Size: 32 bits Description 31:10 Command List Base Address (CLB) -- R/W. Indicates the 32-bit base for the command list for this port. This base is used when fetching commands to execute. The structure pointed to by this address range is 1 KB in length. This address must be 1-KB aligned as indicated by bits 31:10 being read/write. Note that these bits are not reset on a HBA reset. Reserved -- RO 9:0 12.3.2.2 PxCLBU--Port [3:0] Command List Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: Undefined Bit + + + + 104h Attribute: R/W 184h (ICH7R and ICH7DH Only) 204h 284h (ICH7R and ICH7DH Only) Size: 32 bits Description 31:0 Command List Base Address Upper (CLBU) -- R/W. Indicates the upper 32-bits for the command list base address for this port. This base is used when fetching commands to execute. Note that these bits are not reset on a HBA reset. 12.3.2.3 PxFB--Port [3:0] FIS Base Address Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: Undefined Bit + + + + 108h Attribute: R/W, RO 188h (ICH7R and ICH7DH Only) 208h 288h (ICH7R and ICH7DH Only) Size: 32 bits Description 31:8 FIS Base Address (FB) -- R/W. Indicates the 32-bit base for received FISes. The structure pointed to by this address range is 256 bytes in length. This address must be 256-byte aligned, as indicated by bits 31:3 being read/write. Note that these bits are not reset on a HBA reset. Reserved -- RO 7:0 Intel (R) ICH7 Family Datasheet 531 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.4 PxFBU--Port [3:0] FIS Base Address Upper 32-Bits Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: Undefined Bit 31:3 2:0 + + + + 10Ch 18Ch 20Ch 28Ch Attribute: R/W Size: Description 32 bits FIS Base Address Upper (FBU) -- R/W. Indicates the upper 32-bits for the received FIS base for this port. Note that these bits are not reset on a HBA reset. Reserved 12.3.2.5 PxIS--Port [3:0] Interrupt Status Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h Bit 31 30 + + + + 110h Attribute: R/WC, RO 190h (ICH7R and ICH7DH Only) 210h 290h (ICH7R and ICH7DH Only Size: 32 bits Description Cold Port Detect Status (CPDS) -- RO. Cold presence not supported. Task File Error Status (TFES) -- R/WC. This bit is set whenever the status register is updated by the device and the error bit (PxTFD.bit 0) is set. Host Bus Fatal Error Status (HBFS) -- R/WC. Indicates that the Intel(R) ICH7 encountered an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would be a target or master abort. Host Bus Data Error Status (HBDS) -- R/WC. Indicates that the ICH7 encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory. Interface Fatal Error Status (IFS) -- R/WC. Indicates that the ICH7 encountered an error on the SATA interface which caused the transfer to stop. Interface Non-fatal Error Status (INFS) -- R/WC. Indicates that the ICH7 encountered an error on the SATA interface but was able to continue operation. Reserved Overflow Status (OFS) -- R/WC. Indicates that the ICH7 received more bytes from a device than was specified in the PRD table for the command. Incorrect Port Multiplier Status (IPMS) -- R/WC. Indicates that the ICH7 received a FIS from a device whose Port Multiplier field did not match what was expected. NOTE: Port Multiplier not supported by ICH7. PhyRdy Change Status (PRCS) -- RO. When set to one indicates the internal PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared. Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber power management states. Partial and slumber must be disabled when Surprise Removal Notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. 29 28 27 26 25 24 23 22 532 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 21:8 Reserved Description 7 Device Interlock Status (DIS) -- R/WC. When set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in the connection state of the device.This bit is only valid in systems that support an interlock switch (CAP.SIS [ABAR+00:bit 28] set). For systems that do not support an interlock switch, this bit will always be 0. Port Connect Change Status (PCS) -- RO. This bit reflects the state of PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when PxSERR.DIAG.X is cleared. 0 = No change in Current Connect Status. 1 = Change in Current Connect Status. 6 5 Descriptor Processed (DPS) -- R/WC. A PRD with the I bit set has transferred all its data. Unknown FIS Interrupt (UFS) -- RO. When set to `1' indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to `0' by software clearing the PxSERR.DIAG.F bit to `0'. Note that this bit does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should wait to act on an unknown FIS until this bit is set to `1' or the two bits may become out of sync. Set Device Bits Interrupt (SDBS) -- R/WC. A Set Device Bits FIS has been received with the I bit set and has been copied into system memory. DMA Setup FIS Interrupt (DSS) -- R/WC. A DMA Setup FIS has been received with the I bit set and has been copied into system memory. PIO Setup FIS Interrupt (PSS) -- R/WC. A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred. Device to Host Register FIS Interrupt (DHRS) -- R/WC. A D2H Register FIS has been received with the I bit set, and has been copied into system memory. 4 3 2 1 0 12.3.2.6 PxIE--Port [3:0] Interrupt Enable Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h + + + + 114h Attribute: R/W, RO 194h (ICH7R and ICH7DH Only) 214h 294h (ICH7R and ICH7DH Only) Size: 32 bits This register enables and disables the reporting of the corresponding interrupt to system software. When a bit is set (`1') and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (`0') are still reflected in the status registers. Bit 31 30 Description Cold Presence Detect Enable (CPDE) -- RO. Cold Presence Detect not supported. Task File Error Enable (TFEE) -- R/W. When set, and GHC.IE and PxTFD.STS.ERR (due to a reception of the error register from a received FIS) are set, the Intel(R) ICH7 will generate an interrupt. Host Bus Fatal Error Enable (HBFE) -- R/W. When set, and GHC.IE and PxS.HBFS are set, the ICH7 will generate an interrupt. 29 Intel (R) ICH7 Family Datasheet 533 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit 28 27 26 25 24 Description Host Bus Data Error Enable (HBDE) -- R/W. When set, and GHC.IE and PxS.HBDS are set, the ICH7 will generate an interrupt. Host Bus Data Error Enable (HBDE) -- R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the ICH7 will generate an interrupt. Interface Non-fatal Error Enable (INFE) -- R/W. When set, GHC.IE is set, and PxIS.INFS is set, the ICH7 will generate an interrupt. Reserved - Should be written as 0 Overflow Error Enable (OFE) -- R/W. When set, and GHC.IE and PxS.OFS are set, the ICH7 will generate an interrupt. Incorrect Port Multiplier Enable (IPME) -- R/W. When set, and GHC.IE and PxIS.IPMS are set, the ICH7 will generate an interrupt. NOTE: Should be written as 0. Port Multiplier not supported by ICH7. PhyRdy Change Interrupt Enable (PRCE) -- R/W. When set, and GHC.IE is set, and PxIS.PRCS is set, the ICH7 shall generate an interrupt. Reserved - Should be written as 0 Device Interlock Enable (DIE) -- R/W. When set, and PxIS.DIS is set, the ICH7 will generate an interrupt. For systems that do not support an interlock switch, this bit shall be a read-only 0. Port Change Interrupt Enable (PCE) -- R/W. When set, and GHC.IE and PxS.PCS are set, the ICH7 will generate an interrupt. Descriptor Processed Interrupt Enable (DPE) -- R/W. When set, and GHC.IE and PxS.DPS are set, the ICH7 will generate an interrupt Unknown FIS Interrupt Enable (UFIE) -- R/W. When set, and GHC.IE is set and an unknown FIS is received, the ICH7 will generate this interrupt. Set Device Bits FIS Interrupt Enable (SDBE) -- R/W. When set, and GHC.IE and PxS.SDBS are set, the ICH7 will generate an interrupt. DMA Setup FIS Interrupt Enable (DSE) -- R/W. When set, and GHC.IE and PxS.DSS are set, the ICH7 will generate an interrupt. PIO Setup FIS Interrupt Enable (PSE) -- R/W. When set, and GHC.IE and PxS.PSS are set, the ICH7 will generate an interrupt. Device to Host Register FIS Interrupt Enable (DHRE) -- R/W. When set, and GHC.IE and PxS.DHRS are set, the ICH7 will generate an interrupt. 23 22 21:8 7 6 5 4 3 2 1 0 534 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.7 PxCMD--Port [3:0] Command Register (D31:F2) Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO Port 1: ABAR + 198h (ICH7R and ICH7DH Only) Port 2: ABAR + 218h Port 3: ABAR + 298h (ICH7R and ICH7DH Only) Default Value: 0000w00wh Size: 32 bits where w = 00?0b (for?, see bit description) Bit Description Interface Communication Control (ICC) -- R/W. This is a four bit field which can be used to control reset and power states of the interface. Writes to this field will cause actions on the interface, either as primitives or an OOB sequence, and the resulting status of the interface will be reported in the PxSSTS register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h). Value Fh-7h 6h 5h-3h 31:28 2h 1h 0h Definition Reserved Slumber: This will cause the Intel(R) ICH7 to request a transition of the interface to the slumber state. The SATA device may reject the request and the interface will remain in its current state Reserved Partial: This will cause the ICH7 to request a transition of the interface to the partial state. The SATA device may reject the request and the interface will remain in its current state. Active: This will cause the ICH7 to request a transition of the interface into the active No-Op / Idle: When software reads this value, it indicates the ICH7 is not in the process of changing the interface state or sending a device reset, and a new link command may be issued. When system software writes a non-reserved value other than No-Op (0h), the ICH7 will perform the action and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (e.g. interface is in the active state and a request is made to go to the active state), the ICH7 will take no action and return this field to Idle. NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or 06h. Aggressive Slumber / Partial (ASP) -- R/W. When set, and the ALPE bit (bit 26) is set, the ICH7 will aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the ICH7 will aggressively enter the partial state when it clears the PxCI register and the PxSACT register is cleared. Aggressive Link Power Management Enable (ALPE) -- R/W. When set, the ICH7 will aggressively enter a lower link power state (partial or slumber) based upon the setting of the ASP bit (bit 27). Drive LED on ATAPI Enable (DLAE) -- R/W. When set, the ICH7 will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the ICH7 will only drive the LED pin active for ATA commands. See Section 5.17.5 for details on the activity LED. HDevice is ATAPI (ATAPI) -- R/W. When set, the connected device is an ATAPI device. This bit is used by the ICH7 to control whether or not to generate the desktop LED when commands are active. See Section 5.17.5 for details on the activity LED. Reserved 27 26 25 24 23:20 Intel (R) ICH7 Family Datasheet 535 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description Interlock Switch Attached to Port (ISP) -- R/WO. When interlock switches are supported in the platform (CAP.SIS [ABAR+00h:bit 28] set), this indicates whether this particular port has an interlock switch attached. This bit can be used by system software to enable such features as aggressive power management, as disconnects can always be detected regardless of PHY state with an interlock switch. When this bit is set, it is expected that HPCP (bit 18) in this register is also set. The ICH7 takes no action on the state of this bit - it is for system software only. For example, if this bit is cleared, and an interlock switch toggles, the ICH7 still treats it as a proper interlock switch event. Note that these bits are not reset on a HBA reset. Hot Plug Capable Port (HPCP) -- R/WO. 0 = Port is not capable of Hot-Plug. 1 = Port is Hot-Plug capable. This indicates whether the platform exposes this port to a device which can be HotPlugged. SATA by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). This bit can be used by system software to indicate a feature such as "eject device" to the end-user. The ICH7 takes no action on the state of this bit - it is for system software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the ICH7 still treats it as a proper Hot-Plug event. Note that these bits are not reset on a HBA reset. Port Multiplier Attached (PMA) -- RO / R/W. When this bit is set, a port multiplier is attached to the ICH7 for this port. When cleared, a port multiplier is not attached to this port. This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS = 1. NOTE: Port Multiplier not supported by ICH7. Port Multiplier FIS Based Switching Enable (PMFSE) -- RO. The ICH7 does not support FIS-based switching. NOTE: Port Multiplier not supported by ICH7. Controller Running (CR) -- RO. When this bit is set, the DMA engines for a port are running. See section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH7. FIS Receive Running (FR) -- RO. When set, the FIS Receive DMA engine for the port is running. See section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the ICH7. Interlock Switch State (ISS) -- RO. For systems that support interlock switches (via CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this register), this bit indicates the current state of the interlock switch. A 0 indicates the switch is closed, and a 1 indicates the switch is opened. For systems that do not support interlock switches, or if an interlock switch is not attached to this port, this bit reports 0. Current Command Slot (CCS) -- RO. Indicates the current command slot the ICH7 is processing. This field is valid when the ST bit is set in this register, and is constantly updated by the ICH7. This field can be updated as soon as the ICH7 recognizes an active command slot, or at some point soon after when it begins processing the command. This field is used by software to determine the current command issue location of the ICH7. In queued mode, software shall not use this field, as its value does not represent the current command being executed. Software shall only use PxCI and PxSACT when running queued commands. Reserved 19 18 17 16 15 14 13 12:8 7:5 536 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description FIS Receive Enable (FRE) -- R/W. When set, the ICH7 may post received FISes into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU (ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by the ICH7, except for the first D2H (device-to-host) register FIS after the initialization sequence. System software must not set this bit until PxFB (PxFBU) have been programmed with a valid pointer to the FIS receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the FR bit (bit 14) in this register to be cleared. Command List Override (CLO) -- R/W. Setting this bit to '1' causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be transmitted to the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The HBA sets this bit to '0' when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to '0'. A write to this register with a value of '0' shall have no effect. This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to '1' from a previous value of '0'. Setting this bit to '1' at any other time is not supported and will result in indeterminate behavior 4 3 2 Power On Device (POD) -- RO. Cold presence detect not supported. Defaults to 1. Spin-Up Device (SUD) -- R/W / RO. This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spin-up (when CAP.SSS is 0). 0 = No action. 1 = On an edge detect from 0 to 1, the ICH7 starts a COMRESET initialization sequence to the device. Start (ST) -- R/W. When set, the ICH7 may process the command list. When cleared, the ICH7 may not process the command list. Whenever this bit is changed from a 0 to a 1, the ICH7 starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI register is cleared by the ICH7 upon the ICH7 putting the controller into an idle state. Refer to section 10.3.1 of the Serial ATA AHCI Specification for important restrictions on when ST can be set to 1. 1 0 Intel (R) ICH7 Family Datasheet 537 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.8 PxTFD--Port [3:0] Task File Data Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 0000007Fh + + + + 120h Attribute: RO 1A0h (ICH7R and ICH7DH Only) 220h 2A0h (ICH7R and ICH7DH Only) Size: 32 bits This is a 32-bit register that copies specific fields of the task file when FISes are received. The FISes that contain this information are: D2H Register FIS PIO Setup FIS Set Device Bits FIS Bit 31:16 15:8 Reserved Error (ERR) -- RO. Contains the latest copy of the task file error register. Status (STS) -- RO. Contains the latest copy of the task file status register. Fields of note in this register that affect AHCI. Bit 7 6:4 7:0 3 2:1 0 Field BSY N/A DRQ N/A ERR Definition Indicates the interface is busy Not applicable Indicates a data transfer is requested Not applicable Indicates an error during the transfer Description 12.3.2.9 PxSIG--Port [3:0] Signature Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: FFFFFFFFh + + + + 124h Attribute: RO 1A4h (ICH7R and ICH7DH Only) 224h 2A4h (ICH7R and ICH7DH Only) Size: 32 bits This is a 32-bit register which contains the initial signature of an attached device when the first D2H Register FIS is received from that device. It is updated once after a reset sequence. Bit Description Signature (SIG) -- RO. Contains the signature received from a device on the first D2H register FIS. The bit order is as follows: Bit 31:0 31:24 23:16 15:8 7:0 Field LBA High Register LBA Mid Register LBA Low Register Sector Count Register 538 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.10 PxSSTS--Port [3:0] Serial ATA Status Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h + + + + 128h Attribute: 1A8h (Desktop Only) 228h 2A8h (Desktop Only) Size: RO 32 bits This is a 32-bit register that conveys the current state of the interface and host. The ICH7 updates it continuously and asynchronously. When the ICH7 transmits a COMRESET to the device, this register is updated to its reset values. Bit 31:12 Reserved Interface Power Management (IPM) -- RO. Indicates the current interface state: Value 0h 11:8 1h 2h 6h Description Device not present or communication not established Interface in active state Interface in PARTIAL power management state Interface in SLUMBER power management state Description All other values reserved. Current Interface Speed (SPD) -- RO. Indicates the negotiated interface communication speed. Value Description 0h 1h 7:4 2h Device not present or communication not established Generation 1 communication rate negotiated Generation 2 communication rate negotiated All other values reserved. Intel(R) ICH7 supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0 Gb/s). ICH7 Mobile SKUs support Generation 1 communication rates (1.5 Gb/sec). Device Detection (DET) -- RO. Indicates the interface device detection and Phy state: Value 0h 3:0 1h 3h 4h Description No device detected and Phy communication not established Device presence detected but Phy communication not established Device presence detected and Phy communication established Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved. Intel (R) ICH7 Family Datasheet 539 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.11 PxSCTL -- Port [3:0] Serial ATA Control Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000004h + + + + 12Ch Attribute: 1ACh (Desktop Only 22Ch 2ACh (Desktop Only) Size: R/W, RO 32 bits This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by the ICH7 or the interface. Reads from the register return the last value written to it. Bit 31:20 19:16 15:12 Reserved Port Multiplier Port (PMP) -- RO. This field is not used by AHCI NOTE: Port Multiplier not supported by Intel(R) ICH7. Select Power Management (SPM) -- RO. This field is not used by AHCI Interface Power Management Transitions Allowed (IPM) -- R/W. Indicates which power states the ICH7 is allowed to transition to: Value 11:8 0h 1h 2h 3h Description No interface restrictions Transitions to the PARTIAL state disabled Transitions to the SLUMBER state disabled Transitions to both PARTIAL and SLUMBER states disabled Description All other values reserved Speed Allowed (SPD) -- R/W. Indicates the highest allowable speed of the interface. This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field. Value 0h 7:4 1h 2h Description No speed negotiation restrictions Limit speed negotiation to Generation 1 communication rate Limit speed negotiation to Generation 2 communication rate All other values reserved ICH7 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0 Gb/s). ICH7 Mobile SKUs support Generation 1 communication rates (1.5 Gb/sec). Device Detection Initialization (DET) -- R/W. Controls the ICH7's device detection and interface initialization. Value 0h 1h 3:0 4h Description No device detection or initialization action requested Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications re-initialized Disable the Serial ATA interface and put Phy in offline mode All other values reserved. When this field is written to a 1h, the ICH7 initiates COMRESET and starts the initialization process. When the initialization is complete, this field shall remain 1h until set to another value by software. This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while the ICH7 is running results in undefined behavior. 540 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.12 PxSERR--Port [3:0] Serial ATA Error Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h Bit + + + + 130h Attribute: R/WC 1B0h (ICH7R and ICH7DH Only) 230h 2B0h (ICH7R and ICH7DH Only) Size: 32 bits Description Diagnostics (DIAG) -- R/WC. Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes: Bits 26 25 24 Description Exchanged (X): When set to one this bit indicates a COMINIT signal was received. This bit is reflected in the interrupt register PxIS.PCS. Unrecognized FIS Type (F): Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. Transport state transition error (T): Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared. Link Sequence Error (S): Indicates that one or more Link state machine error conditions was encountered. The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition. Handshake Error (H): Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. CRC Error (C): Indicates that one or more CRC errors occurred with the Link Layer. Disparity Error (D): This field is not used by AHCI. 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding errors occurred. Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy. Phy Internal Error (I): Indicates that the Phy detected some internal error. PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. In the Intel(R) ICH7, this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it. 31:27Reserved 23 31:16 22 21 20 19 18 17 16 Intel (R) ICH7 Family Datasheet 541 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) Bit Description Error (ERR) -- R/WC. The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bits Description 15:12Reserved 11 10 Internal Error (E): The SATA controller failed due to a master or target abort when attempting to access system memory. Protocol Error (P): A violation of the Serial ATA protocol was detected. Note: The ICH7 does not set this bit for all protocol violations that may occur on the SATA link. Persistent Communication or Data Integrity Error (C): A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. Transient Data Integrity Error (T): A data integrity error occurred that was not recovered by the interface. Reserved Recovered Communications Error (M): Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers. Recovered Data Integrity Error (I): A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. 9 15:0 8 7:2 1 0 12.3.2.13 PxSACT--Port [3:0] Serial ATA Active (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h Bit + + + + 134h Attribute: R/W 1B4h (ICH7R and ICH7DH Only) 234h 2B4h (ICH7R and ICH7DH Only) Size: 32 bits Description 31:0 Device Status (DS) -- R/W. System software sets this bit for SATA queuing operations prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via the Set Device Bits FIS. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software, and as a result of a COMRESET or SRST. 542 Intel (R) ICH7 Family Datasheet SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 12.3.2.14 PxCI--Port [3:0] Command Issue Register (D31:F2) Address Offset: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Default Value: 00000000h Bit + + + + 138h Attribute: R/W 1B8h (ICH7R and ICH7DH Only) 238h 2B8h (ICH7R and ICH7DH Only) Size: 32 bits Description 31:0 Commands Issued (CI) -- R/W. This field is set by software to indicate to the Intel(R) ICH7 that a command has been built-in system memory for a command slot and may be sent to the device. When the ICH7 receives a FIS which clears the BSY and DRQ bits for the command, it clears the corresponding bit in this register for that command slot. This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by software. Intel (R) ICH7 Family Datasheet 543 SATA Controller Registers (D31:F2) (Desktop and Mobile Only) 544 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13 13.1 Note: Note: EHCI Controller Registers (D29:F7) USB EHCI Configuration Registers (USB EHCI--D29:F7) Register address locations that are not shown in Table 13-1 should be treated as Reserved (see Section 6.2 for details). All configuration registers in this section are in the core well and reset by a core well reset and the D3-to-D0 warm reset, except as noted. Table 13-1. USB EHCI PCI Register Address Map (USB EHCI--D29:F7) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Dh 10h-13h 2Ch-2Dh 2Eh-2Fh 34h 3Ch 3Dh 50h 51h 52h-53h 54h-55h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC PMLT MEM_BASE SVID SID CAP_PTR INT_LN INT_PN PWR_CAPID NXT_PTR1 PWR_CAP PWR_CNTL_STS Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Primary Master Latency Timer Memory Base Address USB EHCI Subsystem Vendor Identification USB EHCI Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin PCI Power Management Capability ID Next Item Pointer #1 Power Management Capabilities Power Management Control/Status Default Val ue 8086h See register description. 0000h 0290h See register description 20h 03h 0Ch 00h 00000000h XXXXh XXXXh 50h 00h See register description 01h 58h C9C2h 0000h Type RO RO R/W, RO R/W, RO RO RO RO RO RO R/W, RO R/W (special) R/W (special) RO R/W RO RO R/W (special) R/W (special) R/W, R/WC, RO Intel (R) ICH7 Family Datasheet 545 EHCI Controller Registers (D29:F7) Table 13-1. USB EHCI PCI Register Address Map (USB EHCI--D29:F7) (Sheet 2 of 2) Offset 58h 59h 5Ah-5Bh 60h 61h 62h-63h 64h-67h 68h-6Bh 6Ch-6Fh 70h-73h 74h-7Fh 80h Mnemonic DEBUG_CAPID NXT_PTR2 DEBUG_BASE USB_RELNUM FL_ADJ PWAKE_CAP -- LEG_EXT_CAP LEG_EXT_CS SPECIAL_SMI -- ACCESS_CNTL Register Name Debug Port Capability ID Next Item Pointer #2 Debug Port Base Offset USB Release Number Frame Length Adjustment Port Wake Capabilities Reserved USB EHCI Legacy Support Extended Capability USB EHCI Legacy Extended Support Control/Status Intel Specific USB 2.0 SMI Reserved Access Control Default Val ue 0Ah 00h 20A0h 20h 20h 01FFh -- 00000001h 00000000h 00000000h -- 00h Type RO RO RO RO R/W R/W -- R/W, RO R/W, R/WC, RO R/W, R/WC -- R/W 13.1.1 VID--Vendor Identification Register (USB EHCI--D29:F7) Offset Address: 00h-01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel. 13.1.2 DID--Device Identification Register (USB EHCI--D29:F7) Offset Address: 02h-03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 USB EHCI controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 546 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.3 PCICMD--PCI Command Register (USB EHCI--D29:F7) Address Offset: 0h4-05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable -- R/W. 10 0 = The function is capable of generating interrupts. 1 = The function can not generate its interrupt to the interrupt controller. Note that the corresponding Interrupt Status bit (D29:F7:06h, bit 3) is not affected by the interrupt enable. 9 Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. SERR# Enable (SERR_EN) -- R/W. 8 0 = Disables EHC's capability to generate an SERR#. 1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# when it receive a completion status other than "successful" for one of its DMAinitiated memory reads on DMI (and subsequently on its internal interface). Wait Cycle Control (WCC) -- RO. Hardwired to 0. Parity Error Response (PER) -- RO. 1 = EHCI Host Controller will check for correct parity and halt operation when bad parity is detected during the data phase as recommended by the EHCI specification. If it detects bad parity on the address or command phases when this bit is set to 1, the host controller does not take the cycle, halts the host controller (if currently not halted), and sets the host system error bit in the USBSTS register. Note that this applies to both requests and completions from the system interface. This bit must be set in order for the parity errors to generate SERR#. 5 4 3 2 VGA Palette Snoop (VPS) -- RO. Hardwired to 0. Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. Special Cycle Enable (SCE) -- RO. Hardwired to 0. Bus Master Enable (BME) -- R/W. 0 = Disables this functionality. 1 = Enables the Intel(R) ICH7 to act as a master on the PCI bus for USB transfers. Memory Space Enable (MSE) -- R/W. This bit controls access to the USB 2.0 Memory Space registers. 1 0 = Disables this functionality. 1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F7:10h) for USB 2.0 should be programmed before this bit is set. I/O Space Enable (IOSE) -- RO. Hardwired to 0. Attribute: Size: Description R/W, RO 16 bits 7 6 0 Intel (R) ICH7 Family Datasheet 547 EHCI Controller Registers (D29:F7) 13.1.4 PCISTS--PCI Status Register (USB EHCI--D29:F7) Address Offset: 06h-07h Default Value: 0290h Attribute: Size: R/W, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 Description Detected Parity Error (DPE) -- RO. Hardwired to 0. Signaled System Error (SSE) -- R/W. 14 0 = No SERR# signaled by Intel(R) ICH7. 1 = This bit is set by the ICH7 when it signals SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be 1 for this bit to be set. Received Master Abort (RMA) -- R/W. 13 0 = No master abort received by EHC on a memory access. 1 = This bit is set when EHC, as a master, receives a master abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit. Received Target Abort (RTA) -- R/W. 12 0 = No target abort received by EHC on memory access. 1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit (D29:F7:04h, bit 8). Signaled Target Abort (STA) -- RO. This bit is used to indicate when the EHCI function responds to a cycle with a target abort. There is no reason for this to happen, so this bit will be hardwired to 0. DEVSEL# Timing Status (DEVT_STS) -- RO. This 2-bit field defines the timing for DEVSEL# assertion. Master Data Parity Error Detected (DPED) -- R/W. 8 0 = No data parity error detected on USB2.0 read completion packet. 1 = This bit is set by the ICH7 when a data parity error is detected on a USB 2.0 read completion packet on the internal interface to the EHCI host controller and bit 6 of the Command register is set to 1. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. User Definable Features (UDF) -- RO. Hardwired to 0. 66 MHz Capable (66 MHz _CAP) -- RO. Hardwired to 0. Capabilities List (CAP_LIST) -- RO. Hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. Interrupt Status -- RO. This bit reflects the state of this function's interrupt at the input of the enable/disable logic. 3 0 = This bit will be 0 when the interrupt is de-asserted. 1 = This bit is a 1 when the interrupt is asserted. The value reported in this bit is independent of the value in the Interrupt Enable bit. 2:0 Reserved 11 10:9 7 6 5 4 548 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.5 RID--Revision Identification Register (USB EHCI--D29:F7) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. Intel(R) 13.1.6 PI--Programming Interface Register (USB EHCI--D29:F7) Address Offset: 09h Default Value: 20h Bit 7:0 Attribute: Size: Description RO 8 bits Programming Interface -- RO. A value of 20h indicates that this USB 2.0 host controller conforms to the EHCI Specification. 13.1.7 SCC--Sub Class Code Register (USB EHCI--D29:F7) Address Offset: 0Ah Default Value: 03h Bit 7:0 Sub Class Code (SCC) -- RO. 03h = Universal serial bus host controller. Attribute: Size: Description RO 8 bits 13.1.8 BCC--Base Class Code Register (USB EHCI--D29:F7) Address Offset: 0Bh Default Value: 0Ch Bit 7:0 Base Class Code (BCC) -- RO. 0Ch = Serial bus controller. Attribute: Size: Description RO 8 bits Intel (R) ICH7 Family Datasheet 549 EHCI Controller Registers (D29:F7) 13.1.9 PMLT--Primary Master Latency Timer Register (USB EHCI--D29:F7) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) -- RO. Hardwired to 00h. Because the EHCI controller is internally implemented with arbitration on an interface (and not PCI), it does not need a master latency timer. 13.1.10 MEM_BASE--Memory Base Address Register (USB EHCI--D29:F7) Address Offset: 10h-13h Default Value: 00000000h Bit 31:10 9:4 3 2:1 0 Attribute: Size: Description R/W, RO 32 bits Base Address -- R/W. Bits [31:10] correspond to memory address signals [31:10], respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries. Reserved Prefetchable -- RO. Hardwired to 0 indicating that this range should not be prefetched. Type -- RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. Resource Type Indicator (RTE) -- RO. Hardwired to 0 indicating that the base address field in this register maps to memory space. 13.1.11 SVID--USB EHCI Subsystem Vendor ID Register (USB EHCI--D29:F7) Address Offset: 2Ch-2Dh Default Value: XXXXh Reset: None Bit Attribute: Size: R/W (special) 16 bits Description Subsystem Vendor ID (SVID) -- R/W (special). This register, in combination with the USB 2.0 Subsystem ID register, enables the operating system to distinguish each subsystem from the others. NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7:80h, bit 0) is set to 1. 15:0 550 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.12 SID--USB EHCI Subsystem ID Register (USB EHCI--D29:F7) Address Offset: 2Eh-2Fh Default Value: XXXXh Reset: None Bit Attribute: Size: R/W (special) 16 bits Description Subsystem ID (SID) -- R/W (special). BIOS sets the value in this register to identify the Subsystem ID. This register, in combination with the Subsystem Vendor ID register, enables the operating system to distinguish each subsystem from other(s). NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7:80h, bit 0) is set to 1. 15:0 13.1.13 CAP_PTR--Capabilities Pointer Register (USB EHCI--D29:F7) Address Offset: 34h Default Value: 50h Bit 7:0 Attribute: Size: Description RO 8 bits Capabilities Pointer (CAP_PTR) -- RO. This register points to the starting offset of the USB 2.0 capabilities ranges. 13.1.14 INT_LN--Interrupt Line Register (USB EHCI--D29:F7) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- R/W. This data is not used by the Intel(R) ICH7. It is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. 13.1.15 INT_PN--Interrupt Pin Register (USB EHCI--D29:F7) Address Offset: 3Dh Default Value: See Description Bit 7:0 Attribute: Size: Description RO 8 bits Interrupt Pin -- RO. This reflects the value of D29IP.EIP (Chipset Config Registers:Offset 3108:bits 31:28). NOTE: Bits 7:4 are always 0h Intel (R) ICH7 Family Datasheet 551 EHCI Controller Registers (D29:F7) 13.1.16 PWR_CAPID--PCI Power Management Capability ID Register (USB EHCI--D29:F7) Address Offset: 50h Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Power Management Capability ID -- RO. A value of 01h indicates that this is a PCI Power Management capabilities field. 13.1.17 NXT_PTR1--Next Item Pointer #1 Register (USB EHCI--D29:F7) Address Offset: 51h Default Value: 58h Bit Attribute: Size: Description R/W (special) 8 bits 7:0 Next Item Pointer 1 Value -- R/W (special). This register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. This register is writable when the WRT_RDONLY bit (D29:F7:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port capability registers, if necessary. This register should only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h (Debug Port visible) and 00h (Debug Port invisible) are expected to be programmed in this register. NOTE: Register not reset by D3-to-D0 warm reset. 13.1.18 PWR_CAP--Power Management Capabilities Register (USB EHCI--D29:F7) Address Offset: 52h-53h Default Value: C9C2h Bit Attribute: Size: Description R/W (special) 16 bits 15:11 PME Support (PME_SUP) -- R/W (special). This 5-bit field indicates the power states in which the function may assert PME#. The Intel(R) ICH7 EHC does not support the D1 or D2 states. For all other states, the ICH7 EHC is capable of generating PME#. Software should not need to modify this field. D2 Support (D2_SUP) -- R/W (special). 0 = D2 State is not supported 1 = D2 State is supported D1 Support (D1_SUP) -- R/W (special). 0 = D1 State is not supported 1 = D1 State is supported Auxiliary Current (AUX_CUR) -- R/W (special). The ICH7 EHC reports 375 mA maximum suspend well current required when in the D3COLD state. This value can be written by BIOS when a more accurate value is known. Device Specific Initialization (DSI)-- R/W (special). The ICH7 reports 0, indicating that no device-specific initialization is required. 10 9 8:6 5 552 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) Bit 4 3 2:0 Reserved Description PME Clock (PME_CLK) -- R/W (special). The ICH7 reports 0, indicating that no PCI clock is required to generate PME#. Version (VER) -- R/W (special). The ICH7 reports 010b, indicating that it complies with Revision 1.1 of the PCI Power Management Specification. NOTES: 1. Normally, this register is read-only to report capabilities to the power management software. To report different power management capabilities, depending on the system in which the ICH7 is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit (D29:F7:80h, bit 0) is set. The value written to this register does not affect the hardware other than changing the value returned during a read. 2. Reset: core well, but not D3-to-D0 warm reset. 13.1.19 PWR_CNTL_STS--Power Management Control/ Status Register (USB EHCI--D29:F7) Address Offset: 54h-55h Default Value: 0000h Bit PME Status -- R/WC. 0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled). 1 = This bit is set when the Intel(R) ICH7 EHC would normally assert the PME# signal independent of the state of the PME_En bit. NOTE: This bit must be explicitly cleared by the operating system each time the operating system is loaded. 14:13 12:9 Data Scale -- RO. Hardwired to 00b indicating it does not support the associated Data register. Data Select -- RO. Hardwired to 0000b indicating it does not support the associated Data register. PME Enable -- R/W. 0 = Disable. 1 = Enable. Enables ICH7 EHC to generate an internal PME signal when PME_Status is 1. NOTE: This bit must be explicitly cleared by the operating system each time it is initially loaded. 7:2 Reserved Attribute: Size: Description R/W, R/WC, RO 16 bits 15 8 Intel (R) ICH7 Family Datasheet 553 EHCI Controller Registers (D29:F7) Bit Description Power State -- R/W. This 2-bit field is used both to determine the current power state of EHC function and to set a new power state. The definition of the field values are: 00 = D0 state 11 = D3HOT state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. When in the D3HOT state, the ICH7 must not accept accesses to the EHC memory range; but the configuration space must still be accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically, the PIRQH is not asserted by the ICH7 when not in the D0 state. When software changes this value from the D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. 1:0 NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset. 13.1.20 DEBUG_CAPID--Debug Port Capability ID Register (USB EHCI--D29:F7) Address Offset: 58h Default Value: 0Ah Bit 7:0 Attribute: Size: Description RO 8 bits Debug Port Capability ID -- RO. Hardwired to 0Ah indicating that this is the start of a Debug Port Capability structure. 13.1.21 NXT_PTR2--Next Item Pointer #2 Register (USB EHCI--D29:F7) Address Offset: 59h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Next Item Pointer 2 Capability -- RO. Hardwired to 00h to indicate there are no more capability structures in this function. 13.1.22 DEBUG_BASE--Debug Port Base Offset Register (USB EHCI--D29:F7) Address Offset: 5Ah-5Bh Default Value: 20A0h Bit 15:13 12:0 Attribute: Size: Description RO 16 bits BAR Number -- RO. Hardwired to 001b to indicate the memory BAR begins at offset 10h in the EHCI configuration space. Debug Port Offset -- RO. Hardwired to 0A0h to indicate that the Debug Port registers begin at offset A0h in the EHCI memory range. 554 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.23 USB_RELNUM--USB Release Number Register (USB EHCI--D29:F7) Address Offset: 60h Default Value: 20h Bit 7:0 Attribute: Size: Description RO 8 bits USB Release Number -- RO. A value of 20h indicates that this controller follows Universal Serial Bus (USB) Specification, Revision 2.0. 13.1.24 FL_ADJ--Frame Length Adjustment Register (USB EHCI--D29:F7) Address Offset: 61h Default Value: 20h Attribute: Size: R/W 8 bits This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. This register should only be modified when the HChalted bit (D29:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host controller is operating yields undefined results. It should not be reprogrammed by USB system software unless the default or BIOS programmed values are incorrect, or the system is restoring the register while returning from a suspended state. These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset. Bit 7:6 Description Reserved -- RO. These bits are reserved for future use and should read as 00b. Frame Length Timing Value -- R/W. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Frame Length (# 480 MHz Clocks) (decimal) 59488 5:0 59504 59520 -- 59984 60000 -- 60480 60496 Frame Length Timing Value (this register) (decimal) 0 1 2 -- 31 32 -- 62 63 Intel (R) ICH7 Family Datasheet 555 EHCI Controller Registers (D29:F7) 13.1.25 PWAKE_CAP--Port Wake Capability Register (USB EHCI--D29:F7) Address Offset: 62-63h Default Value: 01FFh Attribute: Size: R/W 16 bits This register is in the suspend power well. The intended use of this register is to establish a policy about which ports are to be used for wake events. Bit positions 1-8 in the mask correspond to a physical port implemented on the current EHCI controller. A 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect or overcurrent events as wake-up events. This is an information-only mask register. The bits in this register do not affect the actual operation of the EHCI host controller. The systemspecific policy can be established by BIOS initializing this register to a system-specific value. System software uses the information in this register when enabling devices and ports for remote wake-up. These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 15:9 8:1 Reserved -- RO. Port Wake Up Capability Mask -- R/W. Bit positions 1 through 8 correspond to a physical port implemented on this host controller. For example, bit position 1 corresponds to port 0, bit position 2 corresponds to port 1, etc. Port Wake Implemented -- R/W. A 1 in this bit indicates that this register is implemented to software. Description 0 13.1.26 LEG_EXT_CAP--USB EHCI Legacy Support Extended Capability Register (USB EHCI--D29:F7) Address Offset: 68-6Bh Default Value: 00000001h Power Well: Suspend Attribute: Size: R/W, RO 32 bits NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31:25 24 23:17 16 Reserved -- RO. Hardwired to 00h HC OS Owned Semaphore -- R/W. System software sets this bit to request ownership of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS Owned Semaphore bit reads as clear. Reserved -- RO. Hardwired to 00h HC BIOS Owned Semaphore -- R/W. The BIOS sets this bit to establish ownership of the EHCI controller. System BIOS will clear this bit in response to a request for ownership of the EHCI controller by system software. Next EHCI Capability Pointer -- RO. Hardwired to 00h to indicate that there are no EHCI Extended Capability structures in this device. Capability ID -- RO. Hardwired to 01h to indicate that this EHCI Extended Capability is the Legacy Support Capability. Description 15:8 7:0 556 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.27 LEG_EXT_CS--USB EHCI Legacy Support Extended Control / Status Register (USB EHCI--D29:F7) Address Offset: 6C-6Fh Default Value: 00000000h Power Well: Suspend Attribute: Size: R/W, R/WC, RO 32 bits NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31 Description SMI on BAR -- R/WC. Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written. 1 = This bit is set to 1 when the Base Address Register (BAR) is written. SMI on PCI Command -- R/WC. Software clears this bit by writing a 1 to it. 30 0 = PCI Command (PCICMD) Register Not written. 1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written. SMI on OS Ownership Change -- R/WC. Software clears this bit by writing a 1 to it. 29 0 = No HC OS Owned Semaphore bit change. 1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP register (D29:F7:68h, bit 24) transitions from 1 to 0 or 0 to 1. Reserved -- RO. Hardwired to 00h SMI on Async Advance -- RO. This bit is a shadow bit of the Interrupt on Async Advance bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register. 21 NOTE: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the USB2.0_STS register. SMI on Host System Error -- RO. This bit is a shadow bit of Host System Error bit in the USB2.0_STS register (D29:F7:CAPLENGTH + 24h, bit 4). 20 NOTE: To clear this bit system software must write a 1 to the Host System Error bit in the USB2.0_STS register. SMI on Frame List Rollover -- RO. This bit is a shadow bit of Frame List Rollover bit (D29:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register. 19 NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in the USB2.0_STS register. SMI on Port Change Detect -- RO. This bit is a shadow bit of Port Change Detect bit (D29:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register. 18 NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in the USB2.0_STS register. SMI on USB Error -- RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT) bit (D29:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register. 17 NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the USB2.0_STS register. SMI on USB Complete -- RO. This bit is a shadow bit of USB Interrupt (USBINT) bit (D29:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register. 16 NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the USB2.0_STS register. 28:22 Intel (R) ICH7 Family Datasheet 557 EHCI Controller Registers (D29:F7) Bit SMI on BAR Enable -- R/W. 15 Description 0 = Disable. 1 = Enable. When this bit is 1 and SMI on BAR (D29:F7:6Ch, bit 31) is 1, then the host controller will issue an SMI. SMI on PCI Command Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7:6Ch, bit 30) is 1, then the host controller will issue an SMI. SMI on OS Ownership Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7:6Ch, bit 29) is 1, the host controller will issue an SMI. Reserved -- RO. Hardwired to 00h SMI on Async Advance Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately. SMI on Host System Error Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7:6Ch, bit 20) is a 1, the host controller will issue an SMI. SMI on Frame List Rollover Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7:6Ch, bit 19) is a 1, the host controller will issue an SMI. SMI on Port Change Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7:6Ch, bit 18) is a 1, the host controller will issue an SMI. SMI on USB Error Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7:6Ch, bit 17) is a 1, the host controller will issue an SMI immediately. SMI on USB Complete Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately. 14 13 12:6 5 4 3 2 1 0 558 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.1.28 SPECIAL_SMI--Intel Specific USB 2.0 SMI Register (USB EHCI--D29:F7) Address Offset: 70h-73h Default Value: 00000000h Power Well: Suspend Attribute: Size: R/W, R/WC 32 bits NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit 31:30 Reserved -- RO. Hardwired to 00h SMI on PortOwner -- R/WC. Software clears these bits by writing a 1 to it. 29:22 0 = No Port Owner bit change. 1 = Bits 29:22 correspond to the Port Owner bits for ports 1 (22) through 8 (29). These bits are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0. SMI on PMCSR -- R/WC. Software clears these bits by writing a 1 to it. 21 0 = Power State bits Not modified. 1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR) register (D29:F7:54h). SMI on Async -- R/WC. Software clears these bits by writing a 1 to it. 20 0 = No Async Schedule Enable bit change 1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1. SMI on Periodic -- R/WC. Software clears this bit by writing a 1 it. 19 0 = No Periodic Schedule Enable bit change. 1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1. SMI on CF -- R/WC. Software clears this bit by writing a 1 it. 18 0 = No Configure Flag (CF) change. 1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1. SMI on HCHalted -- R/WC. Software clears this bit by writing a 1 it. 17 0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared). 1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared). SMI on HCReset -- R/WC. Software clears this bit by writing a 1 it. 16 15:14 0 = HCRESET did Not transitioned to 1. 1 = HCRESET transitioned to 1. Reserved -- RO. Hardwired to 00h SMI on PortOwner Enable -- R/W. 13:6 0 = Disable. 1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits are 1, then the host controller will issue an SMI. Unused ports should have their corresponding bits cleared. SMI on PMSCR Enable -- R/W. 5 0 = Disable. 1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue an SMI. SMI on Async Enable -- R/W. 4 0 = Disable. 1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue an SMI Description Intel (R) ICH7 Family Datasheet 559 EHCI Controller Registers (D29:F7) Bit SMI on Periodic Enable -- R/W. 3 Description 0 = Disable. 1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will issue an SMI. SMI on CF Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an SMI. SMI on HCHalted Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will issue an SMI. SMI on HCReset Enable -- R/W. 0 = Disable. 1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue an SMI. 2 1 0 13.1.29 ACCESS_CNTL--Access Control Register (USB EHCI--D29:F7) Address Offset: Default Value: Bit 7:1 Reserved WRT_RDONLY -- R/W. When set to 1, this bit enables a select group of normally readonly registers in the EHC function to be written by software. Registers that may only be written when this mode is entered are noted in the summary tables and detailed description as "Read/Write-Special". The registers fall into two categories: 1. System-configured parameters, and 2. Status bits 80h 00h Attribute: Size: Description R/W 8 bits 0 560 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2 Memory-Mapped I/O Registers The EHCI memory-mapped I/O space is composed of two sets of registers: Capability Registers and Operational Registers. Note: The ICH7 EHCI controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. The locked transactions should not be forwarded to PCI as the address space is known to be allocated to USB. When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory range are ignored and result a master abort. Similarly, if the Memory Space Enable (MSE) bit (D29:F7:04h, bit 1) is not set in the Command register in configuration space, the memory range will not be decoded by the ICH7 enhanced host controller (EHC). If the MSE bit is not set, then the ICH7 must default to allowing any memory accesses for the range specified in the BAR to go to PCI. This is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. Note: 13.2.1 Host Controller Capability Registers These registers specify the limits, restrictions and capabilities of the host controller implementation. Within the host controller capability registers, only the structural parameters register is writable. These registers are implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset. Table 13-2. Enhanced Host Controller Capability Registers MEM_BAS E + Offset 00h 02h-03h Mnemonic CAPLENGTH HCIVERSION Register Capabilities Registers Length Host Controller Interface Version Number Host Controller Structural Parameters Host Controller Capability Parameters Default 20h 0100h Type RO RO R/W (special), RO RO 04h-07h 08h-0Bh HCSPARAMS HCCPARAMS 00104208h 00006871h NOTE: "Read/Write Special" means that the register is normally read-only, but may be written when the WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during initialization, their contents must not get modified by HCRESET or D3-toD0 internal reset. 13.2.1.1 CAPLENGTH--Capability Registers Length Register Offset: Default Value: Bit MEM_BASE + 00h 20h Attribute: Size: Description RO 8 bits 7:0 Capability Register Length Value -- RO. This register is used as an offset to add to the Memory Base Register (D29:F7:10h) to find the beginning of the Operational Register Space. This field is hardwired to 20h indicating that the Operation Registers begin at offset 20h. Intel (R) ICH7 Family Datasheet 561 EHCI Controller Registers (D29:F7) 13.2.1.2 HCIVERSION--Host Controller Interface Version Number Register Offset: Default Value: Bit 15:0 MEM_BASE + 02h-03h 0100h Attribute: Size: Description RO 16 bits Host Controller Interface Version Number -- RO. This is a two-byte register containing a BCD encoding of the version number of interface that this host controller interface conforms. 13.2.1.3 HCSPARAMS--Host Controller Structural Parameters Offset: Default Value: MEM_BASE + 04h-07h 00104208h Attribute: Size: R/W (special), RO 32 bits Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET. Bit 31:24 23:20 19:16 Reserved -- RO. Default=0h. Debug Port Number (DP_N) -- RO (special). Hardwired to 1h indicating that the Debug Port is on the lowest numbered port on the Intel(R) ICH7. Reserved Number of Companion Controllers (N_CC) -- R/W (special). This field indicates the number of companion controllers associated with this USB EHCI host controller. A 0 in this field indicates there are no companion host controllers. Port-ownership handoff is not supported. Only high-speed devices are supported on the host controller root ports. 15:12 A value of 1 or more in this field indicates there are companion USB UHCI host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports. The ICH7 allows the default value of 4h to be over-written by BIOS. When removing classic controllers, they should be disabled in the following order: Function 3, Function 2, Function 1, and Function 0, which correspond to ports 7:6, 5:4, 3:2, and 1:0, respectively. 11:8 7:4 Number of Ports per Companion Controller (N_PCC) -- RO. Hardwired to 2h. This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software. Reserved. These bits are reserved and default to 0. N_PORTS -- R/W (special). This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space. Valid values are in the range of 1h to Fh. The ICH7 reports 8h by default. However, software may write a value less than 8 for some platform configurations. A 0 in this field is undefined. NOTE: This register is writable when the WRT_RDONLY bit is set. Description 3:0 562 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2.1.4 HCCPARAMS--Host Controller Capability Parameters Register Offset: Default Value: Bit 31:16 15:8 Reserved EHCI Extended Capabilities Pointer (EECP) -- RO. This field is hardwired to 68h, indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI configuration space. Isochronous Scheduling Threshold -- RO. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. Refer to the EHCI specification for details on how software uses this information for scheduling isochronous transfers. This field is hardwired to 7h. 3 2 Reserved. These bits are reserved and should be set to 0. Asynchronous Schedule Park Capability -- RO. This bit is hardwired to 0 indicating that the host controller does not support this optional feature Programmable Frame List Flag -- RO. 0 = System software must use a frame list length of 1024 elements with this host controller. The USB2.0_CMD register (D29:F7:CAPLENGTH + 20h, bits 3:2) Frame List Size field is a read-only register and must be set to 0. 1 = System software can specify and use a smaller frame list and configure the host controller via the USB2.0_CMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. 64-bit Addressing Capability -- RO. This field documents the addressing range capability of this implementation. The value of this field determines whether software should use the 32-bit or 64-bit data structures. Values for this field have the following interpretation: 0 0 = Data structures using 32-bit address memory pointers 1 = Data structures using 64-bit address memory pointers This bit is hardwired to 1. NOTE: Intel(R) ICH7 only implements 44 bits of addressing. Bits 63:44 will always be 0. MEM_BASE + 08h-0Bh 00006871h Attribute: Size: Description RO 32 bits 7:4 1 Intel (R) ICH7 Family Datasheet 563 EHCI Controller Registers (D29:F7) 13.2.2 Host Controller Operational Registers This section defines the enhanced host controller operational registers. These registers are located after the capabilities registers. The operational register base must be DWord-aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address of the enhanced host controller register address space (MEM_BASE). Since CAPLENGTH is always 20h, Table 13-3 already accounts for this offset. All registers are 32 bits in length. Table 13-3. Enhanced Host Controller Operational Register Address Map MEM_BAS E + Offset 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-5Fh 60h-63h 64h-67h 68h-6Bh 6Ch-6Fh 70h-73h 74h-77h 78h-7Bh 7Ch-7Fh 80h-83h 84h-9Fh A0h-B3h B4h-3FFh Mnemonic USB2.0_CMD USB2.0_STS USB2.0_INTR FRINDEX CTRLDSSEGM ENT PERODICLIST BASE ASYNCLISTAD DR -- CONFIGFLAG PORT0SC PORT1SC PORT2SC PORT3SC PORT4SC PORT5SC PORT6SC PORT7SC -- -- -- Register Name USB 2.0 Command USB 2.0 Status USB 2.0 Interrupt Enable USB 2.0 Frame Index Control Data Structure Segment Period Frame List Base Address Current Asynchronous List Address Reserved Configure Flag Port 0 Status and Control Port 1 Status and Control Port 2 Status and Control Port 3 Status and Control Port 4 Status and Control Port 5 Status and Control Port 6 Status and Control Port 7 Status and Control Reserved Debug Port Registers Reserved Default 00080000h 00001000h 00000000h 00000000h 00000000h 00000000h 00000000h 0h 00000000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h 00003000h Undefined Undefined Undefined Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend Special Notes Type R/W, RO R/WC, RO R/W R/W, R/W, RO R/W R/W RO R/W R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO R/W, R/WC, RO RO See register description RO Note: Software must read and write these registers using only DWord accesses.These registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are 564 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) implemented in the core power well. Unless otherwise noted, the core well registers are reset by the assertion of any of the following: * Core well hardware reset * HCRESET * D3-to-D0 reset The second set at offsets MEM_BASE + 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: * Suspend well hardware reset * HCRESET 13.2.2.1 USB2.0_CMD--USB 2.0 Command Register Offset: Default Value: Bit 31:24 MEM_BASE + 20-23h 00080000h Attribute: Size: Description R/W, RO 32 bits Reserved. These bits are reserved and should be set to 0 when writing this register. Interrupt Threshold Control -- R/W. System software uses this field to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value 00h 01h Maximum Interrupt Interval Reserved 1 micro-frame 2 micro-frames 4 micro-frames 8 micro-frames (default, equates to 1 ms) 16 micro-frames (2 ms) 32 micro-frames (4 ms) 64 micro-frames (8 ms) 23:16 02h 04h 08h 10h 20h 40h 15:8 11:8 7 Reserved. These bits are reserved and should be set to 0 when writing this register. Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host controller does not support this optional feature. Light Host Controller Reset -- RO. Hardwired to 0. The Intel(R) ICH7 does not implement this optional reset. Intel (R) ICH7 Family Datasheet 565 EHCI Controller Registers (D29:F7) Bit Description Interrupt on Async Advance Doorbell -- R/W. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register to a 1. 1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance Enable bit in the USB2.0_INTR register (D29:F7:CAPLENGTH + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the next interrupt threshold. See the EHCI specification for operational details. NOTE: Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. Asynchronous Schedule Enable -- R/W. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Periodic Schedule Enable -- R/W. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Frame List Size -- RO. The ICH7 hardwires this field to 00b because it only supports the 1024-element frame list size. Host Controller Reset (HCRESET) -- R/W. This control bit used by software to reset the host controller. The effects of this on root hub registers are similar to a Chip Hardware Reset (i.e., RSMRST# assertion and PWROK deassertion on the ICH7). When software writes a 1 to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. NOTE: PCI configuration registers and Host controller capability registers are not effected by this reset. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects described in the EHCI spec. Software must re-initialize the host controller in order to return the host controller to an operational state. This bit is set to 0 by the host controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Software should not set this bit to a 1 when the HCHalted bit (D29:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to reset an actively running host controller will result in undefined behavior. This reset me be used to leave EHCI port test modes. 6 5 4 3:2 1 566 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) Bit Run/Stop (RS) -- R/W. Description 0 = Stop (default) 1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host controller continues execution as long as this bit is set. When this bit is set to 0, the Host controller completes the current transaction on the USB and then halts. The HCHalted bit in the USB2.0_STS register indicates when the Host controller has finished the transaction and has entered the stopped state. Software should not write a 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately when the Run bit is set. 0 The following table explains how the different combinations of Run and Halted should be interpreted: Run/Stop 0b 0b 1b 1b Halted 0b 1b 0b 1b Interpretation In the process of halting Halted Running Invalid - the HCHalted bit clears immediately Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being cleared. NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. Intel (R) ICH7 Family Datasheet 567 EHCI Controller Registers (D29:F7) 13.2.2.2 USB2.0_STS--USB 2.0 Status Register Offset: Default Value: MEM_BASE + 24h-27h 00001000h Attribute: Size: R/WC, RO 32 bits This register indicates pending interrupts and various states of the Host controller. The status resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts description in section 4 of the EHCI specification for additional information concerning USB 2.0 interrupt conditions. Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect. Bit 31:16 Description Reserved. These bits are reserved and should be set to 0 when writing this register. Asynchronous Schedule Status RO. This bit reports the current real status of the Asynchronous Schedule. 0 = Status of the Asynchronous Schedule is disabled. (Default) 1 = Status of the Asynchronous Schedule is enabled. 15 NOTE: The Host controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit (D29:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Periodic Schedule Status RO. This bit reports the current real status of the Periodic Schedule. 0 = Status of the Periodic Schedule is disabled. (Default) 1 = Status of the Periodic Schedule is enabled. 14 NOTE: The Host controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit (D29:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Reclamation RO. 0=Default. This read-only status bit is used to detect an empty asynchronous schedule. The operational model and valid transitions for this bit are described in Section 4 of the EHCI Specification. HCHalted RO. 12 0 = This bit is a 0 when the Run/Stop bit is a 1. 1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host controller hardware (e.g., internal error). (Default) Reserved Interrupt on Async Advance -- R/WC. 0=Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit (D29:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the assertion of that interrupt source. 13 11:6 5 568 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) Bit Host System Error -- R/WC. Description 0 = No serious error occurred during a host system access involving the Host controller module 1 = The Host controller sets this bit to 1 when a serious error occurs during a host system access involving the Host controller module. A hardware interrupt is generated to the system. Memory read cycles initiated by the EHC that receive any status other than Successful will result in this bit being set. When this error occurs, the Host controller clears the Run/Stop bit in the USB2.0_CMDregister (D29:F7:CAPLENGTH + 20h, bit 0) to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system (if enabled in the Interrupt Enable Register). Frame List Rollover -- R/WC. 0 = No Frame List Index rollover from its maximum value to 0. 1 = The Host controller sets this bit to a 1 when the Frame List Index (see Section) rolls over from its maximum value to 0. Since the Intel(R) ICH7 only supports the 1024entry Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles. Port Change Detect -- R/WC. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/disable change and connect status change). Regardless of the implementation, when this bit is readable (i.e., in the D0 state), it must provide a valid view of the Port Status registers. 0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. 1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. USB Error Interrupt (USBERRINT) -- R/WC. 0 = No error condition. 1 = The Host controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a list of the USB errors that will result in this interrupt being asserted. USB Interrupt (USBINT) -- R/WC. 0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set. No short packet is detected. 1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set. The Host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). 4 3 2 1 0 Intel (R) ICH7 Family Datasheet 569 EHCI Controller Registers (D29:F7) 13.2.2.3 USB2.0_INTR--USB 2.0 Interrupt Enable Register Offset: Default Value: MEM_BASE + 28h-2Bh 00000000h Attribute: Size: R/W 32 bits This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USB2.0_STS Register to allow the software to poll for events. Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see Section 4 of the EHCI specification), or not. Bit 31:6 Description Reserved. These bits are reserved and should be 0 when writing this register. Interrupt on Async Advance Enable -- R/W. 5 0 = Disable. 1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. Host System Error Enable -- R/W. 4 0 = Disable. 1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F7:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. Frame List Rollover Enable -- R/W. 3 0 = Disable. 1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Port Change Interrupt Enable -- R/W. 2 0 = Disable. 1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. USB Error Interrupt Enable -- R/W. 1 0 = Disable. 1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBERRINT bit in the USB2.0_STS register. USB Interrupt Enable -- R/W. 0 0 = Disable. 1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software by clearing the USBINT bit in the USB2.0_STS register. 570 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2.2.4 FRINDEX--Frame Index Register Offset: Default Value: MEM_BASE + 2Ch-2Fh 00000000h Attribute: Size: R/W 32 bits The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value management requirements on the host controller. The value of FRINDEX must be within 125 s (1 micro-frame) ahead of the SOF token value. The SOF value may be implemented as an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames. (1 millisecond). An example implementation to achieve this behavior is to increment SOFV each time the FRINDEX[2:0] increments from 0 to 1. Software must use the value of FRINDEX to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get micro-frame number function required to client drivers. Therefore, the value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible, software should not write a FRINDEX value where the three least significant bits are 111b or 000b. Note: This register is used by the host controller to index into the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [12:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index is fixed at 10 for the ICH7 since it only supports 1024-entry frame lists. This register must be written as a DWord. Word and byte writes produce undefined results. This register cannot be written unless the Host controller is in the Halted state as indicated by the HCHalted bit (D29:F7:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit (D29:F7:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register) produces undefined results. Writes to this register also effect the SOF value. See Section 4 of the EHCI specification for details. Bit 31:14 Reserved Frame List Current Index/Frame Number -- R/W. The value in this register increments at the end of each time frame (e.g., micro-frame). 13:0 Bits [12:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. Description Intel (R) ICH7 Family Datasheet 571 EHCI Controller Registers (D29:F7) 13.2.2.5 CTRLDSSEGMENT--Control Data Structure Segment Register Offset: Default Value: MEM_BASE + 30h-33h 00000000h Attribute: Size: R/W, RO 32 bits This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. Since the ICH7 hardwires the 64-bit Addressing Capability field in HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register allows the host software to locate all control data structures within the same 4 GB memory segment. Bit 31:12 11:0 Description Upper Address[63:44] -- RO. Hardwired to 0s. The Intel(R) ICH7 EHC is only capable of generating addresses up to 16 terabytes (44 bits of address). Upper Address[43:32] -- R/W. This 12-bit field corresponds to address bits 43:32 when forming a control data structure address. 13.2.2.6 PERIODICLISTBASE--Periodic Frame List Base Address Register Offset: Default Value: MEM_BASE + 34h-37h 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. Since the ICH7 host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the schedule execution by the host controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host controller to step through the Periodic Frame List in sequence. Bit 31:12 11:0 Description Base Address (Low) -- R/W. These bits correspond to memory address signals [31:12], respectively. Reserved. Must be written as 0s. During runtime, the value of these bits are undefined. 572 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2.2.7 ASYNCLISTADDR--Current Asynchronous List Address Register Offset: Default Value: MEM_BASE + 38h-3Bh 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the address of the next asynchronous queue head to be executed. Since the ICH7 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by system software and will always return 0's when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. Bit 31:5 4:0 Description Link Pointer Low (LPL) -- R/W. These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH). Reserved. These bits are reserved and their value has no effect on operation. 13.2.2.8 CONFIGFLAG--Configure Flag Register Offset: Default Value: MEM_BASE + 60h-63h 00000000h Attribute: Size: R/W 32 bits This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. Bit 31:1 Description Reserved. Read from this field will always return 0. Configure Flag (CF) -- R/W. Host software sets this bit as the last action in its process of configuring the Host controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. See section 4 of the EHCI spec for operation details. 0 = Port routing control logic default-routes each port to the classic host controllers (default). 1 = Port routing control logic default-routes all ports to this host controller. 0 13.2.2.9 PORTSC--Port N Status and Control Register Offset: Port 0: MEM_BASE Port 1: MEM_BASE Port 2: MEM_BASE Port 3: MEM_BASE Port 4: MEM_BASE Port 5: MEM_BASE Port 6: MEM_BASE Port 7: MEM_BASE R/W, R/WC, RO 00003000h + + + + + + + + 64h-67h 68-6Bh 6C-6Fh 70-73h 74-77h 78-7Bh 7C-7Fh 80-83h Size: 32 bits Attribute: Default Value: A host controller must implement one or more port registers. Software uses the N_Port information from the Structural Parameters Register to determine how many ports need to be serviced. All ports have the structure defined below. Software must not write to unreported Port Status and Control Registers. Intel (R) ICH7 Family Datasheet 573 EHCI Controller Registers (D29:F7) This register is in the suspend power well. It is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. The initial conditions of a port are: * No device connected * Port disabled. When a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. Refer to Section 4 of the EHCI specification for operational requirements for how change events interact with port suspend mode. Bit 31:23 Description Reserved. These bits are reserved for future use and will return a value of 0's when read. Wake on Overcurrent Enable (WKOC_E) -- R/W. 22 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of this register) is set. Wake on Disconnect Enable (WKDSCNNT_E) -- R/W. 21 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0). Wake on Connect Enable (WKCNNT_E) -- R/W. 20 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power Management Control/Status Register (offset 54, bit 15) when the Current Connect Status changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1). Port Test Control -- R/W. When this field is 0's, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode bits are (0110b - 1111b are reserved): Value 19:16 0000b 0001b 0010b 0011b 0100b 0101b Maximum Interrupt Interval Test mode not enabled (default) Test J_STATE Test K_STATE Test SE0_NAK Test Packet FORCE_ENABLE Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode. 15:14 Reserved -- R/W. Should be written to =00b. Port Owner -- R/W. Default = 1b. This bit unconditionally goes to a 0 when the Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition. 13 System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that a companion host controller owns and controls the port. See Section 4 of the EHCI Specification for operational details. 574 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) Bit 12 Description Port Power (PP) -- RO. Read-only with a value of 1. This indicates that the port does have power. Line Status-- RO.These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is set to a 1. 00 10 01 11 = = = = SE0 J-state K-state Undefined 11:10 9 Reserved. This bit will return a 0 when read. Port Reset -- R/W. Default = 0. When software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0. 1 = Port is in Reset. 0 = Port is not in Reset. NOTE: When software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. The bit status will not read as a 0 until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the Port Enable bit to a 1). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a 0. The HCHalted bit (D29:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register should be a 0 before software attempts to use this bit. The host controller may hold Port Reset asserted to a 1 when the HCHalted bit is a 1. This bit is 0 if Port Power is 0 NOTE: System software should not attempt to reset a port if the HCHalted bit in the USB2.0_STS register is a 1. Doing so will result in undefined behavior. Suspend -- R/W. 0 = Port not in suspend state.(Default) 1 = Port in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows: Port Enabled 0 1 Suspend X 0 1 Port State Disabled Enabled Suspend 8 7 1 When in suspend state, downstream propagation of data is blocked on this port, except for port reset. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. The host controller will unconditionally set this bit to a 0 when software sets the Force Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller. If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the results are undefined. Intel (R) ICH7 Family Datasheet 575 EHCI Controller Registers (D29:F7) Bit Force Port Resume -- R/W. Description 0 = No resume (K-state) detected/driven on port. (Default) 1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a 1 because a Jto-K transition is detected, the Port Change Detect bit (D29:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If software sets this bit to a 1, the host controller must not set the Port Change Detect bit. NOTE: When the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification, Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. Software must appropriately time the Resume and set this bit to a 0 when the appropriate amount of time has elapsed. Writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a 1 until the port has switched to the high-speed idle. Overcurrent Change -- R/WC. The functionality of this bit is not dependent upon the port owner. Software clears this bit by writing a 1 to it. 0 = No change. (Default) 1 = There is a change to Overcurrent Active. Overcurrent Active -- RO. 0 = This port does not have an overcurrent condition. (Default) 1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0 when the over current condition is removed. The Intel(R) ICH7 automatically disables the port when the overcurrent active bit is 1. Port Enable/Disable Change -- R/WC. For the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a port error). This bit is not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software clears this bit by writing a 1 to it. 0 = No change in status. (Default). 1 = Port enabled/disabled status has changed. Port Enabled/Disabled -- R/W. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = Disable 1 = Enable (Default) Connect Status Change -- R/WC. This bit indicates a change has occurred in the port's Current Connect Status. Software sets this bit to 0 by writing a 1 to it. 6 5 4 3 2 1 0 = No change (Default). 1 = Change in Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set). Current Connect Status -- RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. (Default) 1 = Device is present on port. 0 576 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2.3 USB 2.0-Based Debug Port Register The Debug port's registers are located in the same memory area, defined by the Base Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah (D29:F7:offset 5Ah). The specific EHCI port that supports this debug capability (port 0) is indicated by a 4-bit field (bits 20-23) in the HCSPARAMS register of the EHCI controller. The address map of the Debug Port registers is shown in Table 13-4. Table 13-4. Debug Port Register Address Map MEM_BASE + Offset A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h Mnemonic CNTL_STS USBPID DATABUF[3:0] DATABUF[7:4] CONFIG Register Name Control/Status USB PIDs Data Buffer (Bytes 3:0) Data Buffer (Bytes 7:4) Configuration Default 00000000h 00000000h 00000000h 00000000h 00007F01h Type R/W, R/WC, RO, WO R/W, RO R/W R/W R/W NOTES: 1. All of these registers are implemented in the core well and reset by PLTRST#, EHC HCRESET, and a EHC D3-to-D0 transition. 2. The hardware associated with this register provides no checks to ensure that software programs the interface correctly. How the hardware behaves when programmed inappropriately is undefined. 13.2.3.1 CNTL_STS--Control/Status Register Offset: Default Value: Bit 31 Reserved OWNER_CNT -- R/W. 30 0 = Ownership of the debug port is NOT forced to the EHCI controller (Default) 1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately taken away from the companion Classic USB Host controller) If the port was already owned by the EHCI controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits in the standard EHCI registers. Reserved ENABLED_CNT -- R/W. 0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same conditions where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default) 1 = Debug port is enabled for operation. Software can directly set this bit if the port is already enabled in the associated PORTSC register (this is enforced by the hardware). Reserved MEM_BASE + A0h 0000h Attribute: Size: Description R/W, R/WC, RO, WO 32 bits 29 28 27:17 Intel (R) ICH7 Family Datasheet 577 EHCI Controller Registers (D29:F7) Bit Description DONE_STS -- R/WC. Software can clear this by writing a 1 to it. 16 0 = Request Not complete 1 = Set by hardware to indicate that the request is complete. LINK_ID_STS -- RO. This field identifies the link interface. 0h = Hardwired. Indicates that it is a USB Debug Port. Reserved. This bit returns 0 when read. Writes have no effect. IN_USE_CNT -- R/W. Set by software to indicate that the port is in use. Cleared by software to indicate that the port is free and may be used by other software. This bit is cleared after reset. (This bit has no effect on hardware.) EXCEPTION_STS -- RO. This field indicates the exception when the ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0. 000 = No Error. (Default) Note: this should not be seen, since this field should only be checked if there is an error. 001 =Transaction error: indicates the USB 2.0 transaction had an error (CRC, bad PID, timeout, etc.) 010 =Hardware error. Request was attempted (or in progress) when port was suspended or reset. All Other combinations are reserved ERROR_GOOD#_STS -- RO. 15:12 11 10 9:7 6 0 = Hardware clears this bit to 0 after the proper completion of a read or write. (Default) 1 = Error has occurred. Details on the nature of the error are provided in the Exception field. GO_CNT -- WO. 5 0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default) 1 = Causes hardware to perform a read or write request. NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior. WRITE_READ#_CNT -- R/W. Software clears this bit to indicate that the current request is a read. Software sets this bit to indicate that the current request is a write. 0 = Read (Default) 1 = Write 4 578 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) Bit Description DONE_STS -- R/WC. Software can clear this by writing a 1 to it. 16 0 = Request Not complete 1 = Set by hardware to indicate that the request is complete. LINK_ID_STS -- RO. This field identifies the link interface. 0h = Hardwired. Indicates that it is a USB Debug Port. Reserved. This bit returns 0 when read. Writes have no effect. IN_USE_CNT -- R/W. Set by software to indicate that the port is in use. Cleared by software to indicate that the port is free and may be used by other software. This bit is cleared after reset. (This bit has no effect on hardware.) EXCEPTION_STS -- RO. This field indicates the exception when the ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0. 000 = No Error. (Default) Note: this should not be seen, since this field should only be checked if there is an error. 001 =Transaction error: indicates the USB 2.0 transaction had an error (CRC, bad PID, timeout, etc.) 010 =Hardware error. Request was attempted (or in progress) when port was suspended or reset. All Other combinations are reserved ERROR_GOOD#_STS -- RO. 15:12 11 10 9:7 6 0 = Hardware clears this bit to 0 after the proper completion of a read or write. (Default) 1 = Error has occurred. Details on the nature of the error are provided in the Exception field. GO_CNT -- WO. 5 0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default) 1 = Causes hardware to perform a read or write request. NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior. WRITE_READ#_CNT -- R/W. Software clears this bit to indicate that the current request is a read. Software sets this bit to indicate that the current request is a write. 0 = Read (Default) 1 = Write 4 Intel (R) ICH7 Family Datasheet 579 EHCI Controller Registers (D29:F7) Bit Description DATA_LEN_CNT -- R/W. This field is used to indicate the size of the data to be transferred. default = 0h. For write operations, this field is set by software to indicate to the hardware how many bytes of data in Data Buffer are to be transferred to the console. A value of 0h indicates that a zero-length packet should be sent. A value of 1-8 indicates 1-8 bytes are to be transferred. Values 9-Fh are invalid and how hardware behaves if used is undefined. For read operations, this field is set by hardware to indicate to software how many bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates that a zero length packet was returned and the state of Data Buffer is not defined. A value of 1-8 indicates 1-8 bytes were received. Hardware is not allowed to return values 9-Fh. The transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. 3:0 NOTES: 1. Software should do Read-Modify-Write operations to this register to preserve the contents of bits not being modified. This include Reserved bits. 2. To preserve the usage of RESERVED bits in the future, software should always write the same value read from the bit until it is defined. Reserved bits will always return 0 when read. 13.2.3.2 USBPID--USB PIDs Register Offset: Default Value: MEM_BASE + A4h 0000h Attribute: Size: R/W, RO 32 bits This DWord register is used to communicate PID information between the USB debug driver and the USB debug port. The debug port uses some of these fields to generate USB packets, and uses other fields to return PID information to the USB debug driver. Bit 31:24 Description Reserved: These bits will return 0 when read. Writes will have no effect. RECEIVED_PID_STS[23:16] -- RO. Hardware updates this field with the received PID for transactions in either direction. When the controller is writing data, this field is updated with the handshake PID that is received from the device. When the host controller is reading data, this field is updated with the data packet PID (if the device sent data), or the handshake PID (if the device NAKs the request). This field is valid when the hardware clears the GO_DONE#_CNT bit. SEND_PID_CNT[15:8] -- R/W. Hardware sends this PID to begin the data packet when sending data to USB (i.e., WRITE_READ#_CNT is asserted). Software typically sets this field to either DATA0 or DATA1 PID values. TOKEN_PID_CNT[7:0] -- R/W. Hardware sends this PID as the Token PID for each USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID values. 23:16 15:8 7:0 580 Intel (R) ICH7 Family Datasheet EHCI Controller Registers (D29:F7) 13.2.3.3 DATABUF[7:0]--Data Buffer Bytes[7:0] Register Offset: Default Value: MEM_BASE + A8h-AFh 0000000000000000h Attribute: Size: R/W 64 bits This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. Bit Description DATABUFFER[63:0] -- R/W. This field is the 8 bytes of the data buffer. Bits 7:0 correspond to least significant byte (byte 0). Bits 63:56 correspond to the most significant byte (byte 7). 63:0 The bytes in the Data Buffer must be written with data before software initiates a write request. For a read request, the Data Buffer contains valid data when DONE_STS bit (offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6) is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0) indicates the number of bytes that are valid. 13.2.3.4 CONFIG--Configuration Register Offset: Default Value: MEM_BASE + B0-B3h 00007F01h Attribute: Size: R/W 32 bits Bit 31:15 14:8 7:4 3:0 Reserved Description USB_ADDRESS_CNF -- R/W. This 7-bit field identifies the USB device address used by the controller for all Token PID generation. (Default = 7Fh) Reserved USB_ENDPOINT_CNF -- R/W. This 4-bit field identifies the endpoint used by the controller for all Token PID generation. (Default = 01h) Intel (R) ICH7 Family Datasheet 581 EHCI Controller Registers (D29:F7) 582 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14 14.1 SMBus Controller Registers (D31:F3) PCI Configuration Registers (SMBUS--D31:F3) Table 14-1. SMBus Controller PCI Register Address Map (SMBUS--D31:F3) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 20h-23h 2Ch-2Dh 2Eh-2Fh 3Ch 3Dh 40h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC SMB_BASE SVID SID INT_LN INT_PN HOSTC Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code SMBus Base Address Subsystem Vendor Identification Subsystem Identification Interrupt Line Interrupt Pin Host Configuration Default 8086 See register description. 0000h 0280h See register description. 00h 05h 0Ch 00000001h 00h 00h 00h See description 00h Type RO RO R/W, RO RO, R/WC RO RO RO RO R/W, RO RO R/WO R/W RO R/W NOTE: Registers that are not shown should be treated as Reserved (See Section 6.2 for details). 14.1.1 VID--Vendor Identification Register (SMBUS--D31:F3) Address: Default Value: Bit 15:0 00h-01h 8086h Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel Intel (R) ICH7 Family Datasheet 583 SMBus Controller Registers (D31:F3) 14.1.2 DID--Device Identification Register (SMBUS--D31:F3) Address: Default Value: Bit 15:0 02h-03h See bit description Attribute: Size: Description RO 16 bits Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 SMBus controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 14.1.3 PCICMD--PCI Command Register (SMBUS--D31:F3) Address: Default Value: Bit 15:11 10 9 8 7 6 5 4 3 2 1 Reserved Interrupt Disable -- R/W. 0 = Enable 1 = Disables SMBus to assert its PIRQB# signal. Fast Back to Back Enable (FBE) -- RO. Hardwired to 0. SERR# Enable (SERR_EN) -- R/W. 0 = Enables SERR# generation. 1 = Disables SERR# generation. Wait Cycle Control (WCC) -- RO. Hardwired to 0. Parity Error Response (PER) -- R/W. 0 = Disable 1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected. VGA Palette Snoop (VPS) -- RO. Hardwired to 0. Postable Memory Write Enable (PMWE) -- RO. Hardwired to 0. Special Cycle Enable (SCE) -- RO. Hardwired to 0. Bus Master Enable (BME) -- RO. Hardwired to 0. Memory Space Enable (MSE) -- RO. Hardwired to 0. I/O Space Enable (IOSE) -- R/W. 0 0 = Disable 1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register. 04h-05h 0000h Attributes: Size: Description RO, R/W 16 bits 584 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.1.4 PCISTS--PCI Status Register (SMBUS--D31:F3) Address: Default Value: 06h-07h 0280h Attributes: Size: RO, R/WC 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 0 = No parity error detected. 1 = Parity error detected. Signaled System Error (SSE) -- R/WC. 14 13 12 0 = No system error detected. 1 = System error detected. Received Master Abort (RMA) -- RO. Hardwired to 0. Received Target Abort (RTA) -- RO. Hardwired to 0. Signaled Target Abort (STA) -- R/WC. 11 0 = Intel(R) ICH7 did Not terminate transaction for this function with a target abort. 1 = The function is targeted with a transaction that the ICH7 terminates with a target abort. DEVSEL# Timing Status (DEVT) -- RO. This 2-bit field defines the timing for DEVSEL# assertion for positive decode. 01 = Medium timing. 8 7 6 5 4 3 2:0 Data Parity Error Detected (DPED) -- RO. Hardwired to 0. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. User Definable Features (UDF) -- RO. Hardwired to 0. 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. Capabilities List (CAP_LIST) -- RO. Hardwired to 0 because there are no capability list structures in this function Interrupt Status (INTS) -- RO. This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the PCI Command register. Reserved Description Detected Parity Error (DPE) -- R/WC. 10:9 14.1.5 RID--Revision Identification Register (SMBUS--D31:F3) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the Intel I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. (R) Intel (R) ICH7 Family Datasheet 585 SMBus Controller Registers (D31:F3) 14.1.6 PI--Programming Interface Register (SMBUS--D31:F3) Offset Address: 09h Default Value: 00h Bit 7:0 Reserved Attribute: Size: Description RO 8 bits 14.1.7 SCC--Sub Class Code Register (SMBUS--D31:F3) Address Offset: 0Ah Default Value: 05h Bit 7:0 Sub Class Code (SCC) -- RO. 05h = SM Bus serial controller Attributes: Size: Description RO 8 bits 14.1.8 BCC--Base Class Code Register (SMBUS--D31:F3) Address Offset: 0Bh Default Value: 0Ch Bit 7:0 Base Class Code (BCC) -- RO. 0Ch = Serial controller. Attributes: Size: Description RO 8 bits 14.1.9 SMB_BASE--SMBUS Base Address Register (SMBUS--D31:F3) Address Offset: 20-23h Default Value: 00000001h Bit 31:16 15:5 4:1 0 Reserved -- RO Base Address -- R/W. This field provides the 32-byte system I/O base address for the Intel(R) ICH7 SMB logic. Reserved -- RO IO Space Indicator -- RO. Hardwired to 1 indicating that the SMB logic is I/O mapped. Attribute: Size: Description R/W, RO 32-bits 586 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.1.10 SVID -- Subsystem Vendor Identification Register (SMBUS--D31:F2/F4) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description RO 16 bits Core 15:0 Subsystem Vendor ID (SVID) -- RO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SVID register. NOTE: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. 14.1.11 SID -- Subsystem Identification Register (SMBUS--D31:F2/F4) Address Offset: 2Eh-2Fh Default Value: 00h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem ID (SID) -- RO. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. The value returned by reads to this register is the same as that which was written by BIOS into the IDE SID register. NOTE: Software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle. 14.1.12 INT_LN--Interrupt Line Register (SMBUS--D31:F3) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attributes: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- R/W. This data is not used by the Intel(R) ICH7. It is to communicate to software the interrupt line that the interrupt pin is connected to PIRQB#. 14.1.13 INT_PN--Interrupt Pin Register (SMBUS--D31:F3) Address Offset: 3Dh Default Value: See description Bit 7:0 Attributes: Size: Description RO 8 bits Interrupt PIN (INT_PN) -- RO. This reflects the value of D31IP.SMIP in chipset configuration space. Intel (R) ICH7 Family Datasheet 587 SMBus Controller Registers (D31:F3) 14.1.14 HOSTC--Host Configuration Register (SMBUS--D31:F3) Address Offset: 40h Default Value: 00h Bit 7:3 Reserved I2C_EN -- R/W. 2 0 = SMBus behavior. 1 = The Intel(R) ICH7 is enabled to communicate with I2C devices. This will change the formatting of some commands. SMB_SMI_EN -- R/W. 1 0 = SMBus interrupts will not generate an SMI#. 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to Section 5.21.4 (Interrupts / SMI#). This bit needs to be set for SMBALERT# to be enabled. SMBus Host Enable (HST_EN) -- R/W. 0 0 = Disable the SMBus Host controller. 1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or SMI#. Note that the SMB Host controller will not respond to any new requests until all interrupt requests have been cleared. Attribute: Size: Description R/W 8 bits 14.2 SMBus I/O Registers Table 14-2. SMBus I/O Register Address Map SMB_BASE + Offset 00h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah-0Bh 0Ch 0Dh 0Eh Mnemonic Register Name Default Type R/WC, RO, R/WC (special) R/W, WO R/W R/W R/W R/W R/W R/W R/W RO R/WC, RO R/W R/W, RO HST_STS HST_CNT HST_CMD XMIT_SLVA HST_D0 HST_D1 HOST_BLOCK_DB PEC RCV_SLVA SLV_DATA AUX_STS AUX_CTL SMLINK_PIN_CTL Host Status Host Control Host Command Transmit Slave Address Host Data 0 Host Data 1 Host Block Data Byte Packet Error Check Receive Slave Address Receive Slave Data Auxiliary Status Auxiliary Control SMLink Pin Control (TCO Compatible Mode) 00h 00h 00h 00h 00h 00h 00h 00h 44h 0000h 00h 00h See register description 588 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) Table 14-2. SMBus I/O Register Address Map SMB_BASE + Offset 0Fh 10h 11h 14h 16h 17h Mnemonic Register Name Default See register description 00h 00h 00h 00h 00h Type SMBUS_PIN_CTL SLV_STS SLV_CMD NOTIFY_DADDR NOTIFY_DLOW NOTIFY_DHIGH SMBus Pin Control Slave Status Slave Command Notify Device Address Notify Data Low Byte Notify Data High Byte R/W, RO R/WC R/W RO RO RO 14.2.1 HST_STS--Host Status Register (SMBUS--D31:F3) Register Offset: SMBASE + 00h RO Default Value: 00h Attribute: Size: R/WC, R/WC (special), 8-bits All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a 0 to any bit position has no effect. Bit Byte Done Status (DS) -- R/WC. 0 = Software can clear this by writing a 1 to it. 1 = Host controller received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last byte of the transfer. This bit is not set when transmission is due to the LAN interface heartbeat. 7 This bit has no meaning for block transfers when the 32-byte buffer is enabled. NOTE: When the last byte of a block message is received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt handler clears the DS bit, the message is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the Intel(R) ICH7 will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases. INUSE_STS -- R/WC (special). This bit is used as semaphore among various independent software threads that may need to use the ICH7's SMBus logic, and has no other effect on hardware. 6 0 = After a full PCI reset, a read to this bit returns a 0. 1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0, and will then own the usage of the host controller. SMBALERT_STS -- R/WC. 5 0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by software writing a 1 to the bit position or by RSMRST# going low. If the signal is programmed as a GPIO, then this bit will not be set. Description Intel (R) ICH7 Family Datasheet 589 SMBus Controller Registers (D31:F3) Bit FAILED -- R/WC. 4 Description 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to the KILL bit being set to terminate the host transaction. BUS_ERR -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = The source of the interrupt of SMI# was a transaction collision. DEV_ERR -- R/WC. 0 = Software clears this bit by writing a 1 to it. The ICH7 will then deassert the interrupt or SMI#. 1 = The source of the interrupt or SMI# was due to one of the following: * * * Invalid Command Field, Unclaimed Cycle (host initiated), Host Device Time-out Error. 3 2 1 INTR -- R/WC (special). This bit can only be set by termination of a command. INTR is not dependent on the INTREN bit (offset SMBASE + 02h, bit 0) of the Host controller register (offset 02h). It is only dependent on the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case. 0 = Software clears this bit by writing a 1 to it. The ICH7 then deasserts the interrupt or SMI#. 1 = The source of the interrupt or SMI# was the successful completion of its last command. HOST_BUSY -- RO. 0 = Cleared by the ICH7 when the current transaction is completed. 1 = Indicates that the ICH7 is running a command from the host interface. No SMB registers should be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host Control Register are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_STS bit. 0 590 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.2.2 HST_CNT--Host Control Register (SMBUS--D31:F3) Register Offset: SMBASE + 02h Default Value: 00h Attribute: Size: R/W, WO 8-bits Note: A read to this register will clear the byte pointer of the 32-byte buffer. Bit PEC_EN -- R/W. 0 = SMBus host controller does not perform the transaction with the PEC phase appended. 1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking phase appended. For writes, the value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the write in which the START bit is set. START -- WO. 6 0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when the Intel(R) ICH7 has finished the command. 1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. LAST_BYTE -- WO. This bit is used for Block Read commands. 1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the block. This causes the ICH7 to send a NACK (instead of an ACK) after receiving the last byte. NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the LAST_BYTE bit cannot be cleared. This prevents the ICH7 from running some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write). Description 7 5 Intel (R) ICH7 Family Datasheet 591 SMBus Controller Registers (D31:F3) Bit Description SMB_CMD -- R/W. The bit encoding below indicates which command the ICH7 is to perform. If enabled, the ICH7 will generate an interrupt or SMI# when the command has completed If the value is for a non-supported or reserved command, the ICH7 will set the device error (DEV_ERR) status bit (offset SMBASE + 00h, bit 2) and generate an interrupt when the START bit is set. The ICH7 will perform no command, and will not operate until DEV_ERR is cleared. 000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the slave address register determines if this is a read or write command. 010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data. 011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, after the command completes, the DATA0 and DATA1 registers will contain the read data. 100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. After the command completes, the DATA0 and DATA1 registers will contain the read data. 101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. 110 = I2C Read: This command uses the transmit slave address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The ICH7 continues reading data until the NAK is received. 111 = Block Process: This command uses the transmit slave address, command, DATA0 and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block read, the count is received and stored in the DATA0 register. Bit 0 of the slave address register always indicate a write command. For writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. NOTE: E32B bit in the Auxiliary Control register must be set for this command to work. KILL -- R/W. 0 = Normal SMBus host controller functionality. 1 = Kills the current host transaction taking place, sets the FAILED status bit, and asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the SMBus host controller to function normally. INTREN -- R/W. 0 = Disable. 1 = Enable the generation of an interrupt or SMI# upon the completion of the command. 4:2 1 0 592 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.2.3 HST_CMD--Host Command Register (SMBUS--D31:F3) Register Offset: SMBASE + 03h Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command. 14.2.4 XMIT_SLVA--Transmit Slave Address Register (SMBUS--D31:F3) Register Offset: SMBASE + 04h Default Value: 00h Attribute: Size: R/W 8 bits This register is transmitted by the host controller in the slave address field of the SMBus protocol. Bit 7:1 0 Description Address -- R/W. This field provides a 7-bit address of the targeted slave. RW -- R/W. Direction of the host transfer. 0 = Write 1 = Read 14.2.5 HST_D0--Host Data 0 Register (SMBUS--D31:F3) Register Offset: SMBASE + 05h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits 7:0 Data0/Count -- R/W. This field contains the 8-bit data sent in the DATA0 field of the SMBus protocol. For block write commands, this register reflects the number of bytes to transfer. This register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host controller does not check or log invalid block counts. 14.2.6 HST_D1--Host Data 1 Register (SMBUS--D31:F3) Register Offset: SMBASE + 06h Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Data1 -- R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the execution of any command. Intel (R) ICH7 Family Datasheet 593 SMBus Controller Registers (D31:F3) 14.2.7 Host_BLOCK_DB--Host Block Data Byte Register (SMBUS--D31:F3) Register Offset: SMBASE + 07h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits Block Data (BDTA) -- R/W. This is either a register, or a pointer into a 32-byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit (offset SMBASE + 0Dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read, just as it behaved on the ICH3. When the E32B bit is set, reads and writes to this register are used to access the 32byte block data storage array. An internal index pointer is used to address the array, which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then increments automatically upon each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. When the E2B bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. After the Host controller has sent the Address, Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this register. When the E2B bit is cleared for writes, software will place a single byte in this register. After the host controller has sent the address, command, and byte count fields, it will send the byte in this register. If there is more data to send, software will write the next series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The controller will then send the next byte. During the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. When the E2B bit is set for reads, after receiving the byte count into the Data0 register, the first series of data bytes go into the SRAM pointed to by this register. If the byte count has been exhausted or the 32-byte SRAM has been filled, the controller will generate an SMI# or interrupt (depending on configuration) and set the DONE_STS bit. Software will then read the data. During the time between when the last byte is read from the SRAM to when the DONE_STS bit is cleared, the controller will insert waitstates on the interface. 7:0 14.2.8 PEC--Packet Error Check (PEC) Register (SMBUS--D31:F3) Register Offset: SMBASE + 08h Default Value: 00h Bit Attribute: Size: Description R/W 8 bits 7:0 PEC_DATA -- R/W. This 8-bit register is written with the 8-bit CRC value that is used as the SMBus PEC data prior to a write transaction. For read transactions, the PEC data is loaded from the SMBus into this register and is then read by software. Software must ensure that the INUSE_STS bit is properly maintained to avoid having this field overwritten by a write transaction following a read transaction. 594 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.2.9 RCV_SLVA--Receive Slave Address Register (SMBUS--D31:F3) Register Offset: SMBASE + 09h Default Value: 44h Lockable: No Bit 7 Reserved SLAVE_ADDR -- R/W. This field is the slave address that the Intel(R) ICH7 decodes for read and write cycles. the default is not 0, so the SMBus Slave Interface can respond even before the processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by PLTRST#. Attribute: Size: Power Well: Description R/W 8 bits Resume 6:0 14.2.10 SLV_DATA--Receive Slave Data Register (SMBUS--D31:F3) Register Offset: SMBASE + 0Ah-0Bh Default Value: 0000h Lockable: No Attribute: Size: Power Well: RO 16 bits Resume This register contains the 16-bit data value written by the external SMBus master. The processor can then read the value from this register. This register is reset by RSMRST#, but not PLTRST# . Bit 15:8 7:0 Description Data Message Byte 1 (DATA_MSG1) -- RO. See Section 5.21.7 for a discussion of this field. Data Message Byte 0 (DATA_MSG0) -- RO. See Section 5.21.7 for a discussion of this field. 14.2.11 AUX_STS--Auxiliary Status Register (SMBUS--D31:F3) Register Offset: SMBASE + 0Ch Default Value: 00h Lockable: No Attribute: Size: Power Well: Description Reserved SMBus TCO Mode (STCO) -- RO. This bit reflects the strap setting of TCO compatible mode vs. Advanced TCO mode. 0 = Intel(R) ICH7 is in the compatible TCO mode. 1 = ICH7 is in the advanced TCO mode. CRC Error (CRCE) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of the host status register will also be set. This bit will be set by the controller if a software abort occurs in the middle of the CRC portion of the cycle or an abort happens after the ICH7 has received the final data bit transmitted by an external slave. R/WC, RO 8 bits Resume . Bit 7:2 1 0 Intel (R) ICH7 Family Datasheet 595 SMBus Controller Registers (D31:F3) 14.2.12 AUX_CTL--Auxiliary Control Register (SMBUS--D31:F3) Register Offset: SMBASE + 0Dh Default Value: 00h Lockable: No Attribute: Size: Power Well: Description Reserved Enable 32-Byte Buffer (E32B) -- R/W. 1 0 = Disable. 1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to a single register. This enables the block commands to transfer or receive up to 32-bytes before the Intel(R) ICH7 generates an interrupt. Automatically Append CRC (AAC) -- R/W. 0 0 = ICH7 will Not automatically append the CRC. 1 = The ICH7 will automatically append the CRC. This bit must not be changed during SMBus transactions or undetermined behavior will result. It should be programmed only once during the lifetime of the function. R/W 8 bits Resume . Bit 7:2 14.2.13 SMLINK_PIN_CTL--SMLink Pin Control Register (SMBUS--D31:F3) Register Offset: SMBASE + 0Eh Default Value: See below Attribute: Size: R/W, RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. This register is only applicable in the TCO compatible mode. Bit 7:3 Reserved SMLINK_CLK_CTL -- R/W. 2 0 = Intel(R) ICH7 will drive the SMLINK0 pin low, independent of what the other SMLINK logic would otherwise indicate for the SMLINK0 pin. 1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state of the pin. (Default) SMLINK1_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK1 pin. This allows software to read the current state of the pin. 0 = Low 1 = High SMLINK0_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMLINK0 pin. This allows software to read the current state of the pin. 0 = Low 1 = High Description 1 0 596 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.2.14 SMBUS_PIN_CTL--SMBUS Pin Control Register (SMBUS--D31:F3) Register Offset: SMBASE + 0Fh Default Value: See below Attribute: Size: R/W, RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit 7:3 Reserved SMBCLK_CTL -- R/W. 1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin. 0 = Intel(R) ICH7 drives the SMBCLK pin low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. (Default) SMBDATA_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBDATA pin. This allows software to read the current state of the pin. 0 = Low 1 = High SMBCLK_CUR_STS -- RO. This read-only bit has a default value that is dependent on an external signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current state of the pin. 0 = Low 1 = High Description 2 1 0 14.2.15 SLV_STS--Slave Status Register (SMBUS--D31:F3) Register Offset: SMBASE + 10h Default Value: 00h Attribute: Size: R/WC 8 bits Note: This register is in the resume well and is reset by RSMRST#. All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. Bit 7:1 Reserved HOST_NOTIFY_STS -- R/WC. The Intel(R) ICH7 sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit after reading any information needed from the Notify address and data registers by writing a 1 to this bit. Note that the ICH7 will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the ICH7 will NACK the first byte (host address) of any new "Host Notify" commands on the SMLink. Writing a 0 to this bit has no effect. Description 0 Intel (R) ICH7 Family Datasheet 597 SMBus Controller Registers (D31:F3) 14.2.16 SLV_CMD--Slave Command Register (SMBUS--D31:F3) Register Offset: SMBASE + 11h Default Value: 00h Attribute: Size: R/W 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit 7:2 Reserved SMBALERT_DIS -- R/W. 0 = Allows the generation of the interrupt or SMI#. 1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT# source. This bit is logically inverted and ANDed with the SMBALERT_STS bit (offset SMBASE + 00h, bit 5). The resulting signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the wake logic. HOST_NOTIFY_WKEN -- R/W. Software sets this bit to 1 to enable the reception of a Host Notify command as a wake event. When enabled this event is "OR"ed in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register. 0 = Disable 1 = Enable HOST_NOTIFY_INTREN -- R/W. Software sets this bit to 1 to enable the generation of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or SMI#) is logically generated by AND'ing the STS and INTREN bits. 0 = Disable 1 = Enable Description 2 1 0 14.2.17 NOTIFY_DADDR--Notify Device Address Register (SMBUS--D31:F3) Register Offset: SMBASE + 14h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DEVICE_ADDRESS -- RO. This field contains the 7-bit device address received during the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. Reserved 7:1 0 598 Intel (R) ICH7 Family Datasheet SMBus Controller Registers (D31:F3) 14.2.18 NOTIFY_DLOW--Notify Data Low Byte Register (SMBUS--D31:F3) Register Offset: SMBASE + 16h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DATA_LOW_BYTE -- RO. This field contains the first (low) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. 7:0 14.2.19 NOTIFY_DHIGH--Notify Data High Byte Register (SMBUS--D31:F3) Register Offset: SMBASE + 17h Default Value: 00h Attribute: Size: RO 8 bits Note: This register is in the resume well and is reset by RSMRST#. Bit Description DATA_HIGH_BYTE -- RO. This field contains the second (high) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1. 7:0 Intel (R) ICH7 Family Datasheet 599 SMBus Controller Registers (D31:F3) 600 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15 15.1 Note: IDE Controller Registers (D31:F1) PCI Configuration Registers (IDE--D31:F1) Address locations that are not shown should be treated as Reserved (See Section 6.2 for details). All of the IDE registers are in the core well. None of the registers can be locked. Table 15-1. IDE Controller PCI Register Address Map (IDE-D31:F1) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 2Ch-2Dh 2Eh-2Fh 3C 3D 40h-41h 42h-43h 44h 48h 4Ah-4Bh 54h C0h C4h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC CLS PMLT PCMD_BAR PCNL_BAR SCMD_BAR SCNL_BAR BM_BASE IDE_SVID IDE_SID INTR_LN INTR_PN IDE_TIMP IDE_TIMS SLV_IDETIM SDMA_CNT SDMA_TIM IDE_CONFIG ATC ATS Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Cache Line Size Primary Master Latency Timer Primary Command Block Base Address Primary Control Block Base Address Secondary Command Block Base Address Secondary Control Block Base Address Bus Master Base Address Subsystem Vendor ID Subsystem ID Interrupt Line Interrupt Pin Primary IDE Timing Secondary IDE Timing Slave IDE Timing Synchronous DMA Control Synchronous DMA Timing IDE I/O Configuration APM Trapping Control APM Trapping Status Default 8086h See register description. 00h 0280h See register description. 8Ah 01h 01h 00h 00h 00000001h 00000001h 00000001h 00000001h 00000001h 00h 0000h 00h See register description. 0000h 0000h 00h 00h 0000h 00000000h 00h 00h Type RO RO R/W, RO R/W, RO RO R/W, RO RO RO RO RO R/W, RO R/W, RO R/W, RO R/W, RO R/W, RO R/WO R/WO R/W RO R/W R/W R/W R/W R/W R/W R/W R/WC NOTE: The ICH7 IDE controller is not arbitrated as a PCI device; therefore, it does not need a master latency timer. Intel (R) ICH7 Family Datasheet 601 IDE Controller Registers (D31:F1) 15.1.1 VID--Vendor Identification Register (IDE--D31:F1) Offset Address: 00h-01h Default Value: 8086h Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16-bit Core Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 15.1.2 DID--Device Identification Register (IDE--D31:F1) Offset Address: 02h-03h Default Value: See bit description Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16-bit Core Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 IDE controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 15.1.3 PCICMD--PCI Command Register (IDE--D31:F1) Address Offset: 04h-05h Default Value: 00h Bit 15:11 Reserved Interrupt Disable (ID) -- R/W. 10 0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy mode). 1 = Disable. The interrupt will be deasserted. Fast Back to Back Enable (FBE) -- RO. Reserved as 0. SERR# Enable (SERR_EN) -- RO. Reserved as 0. Wait Cycle Control (WCC) -- RO. Reserved as 0. Parity Error Response (PER) -- RO. Reserved as 0. VGA Palette Snoop (VPS) -- RO. Reserved as 0. Postable Memory Write Enable (PMWE) -- RO. Reserved as 0. Special Cycle Enable (SCE) -- RO. Reserved as 0. Bus Master Enable (BME) -- R/W. Controls the ICH7's ability to act as a PCI master for IDE Bus Master transfers. Memory Space Enable (MSE) -- R/O. This controller does not contain a memory space. I/O Space Enable (IOSE) -- RO. Attribute: Size: Description RO, R/W 16 bits 9 8 7 6 5 4 3 2 1 0 602 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15.1.4 PCISTS -- PCI Status Register (IDE--D31:F1) Address Offset: 06h-07h Default Value: 0280h Attribute: Size: R/WC, RO 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 14 13 12 11 10:9 8 7 6 5 4 Description Detected Parity Error (DPE) -- RO. Reserved as 0. Signaled System Error (SSE) -- RO. Reserved as 0. Received Master Abort (RMA) -- R/WC. 0 = Master abort Not generated by Bus Master IDE interface function. 1 = Bus Master IDE interface function, as a master, generated a master abort. Reserved as 0 -- RO. Reserved as 0 -- RO. DEVSEL# Timing Status (DEV_STS) -- RO. 01 = Hardwired; however, the Intel(R) ICH7 does not have a real DEVSEL# signal associated with the IDE unit, so these bits have no effect. Data Parity Error Detected (DPED) -- RO. Reserved as 0. Fast Back to Back Capable (FB2BC) -- RO. Reserved as 1. User Definable Features (UDF) -- RO. Reserved as 0. 66MHz Capable (66MHZ_CAP) -- RO. Reserved as 0. Reserved Interrupt Status (INTS) -- RO. This bit is independent of the state of the Interrupt Disable bit in the command register. 0 = Interrupt is cleared. 1 = Interrupt/MSI is asserted. Reserved 3 2:0 15.1.5 RID--Revision Identification Register (IDE--D31:F1) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. Intel (R) ICH7 Family Datasheet 603 IDE Controller Registers (D31:F1) 15.1.6 PI--Programming Interface Register (IDE--D31:F1) Address Offset: 09h Default Value: 8Ah Bit 7 6:4 3 Attribute: Size: Description RO, R/W 8 bits This read-only bit is a 1 to indicate that the Intel(R) ICH7 supports bus master operation Reserved. Hardwired to 000b. SOP_MODE_CAP -- RO. This read-only bit is a 1 to indicate that the secondary controller supports both legacy and native modes. SOP_MODE_SEL -- R/W. This read/write bit determines the mode that the secondary IDE channel is operating in. 0 = Legacy-PCI mode (default) 1 = Native-PCI mode POP_MODE_CAP -- RO. This read-only bit is a 1 to indicate that the primary controller supports both legacy and native modes. POP_MODE_SEL -- R/W. This read/write bits determines the mode that the primary IDE channel is operating in. 0 = Legacy-PCI mode (default) 1 = Native-PCI mode 2 1 0 15.1.7 SCC--Sub Class Code Register (IDE--D31:F1) Address Offset: 0Ah Default Value: 01h Bit 7:0 Sub Class Code (SCC) -- RO. 01h = IDE device, in the context of a mass storage device. Attribute: Size: Description RO 8 bits 15.1.8 BCC--Base Class Code Register (IDE--D31:F1) Address Offset: 0Bh Default Value: 01h Bit 7:0 Base Class Code (BCC) -- RO. 01 = Mass storage device Attribute: Size: Description RO 8 bits 15.1.9 CLS--Cache Line Size Register (IDE--D31:F1) Address Offset: 0Ch Default Value: 00h Bit Cache Line Size (CLS) -- RO. 7:0 00h = Hardwired. The IDE controller is implemented internally so this register has no meaning. Attribute: Size: Description RO 8 bits 604 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15.1.10 PMLT--Primary Master Latency Timer Register (IDE--D31:F1) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Master Latency Timer Count (MLTC) -- RO. 00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. 15.1.11 PCMD_BAR--Primary Command Block Base Address Register (IDE--D31:F1) Address Offset: 10h-13h Default Value: 00000001h Attribute: Size: Description Reserved Base Address -- R/W. Base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:3 2:1 0 NOTE: This 8-byte I/O space is used in native mode for the Primary Controller's Command Block. 15.1.12 PCNL_BAR--Primary Control Block Base Address Register (IDE--D31:F1) Address Offset: 14h-17h Default Value: 00000001h Attribute: Size: Description Reserved Base Address -- R/W. Base address of the I/O space (4 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. R/W, RO 32 bits . Bit 31:16 15:2 1 0 NOTE: This 4-byte I/O space is used in native mode for the Primary Controller's Command Block. Intel (R) ICH7 Family Datasheet 605 IDE Controller Registers (D31:F1) 15.1.13 SCMD_BAR--Secondary Command Block Base Address Register (IDE D31:F1) Address Offset: 18h-1Bh Default Value: 00000001h Bit 31:16 15:3 2:1 0 Reserved Base Address -- R/W. Base address of the I/O space (8 consecutive I/O locations). If this register is programmed, the programmed value must not be less than 100h. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller's Command Block. 15.1.14 SCNL_BAR--Secondary Control Block Base Address Register (IDE D31:F1) Address Offset: 1Ch-1Fh Default Value: 00000001h Bit 31:16 15:2 1 0 Reserved Base Address -- R/W. Base address of the I/O space (4 consecutive I/O locations). If this register is programmed, the programmed value must not be less than 100h. Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. Attribute: Size: Description R/W, RO 32 bits NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller's Command Block. 606 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15.1.15 BM_BASE -- Bus Master Base Address Register (IDE--D31:F1) Address Offset: 20h-23h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Bus Master IDE interface function uses Base Address register 5 to request a 16byte I/O space to provide a software interface to the Bus Master functions. Only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address. Bit 31:16 15:4 3:1 0 Reserved Base Address -- R/W. This field provides the base address of the I/O space (16 consecutive I/O locations). Reserved Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. Description 15.1.16 IDE_SVID -- Subsystem Vendor Identification (IDE--D31:F1) Address Offset: 2Ch-2Dh Default Value: 00h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem Vendor ID (SVID) -- R/WO. The SVID register, in combination with the Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SVID registers for the USB#1, USB#2, and SMBus functions. 15.1.17 IDE_SID -- Subsystem Identification Register (IDE--D31:F1) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description R/WO 16 bits Core 15:0 Subsystem ID (SID) -- R/WO. The SID register, in combination with the SVID register, enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this register have no effect. The value written to this register will also be readable via the corresponding SID registers for the USB#1, USB#2, and SMBus functions. Intel (R) ICH7 Family Datasheet 607 IDE Controller Registers (D31:F1) 15.1.18 INTR_LN--Interrupt Line Register (IDE--D31:F1) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. 15.1.19 INTR_PN--Interrupt Pin Register (IDE--D31:F1) Address Offset: 3Dh Default Value: See Register Description Bit 7:0 Attribute: Size: RO 8 bits Description Interrupt Pin -- RO. This reflects the value of D31IP.PIP (Chipset Config Registers:Offset 3100h:bits 7:4). 15.1.20 IDE_TIMP -- IDE Primary Timing Register (IDE--D31:F1) Address Offset: 40-41h Default Value: 0000h Attribute: Size: R/W 16 bits This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It also controls operation of the buffer for PIO transfers. Bit Description IDE Decode Enable (IDE) -- R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be set in order for this bit to have any effect. 15 0 = Disable. 1 = Enables the Intel(R) ICH7 to decode the Command (1F0-1F7h) and Control (3F6h) Blocks. This bit also effects the memory decode range for IDE Expansion. Drive 1 Timing Register Enable (SITRE) -- R/W. 14 0 = Use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1 IORDY Sample Point (ISP) -- R/W. The setting of these bits determine the number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point. 13:12 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = Reserved 11:10 Reserved Recovery Time (RCT) -- R/W. The setting of these bits determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle. 9:8 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 608 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) Bit 7 (Desktop and Mobile Only) 6 (Desktop and Mobile Only) 5 (Desktop and Mobile Only) 4 (Desktop and Mobile Only) 7:4 (Ultra Mobile Only) Description Drive 1 DMA Timing Enable (DTE1) -- R/W. 0 = Disable. 1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 1 Prefetch/Posting Enable (PPE1) -- R/W. 0 = Disable. 1 = Enable Prefetch and posting to the IDE data port for this drive. Drive 1 IORDY Sample Point Enable (IE1) -- R/W. 0 = Disable IORDY sampling for this drive. 1 = Enable IORDY sampling for this drive. Drive 1 Fast Timing Bank (TIME1) -- R/W. 0 = Accesses to the data port will use compatible timings for this drive. 1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register. Reserved Drive 0 DMA Timing Enable (DTE0) -- R/W. 3 0 = Disable 1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing. Drive 0 Prefetch/Posting Enable (PPE0) -- R/W. 0 = Disable prefetch and posting to the IDE data port for this drive. 1 = Enable prefetch and posting to the IDE data port for this drive. Drive 0 IORDY Sample Point Enable (IE0) -- R/W. 0 = Disable IORDY sampling is disabled for this drive. 1 = Enable IORDY sampling for this drive. Drive 0 Fast Timing Bank (TIME0) -- R/W. 0 = Accesses to the data port will use compatible timings for this drive. 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time 2 1 0 Intel (R) ICH7 Family Datasheet 609 IDE Controller Registers (D31:F1) 15.1.21 IDE_TIMS -- IDE Secondary Timing Register (IDE--D31:F1) Address Offset: 42h-43h Default Value: 0000h Bit Attribute: Size: Description R/W 16 bits 15 IDE Decode Enable (IDE) -- R/W. This bit enables/disables the Secondary decode. The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be set in order for this bit to have any effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to individually disable the secondary IDE interface signals, even if the IDE Decode Enable bit is set. 0 = Disable. 1 = Enables the Intel(R) ICH7 to decode the associated Command Blocks (170-177h) and Control Block (376h). Accesses to these ranges return 00h, as the secondary channel is not implemented. 14:12 11 10:0 No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7 since a secondary channel does not exist. Reserved No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7 since a secondary channel does not exist. 15.1.22 SLV_IDETIM--Slave (Drive 1) IDE Timing Register (IDE--D31:F1) (Desktop and Mobile Only) Address Offset: 44h Default Value: 00h Bit 7:4 Attribute: Size: Description R/W 8 bits No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the Intel(R) ICH7. Primary Drive 1 IORDY Sample Point (PISP1) -- R/W. This field determines the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 01 10 11 = = = = 5 clocks 4 clocks 3 clocks Reserved 3:2 1:0 Primary Drive 1 Recovery Time (PRCT1) -- R/W. This field determines the minimum number of PCI clocks between the last IORDY sample point and the IOR#/ IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is set. 00 01 10 11 = = = = 4 3 2 1 clocks clocks clocks clocks 610 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15.1.23 SDMA_CNT--Synchronous DMA Control Register (IDE--D31:F1) Address Offset: 48h Default Value: 00h Bit 7:4 3:2 1 (Desktop and Mobile Only) 1 (Ultra Mobile Only) 0 Reserved No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the Intel(R) ICH7. Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) -- R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 1. Attribute: Size: Description R/W 8 bits Reserved Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) -- R/W. 0 = Disable (default) 1 = Enable Synchronous DMA mode for primary channel drive 0. 15.1.24 SDMA_TIM--Synchronous DMA Timing Register (IDE--D31:F1) Address Offset: 4Ah-4Bh Default Value: 0000h Attribute: Size: R/W 16 bits Note: For FAST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.16.4 for details. Bit 15:14 13:12 11:10 9:8 7:6 Reserved No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the Intel(R) ICH7. Reserved No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7. Reserved Description Intel (R) ICH7 Family Datasheet 611 IDE Controller Registers (D31:F1) Bit Description Primary Drive 1 Cycle Time (PCT1) -- R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved PCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved 5:4 (Desktop and Mobile Only) 5:4 (Ultra and Mobile Only) 3:2 Reserved Reserved Primary Drive 0 Cycle Time (PCT0) -- R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 8 clocks 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clocks, RP 16 clocks 10 = Reserved 11 = Reserved 1:0 00 = CT 4 clocks, RP 6 clocks 01 = CT 3 clocks, RP 5 clocks 10 = CT 2 clocks, RP 4 clocks 11 = Reserved 15.1.25 IDE_CONFIG--IDE I/O Configuration Register (IDE--D31:F1) Address Offset: 54h Default Value: 00000000h Bit 31:24 23:20 Reserved Miscellaneous Scratchpad (MS) -- R/W. Previously defined as a scratchpad bit to indicate to a driver that ATA-100 is supported. This is not used by software as all they needed to know was located in bits 7:4. See the definition of those bits. No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the Intel(R) ICH7. Attribute: Size: Description R/W 32 bits 19:18 612 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) Bit Description SIG_MODE -- R/W. These bits are used to control mode of the IDE signal pins for mobile/Ultra Mobile swap bay support. 17:16 If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 01 10 11 = = = = Normal (Enabled) Tri-state (Disabled) Drive low (Disabled) Reserved 15:14 13 (Desktop and Mobile Only) 13 (Ultra Mobile Only) No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7. Fast Primary Drive 1 Base Clock (FAST_PCB1) -- R/W. This bit is used in conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive. 0 = Disable Ultra ATA/100 timing for the Primary Slave drive. 1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register). Reserved 12 Fast Primary Drive 0 Base Clock (FAST_PCB0) -- R/W. This bit is used in conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive. 0 = Disable Ultra ATA/100 timing for the Primary Master drive. 1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register). Reserved No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7. No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7. Primary Slave Channel Cable Reporting -- R/W. BIOS should program this bit to tell the IDE driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. Primary Master Channel Cable Reporting -- R/W. Same description as bit 5 No Operation (NOP) -- R/W. These bits are read/write for legacy software compatibility, but have no functionality in the ICH7. Primary Drive 1 Base Clock (PCB1) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings 11:8 7 6 5 4 3:2 1 (Desktop and Mobile Only) 1 (Ultra Mobile Only) 0 Reserved Primary Drive 0 Base Clock (PCB0) -- R/W. 0 = 33 MHz base clock for Ultra ATA timings. 1 = 66 MHz base clock for Ultra ATA timings Intel (R) ICH7 Family Datasheet 613 IDE Controller Registers (D31:F1) 15.1.26 ATC--APM Trapping Control Register (IDE--D31:F1) Address Offset: C0h Default Value: 00h Bit 7:2 Reserved Slave Trap (PST) -- R/W. 1 0 = Disable. 1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h. The active device must be the slave device for the trap and/or SMI# to occur. Master Trap (PMT) -- R/W. 0 0 = Disable. 1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h-1F7h and 3F6h. The active device must be master device for the trap and/or SMI# to occur. Attribute: Size: Description R/W 8 bits 15.1.27 ATS--APM Trapping Status Register (IDE--D31:F1) Address Offset: C4h Default Value: 00h Bit 7:2 1 1 = Trap occurred to the slave device Master Trap Status (PMTS) -- R/WC. 0 0 = Trap occurred to the master device Reserved Slave Trap Status (PSTS) -- R/WC. Attribute: Size: Description R/WC 8 bits 614 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) 15.2 Bus Master IDE I/O Registers (IDE--D31:F1) The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no effect (but should not be attempted). The description of the I/O registers is shown in Table 15-2. Table 15-2. Bus Master IDE I/O Registers BMIBASE + Offset 00 01 02 03 04-07 Mnemonic BMICP -- BMISP -- BMIDP Register Name Bus Master IDE Command Primary Reserved Bus Master IDE Status Primary Reserved Bus Master IDE Descriptor Table Pointer Primary Default 00h 00h 00h 00h xxxxxxxxh Type R/W RO R/W, R/WC RO R/W 15.2.1 BMICP--Bus Master IDE Command Register (IDE--D31:F1) Address Offset: BMIBASE + 00h Default Value: 00h Bit 7:4 Reserved. Returns 0. Read / Write Control (RWC) -- R/W. This bit sets the direction of the bus master transfer: This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Returns 0. Attribute: Size: Description R/W 8 bits 3 2:1 Intel (R) ICH7 Family Datasheet 615 IDE Controller Registers (D31:F1) Bit Description Start/Stop Bus Master (START) -- R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master IDE Active bit (BMIBASE + 02h, bit 0) of the Bus Master IDE Status register for that IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit (BMIBASE + 02h, bit 2) in the Bus Master IDE Status register for that IDE channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = Enables bus master operation of the controller. Bus master operation does not actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI configuration space is also set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller will transfer data between the IDE device and memory only when this bit is set. Master operation can be halted by writing a 0 to this bit. NOTE: This bit is intended to be cleared by software after the data transfer is completed, as indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. 0 15.2.2 BMISP--Bus Master IDE Status Register (IDE--D31:F1) Address Offset: BMIBASE + 02h Default Value: 00h Bit Attribute: Size: Description R/W, R/WC 8 bits PRD Interrupt Status (PRDIS) -- R/WC. 7 0 = When this bit is cleared by software, the interrupt is cleared. 1 = Set when the host controller completes execution of a PRD that has its Interrupt bit (bit 2 of this register) set. Drive 1 DMA Capable -- R/W. 0 = Not Capable. 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The Intel(R) ICH7 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Reserved Drive 0 DMA Capable -- R/W. 5 0 = Not Capable 1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this channel is capable of DMA transfers, and that the controller has been initialized for optimum performance. The ICH7 does not use this bit. It is intended for systems that do not attach BMIDE to the PCI bus. Reserved. Returns 0. 6 (Desktop and Mobile Only) 6 (Ultra Mobile Only) 4:3 616 Intel (R) ICH7 Family Datasheet IDE Controller Registers (D31:F1) Bit Description Interrupt -- R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt line (IDEIRQ). 2 0 = Software clears this bit by writing a 1 to it. If this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal I/O APIC. When this bit is read as 1, all data transferred from the drive is visible in system memory. Error -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. Bus Master IDE Active (ACT) -- RO. 0 = This bit is cleared by the ICH7 when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared by the ICH7 when the Start bit is cleared in the Command register. When this bit is read as 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = Set by the ICH7 when the Start bit is written to the Command register. 1 0 15.2.3 BMIDP--Bus Master IDE Descriptor Table Pointer Register (IDE--D31:F1) Address Offset: BMIBASE + 04h Default Value: All bits undefined Bit 31:2 1:0 Attribute: Size: Description R/W 32 bits Address of Descriptor Table (ADDR) -- R/W. Corresponds to A[31:2]. The Descriptor Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in memory. Reserved Intel (R) ICH7 Family Datasheet 617 IDE Controller Registers (D31:F1) 618 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) AC `97 is not supported on ICH7-U Ultra Mobile. Note: 16.1 Note: AC '97 Audio PCI Configuration Space (Audio--D30:F2) Registers that are not shown should be treated as Reserved. Table 16-1. AC `97 Audio PCI Register Address Map (Audio--D30:F2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Eh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 2Ch-2Dh 2Eh-2Fh 34h 3Ch 3Dh 40h 41h 50h-51h 52h-53h 54h-55h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC HEADTYP NAMBAR NABMBAR MMBAR MBBAR SVID SID CAP_PTR INT_LN INT_PN PCID CFG PID PC PCS Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Header Type Native Audio Mixer Base Address Native Audio Bus Mastering Base Address Mixer Base Address (Mem) Bus Master Base Address (Mem) Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin Programmable Codec ID Configuration PCI Power Management Capability ID PC -Power Management Capabilities Power Management Control and Status Default 8086h See register description. 0000h 0280h See register description 00 01h 04h 00h 00000001h 00000001h 00000000h 00000000h 0000h 0000h 50h 00h See register description 09h 00h 0001h C9C2h 0000h Access RO RO R/W, RO R/WC, RO RO RO RO RO RO R/W, RO R/W, RO R/W, RO R/W, RO R/WO R/WO RO R/W RO R/W R/W RO RO R/W, R/ WC Intel (R) ICH7 Family Datasheet 619 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers except the following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0 transition. All resume well registers will not be reset by the D3HOT to D0 transition. Core well registers not reset by the D3HOT to D0 transition: * offset 2Ch-2Dh - Subsystem Vendor ID (SVID) * offset 2Eh-2Fh - Subsystem ID (SID) * offset 40h - Programmable Codec ID (PCID) * offset 41h - Configuration (CFG) Resume well registers will not be reset by the D3HOT to D0 transition: * offset 54h-55h - Power Management Control and Status (PCS) * Bus Mastering Register: Global Status Register, bits 17:16 * Bus Mastering Register: SDATA_IN MAP register, bits 7:3 16.1.1 VID--Vendor Identification Register (Audio--D30:F2) Offset: Default Value: Lockable: Bit 15:0 00h-01h 8086h No Attribute: Size: Power Well: Description RO 16 Bits Core Vendor ID. This is a 16-bit value assigned to Intel. 16.1.2 DID--Device Identification Register (Audio--D30:F2) Offset: Default Value: Lockable: Bit 15:0 02h-03h See bit description No Attribute: Size: Power Well: Description RO 16 Bits Core Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 AC `97 Audio controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 620 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.3 PCICMD--PCI Command Register (Audio--D30:F2) Address Offset: 04h-05h Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/W, RO 16 bits Core PCICMD is a 16-bit control register. Refer to the PCI 2.3 specification for complete details on each bit. Bit 15:11 Reserved. Read 0. Interrupt Disable (ID) -- R/W. 10 0 = The INTx# signals may be asserted and MSIs may be generated. 1 = The AC `97 controller's INTx# signal will be de-asserted and it may not generate MSIs. Fast Back to Back Enable (FBE) -- RO. Not implemented. Hardwired to 0. SERR# Enable (SERR_EN) -- RO. Not implemented. Hardwired to 0. Wait Cycle Control (WCC) -- RO. Not implemented. Hardwired to 0. Parity Error Response (PER) -- RO. Not implemented. Hardwired to 0. VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWIE) -- RO. Not implemented. Hardwired to 0. Special Cycle Enable (SCE). Not implemented. Hardwired to 0. Bus Master Enable (BME) -- R/W. Controls standard PCI bus mastering capabilities. 2 0 = Disable 1 = Enable Memory Space Enable (MSE) -- R/W. Enables memory space addresses to the AC '97 Audio controller. 0 = Disable 1 = Enable I/O Space Enable (IOSE) -- R/W. This bit controls access to the AC '97 Audio controller I/O space registers. 0 0 = Disable (Default). 1 = Enable access to I/O space. The Native PCI Mode Base Address register should be programmed prior to setting this bit. NOTE: This bit becomes writable when the IOSE bit in offset 41h is set. If at any point software decides to clear the IOSE bit, software must first clear the IOS bit. Description 9 8 7 6 5 4 3 1 Intel (R) ICH7 Family Datasheet 621 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.4 PCISTS--PCI Status Register (Audio--D30:F2) Offset: Default Value Lockable: 06h-07h 0280h No Attribute: Size: Power Well: RO, R/WC 16 bits Core PCISTS is a 16-bit status register. Refer to the PCI 2.3 specification for complete details on each bit. Bit 15 14 13 12 11 10:9 8 7 6 5 4 Description Detected Parity Error (DPE). Not implemented. Hardwired to 0. Signaled System Error (SSE) -- RO. Not implemented. Hardwired to 0. Master Abort Status (MAS) -- R/WC. Software clears this bit by writing a 1 to it. 0 = No master abort generated. 1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort. Reserved -- RO. Will always read as 0. Signaled Target Abort (STA) -- RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEV_STS) -- RO. This 2-bit field reflects the Intel(R) ICH7's DEVSEL# timing when performing a positive decode. 01b = Medium timing. Data Parity Error Detected (DPED) -- RO. Not implemented. Hardwired to 0. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. This bit indicates that the ICH7 as a target is capable of fast back-to-back transactions. UDF Supported -- RO. Not implemented. Hardwired to 0. 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. Capabilities List (CAP_LIST) -- RO. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (IS) -- RO. 3 2:0 0 = This bit is 0 after the interrupt is cleared. 1 = This bit is 1 when the INTx# is asserted. Reserved. 16.1.5 RID--Revision Identification Register (Audio--D30:F2) Offset: Default Value: Lockable: Bit 7:0 08h See bit description No Attribute: Size: Power Well: Description RO 8 Bits Core Revision ID -- RO. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. 622 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.6 PI--Programming Interface Register (Audio--D30:F2) Offset: Default Value: Lockable: Bit 7:0 Programming Interface -- RO. 09h 00h No Attribute: Size: Power Well: Description RO 8 bits Core 16.1.7 SCC--Sub Class Code Register (Audio--D30:F2) Address Offset: 0Ah Default Value: 01h Lockable: No Bit 7:0 Sub Class Code (SCC) -- RO. 01h = Audio Device Attribute: Size: Power Well: Description RO 8 bits Core 16.1.8 BCC--Base Class Code Register (Audio--D30:F2) Address Offset: 0Bh Default Value: 04h Lockable: No Bit 7:0 Base Class Code (BCC) -- RO. 04h = Multimedia device Attribute: Size: Power Well: Description RO 8 bits Core 16.1.9 HEADTYP--Header Type Register (Audio--D30:F2) Address Offset: 0Eh Default Value: 00h Lockable: No Bit 7:0 Attribute: Size: Power Well: Description RO 8 bits Core Header Type -- RO. Hardwired to 00h. Intel (R) ICH7 Family Datasheet 623 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.10 NAMBAR--Native Audio Mixer Base Address Register (Audio--D30:F2) Address Offset: 10-13h Default Value: 00000001h Lockable: No Attribute: Size: Power Well: R/W, RO 32 bits Core The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Native Audio Mixer software interface. The mixer requires 256 bytes of I/O space. Native Audio Mixer and Modem codec I/O registers are located from 00h to 7Fh and reside in the codec. Access to these registers will be decoded by the AC '97 controller and forwarded over the AC-link to the codec. The codec will then respond with the register value. In the case of the split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h-7Fh for the primary codec and address offsets 80h-FEh for the secondary codec. Note: The tertiary codec cannot be addressed via this address space. The tertiary space is only available from the new MMBAR register. This register powers up as read only and only becomes write-able when the IOSE bit in offset 41h is set. For description of these I/O registers, refer to the Audio Codec `97 Component Specification, Version 2.3. Bit 31:16 Hardwired to 0s. Base Address -- R/W. These bits are used in the I/O space decode of the Native Audio Mixer interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC `97 mixer, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block size of 256 bytes for this base address. Reserved. Read as 0s. Resource Type Indicator (RTE) -- RO. This bit defaults to 0 and changes to 1 if the IOSE bit is set (D30:F2:Offset 41h, bit 0). When 1, this bit indicates a request for I/O space. Description 15:8 7:1 0 624 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.11 NABMBAR--Native Audio Bus Mastering Base Address Register (Audio--D30:F2) Address Offset: 14h-17h Default Value: 00000001h Lockable: No Attribute: Size: Power Well: R/W, RO 32 bits Core The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Native Mode Audio software interface. Note: The DMA registers for S/PDIF* and Microphone In 2 cannot be addressed via this address space. These DMA functions are only available from the new MBBAR register. This register powers up as read only and only becomes write-able when the IOSE bit in offset 41h is set. Bit 31:16 Hardwired to 0s Base Address -- R/W. These bits are used in the I/O space decode of the Native Audio Bus Mastering interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For AC '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are programmable. This configuration yields a maximum I/O block size of 64 bytes for this base address. Reserved. Read as 0's. Resource Type Indicator (RTE) -- RO. This bit defaults to 0 and changes to 1 if the IOSE bit is set (D30:F2:Offset 41h, bit 0). When 1, this bit indicates a request for I/O space. Description 15:6 5:1 0 16.1.12 MMBAR--Mixer Base Address Register (Audio--D30:F2) Address Offset: 18h-1Bh Default Value: 00000000h Lockable: No Attribute: Size: Power Well: R/W, RO 32 bits Core This BAR creates 512 bytes of memory space to signify the base address of the register space. The lower 256 bytes of this space map to the same registers as the 256-byte I/ O space pointed to by NAMBAR. The lower 384 bytes are divided as follows: * 128 bytes for the primary codec (offsets 00-7Fh) * 128 bytes for the secondary codec (offsets 80-FFh) * 128 bytes for the tertiary codec (offsets 100h-17Fh). * 128 bytes of reserved space (offsets 180h-1FFh), returning all 0's. Bit 31:9 8:3 2:1 0 Description Base Address -- R/W. This field provides the lower 32-bits of the 512-byte memory offset to use for decoding the primary, secondary, and tertiary codec's mixer spaces. Reserved. Read as 0s. Type -- RO. Hardwired to 00b to Indicate the base address exists in 32-bit address space Resource Type Indicator (RTE) -- RO. Hardwired to 0 to indicate a request for memory space. Intel (R) ICH7 Family Datasheet 625 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.13 MBBAR--Bus Master Base Address Register (Audio--D30:F2) Address Offset: 1Ch-1Fh Default Value: 00000000h Lockable: No Attribute: Size: Power Well: R/W, RO 32 bits Core This BAR creates 256-bytes of memory space to signify the base address of the bus master memory space. The lower 64-bytes of the space pointed to by this register point to the same registers as the MBBAR. Bit 31:8 7:3 2:1 0 Description Base Address -- R/W. This field provides the I/O offset to use for decoding the PCM In, PCM Out, and Microphone 1 DMA engines. Reserved. Read as 0s. Type -- RO. Hardwired to 00b to indicate the base address exists in 32-bit address space Resource Type Indicator (RTE) -- RO. Hardwired to 0 to indicate a request for memory space. 16.1.14 SVID--Subsystem Vendor Identification Register (Audio--D30:F2) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/WO 16 bits Core The SVID register, in combination with the Subsystem ID register (D30:F2:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem Vendor ID -- R/WO. Description 626 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.15 SID--Subsystem Identification Register (Audio--D30:F2) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/WO 16 bits Core The SID register, in combination with the Subsystem Vendor ID register (D30:F2:2Ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. T This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem ID -- R/WO. Description 16.1.16 CAP_PTR--Capabilities Pointer Register (Audio--D30:F2) Address Offset: 34h Default Value: 50h Lockable: No Attribute: Size: Power Well: RO 8 bits Core This register indicates the offset for the capability pointer. Bit 7:0 Description Capabilities Pointer (CAP_PTR) -- RO. This field indicates that the first capability pointer offset is offset 50h 16.1.17 INT_LN--Interrupt Line Register (Audio--D30:F2) Address Offset: 3Ch Default Value: 00h Lockable: No Attribute: Size: Power Well: R/W 8 bits Core This register indicates which PCI interrupt line is used for the AC '97 module interrupt. Bit 7:0 Description Interrupt Line (INT_LN) -- R/W. This data is not used by the Intel(R) ICH7. It is used to communicate to software the interrupt line that the interrupt pin is connected to. Intel (R) ICH7 Family Datasheet 627 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.18 INT_PN--Interrupt Pin Register (Audio--D30:F2) Address Offset: 3Dh Default Value: See Description Lockable: No Attribute: Size: Power Well: RO 8 bits Core This register indicates which PCI interrupt pin is used for the AC '97 module interrupt. The AC '97 interrupt is internally OR'd to the interrupt controller with the PIRQB# signal. Bit 7:0 Description AC '97 Interrupt Routing -- RO. This reflects the value of D30IP.AAIP in chipset configuration space. 16.1.19 PCID--Programmable Codec Identification Register (Audio--D30:F2) Address Offset: 40h Default Value: 09h Lockable: No Attribute: Size: Power Well: R/W 8 bits Core This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This register is not affected by the D3HOT to D0 transition. The value in this register must be modified before any AC '97 codec accesses. Bit 7:4 3:2 Reserved. Tertiary Codec ID (TID) -- R/W. These bits define the encoded ID that is used to address the tertiary codec I/O space. Bit 1 is the first bit sent and Bit 0 is the second bit sent on ACZ_SDOUT during slot 0. Secondary Codec ID (SCID) -- R/W. These two bits define the encoded ID that is used to address the secondary codec I/O space. The two bits are the ID that will be placed on slot 0, bits 0 and 1, upon an I/O access to the secondary codec. Bit 1 is the first bit sent and bit 0 is the second bit sent on ACZ_SDOUT during slot 0. Description 1:0 16.1.20 CFG--Configuration Register (Audio--D30:F2) Address Offset: 41h Default Value: 00h Lockable: No Attribute: Size: Power Well: R/W 8 bits Core This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This register is not affected by the D3HOT to D0 transition. Bit 7:1 Reserved--RO. I/O Space Enable (IOSE) -- R/W. 0 0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h become read only registers. Additionally, bit 0 of the I/O BARs at offsets 10h and 14h are hardwired to 0 when this bit is 0. This is the default state for the I/O BARs. BIOS must explicitly set this bit to allow a legacy driver to work. 1 = Enable. Description 628 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.21 PID--PCI Power Management Capability Identification Register (Audio--D30:F2) Address Offset: 50h-51h Default Value: 0001h Lockable: No Bit 15:8 7:0 Attribute: Size: Power Well: Description RO 16 bits Core Next Capability (NEXT) -- RO. This field indicates that the next item in the list is at offset 00h. Capability ID (CAP) -- RO.This field indicates that this pointer is a message signaled interrupt capability 16.1.22 PC--Power Management Capabilities Register (Audio--D30:F2) Address Offset: 52h-53h Default Value: C9C2h Lockable: No Attribute: Size: Power Well: RO 16 bits Core This register is not affected by the D3HOT to D0 transition. Bit 15:11 10:9 8:6 5 4 3 2:0 Description PME Support -- RO. This field indicates PME# can be generated from all D states. Reserved. Auxiliary Current -- RO. This field reports 375 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI)--RO. This field indicates that no device-specific initialization is required. Reserved -- RO. PME Clock (PMEC) -- RO. This field indicates that PCI clock is not required to generate PME#. Version (VER) -- RO. This field indicates support for Revision 1.1 of the PCI Power Management Specification. Intel (R) ICH7 Family Datasheet 629 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.1.23 PCS--Power Management Control and Status Register (Audio--D30:F2) Address Offset: 54h-55h Default Value: 0000h Lockable: No Bit Attribute: Size: Power Well: Description R/W, R/WC 16 bits Resume PME Status (PMES) -- R/WC. This bit resides in the resume well. Software clears this bit by writing a 1 to it. 15 0 = PME# signal Not asserted by AC `97 controller. 1 = This bit is set when the AC '97 controller would normally assert the PME# signal independent of the state of the PME_En bit. Reserved -- RO. Power Management Event Enable (PMEE) -- R/W. 8 0 = Disable. 1 = Enable. When set, and if corresponding PMES is also set, the AC '97 controller sets the AC97_STS bit in the GPE0_STS register Reserved--RO. Power State (PS) -- R/W. This field is used both to determine the current power state of the AC '97 controller and to set a new power state. The values are: 00 = D0 state 01 = not supported 1:0 10 = not supported 11 = D3HOT state When in the D3HOT state, the AC '97 controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 14:9 7:2 630 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2 AC '97 Audio I/O Space (D30:F2) The AC '97 I/O space includes Native Audio Bus Master registers and Native Mixer registers. For the ICH7, the offsets are important as they will determine bits 1:0 of the TAG field (codec ID). Audio Mixer I/O space can be accessed as a 16-bit field only since the data packet length on AC-link is a word. Any S/W access to the codec will be done as a 16-bit access starting from the first active byte. In case no byte enables are active, the access will be done at the first word of the qWord that contains the address of this request. Table 16-2. Intel(R) ICH7 Audio Mixer Register Configuration (Sheet 1 of 2) Primary Offset (Codec ID =00) 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch-56h 58h Secondary Offset (Codec ID =01) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BC-D6h D8h Tertiary Offset (Codec ID =10) 100h 102h 104h 106h 108h 10Ah 10Ch 10Eh 110h 112h 114h 116h 118h 11Ah 11Ch 11Eh 120h 122h 124h 126h 128h 12Ah 12Ch 12Eh 130h 132h 134h 136h 138h 13Ah 13C-156h 158h NAMBAR Exposed Registers (D30:F2) Reset Master Volume Aux Out Volume Mono Volume Master Tone (R & L) PC_BEEP Volume Phone Volume Mic Volume Line In Volume CD Volume Video Volume Aux In Volume PCM Out Volume Record Select Record Gain Record Gain Mic General Purpose 3D Control AC '97 RESERVED Powerdown Ctrl/Stat Extended Audio Extended Audio Ctrl/Stat PCM Front DAC Rate PCM Surround DAC Rate PCM LFE DAC Rate PCM LR ADC Rate MIC ADC Rate 6Ch Vol: C, LFE 6Ch Vol: L, R Surround S/PDIF Control Intel RESERVED AC '97 Reserved Intel (R) ICH7 Family Datasheet 631 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Table 16-2. Intel(R) ICH7 Audio Mixer Register Configuration (Sheet 2 of 2) Primary Offset (Codec ID =00) 5Ah 7Ch 7Eh Secondary Offset (Codec ID =01) DAh FCh FEh Tertiary Offset (Codec ID =10) 15Ah 17Ch 17Eh NAMBAR Exposed Registers (D30:F2) Vendor Reserved Vendor ID1 Vendor ID2 NOTE: 1. Software should not try to access reserved registers 2. Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of configuration register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration register 40h. 3. The tertiary offset is only available through the memory space defined by the MMBAR register. The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC '97 controller. Accesses to these registers do not cause the cycle to be forwarded over the AC-link to the codec. S/W could access these registers as bytes, word, DWord or qword quantities, but reads must not cross DWord boundaries. In the case of the split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h-7Fh for the primary codec, address offsets 80h-FFh for the secondary codec and address offsets 100h-17Fh for the tertiary codec. The Global Control (GLOB_CNT) (D30:F2:2Ch) and Global Status (GLOB_STA) (D30:F2:30h) registers are aliased to the same global registers in the audio and modem I/O space. Therefore a read/write to these registers in either audio or modem I/O space affects the same physical register. Bus Mastering registers exist in I/O space and reside in the AC '97 controller. The six channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their own set of Bus Mastering registers. The following register descriptions apply to all six channels. The register definition section titles use a generic "x_" in front of the register to indicate that the register applies to all six channels. The naming prefix convention used in Table 16-3 and in the register description I/O address is as follows: PI = PCM in channel PO = PCM out channel MC = Mic in channel MC2 = Mic 2 channel PI2 = PCM in 2 channel SP = S/PDIF out channel. 632 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Table 16-3. Native Audio Bus Master Control Registers (Sheet 1 of 2) Offset 00h 04h 05h 06h 08h 0Ah 0Bh 10h 14h 15h 16h 18h 1Ah 1Bh 20h 24h 25h 26h 28h 2Ah 2Bh 2Ch 30h 34h 40h 44h 45h 46h 48h 4Ah 4Bh 50h Mnemonic PI_BDBAR PI_CIV PI_LVI PI_SR PI_PICB PI_PIV PI_CR PO_BDBAR PO_CIV PO_LVI PO_SR PO_PICB PO_PIV PO_CR MC_BDBAR MC_CIV MC_LVI MC_SR MC_PICB MC_PIV MC_CR GLOB_CNT GLOB_STA CAS MC2_BDBAR MC2_CIV MC2_LVI MC2_SR MC2_PICB MC2_PIV MC2_CR PI2_BDBAR Name PCM In Buffer Descriptor list Base Address PCM In Current Index Value PCM In Last Valid Index PCM In Status PCM In Position in Current Buffer PCM In Prefetched Index Value PCM In Control PCM Out Buffer Descriptor list Base Address PCM Out Current Index Value PCM Out Last Valid Index PCM Out Status PCM In Position In Current Buffer PCM Out Prefetched Index Value PCM Out Control Mic. In Buffer Descriptor List Base Address Mic. In Current Index Value Mic. In Last Valid Index Mic. In Status Mic. In Position In Current Buffer Mic. In Prefetched Index Value Mic. In Control Global Control Global Status Codec Access Semaphore Mic. 2 Buffer Descriptor List Base Address Mic. 2 Current Index Value Mic. 2 Last Valid Index Mic. 2 Status Mic 2 Position In Current Buffer Mic. 2 Prefetched Index Value Mic. 2 Control PCM In 2 Buffer Descriptor List Base Address Default 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h See register description 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00000000h Access R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W, R/W (special) R/W, R/WC, RO R/W (special) R/W RO R/W RO, R/WC RO RO R/W, R/W (special) R/W Intel (R) ICH7 Family Datasheet 633 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Table 16-3. Native Audio Bus Master Control Registers (Sheet 2 of 2) Offset 54h 55h 56h 58h 5Ah 5Bh 60h 64h 65h 66h 68h 6Ah 6Bh 80h Mnemonic PI2_CIV PI2_LVI PI2_SR PI2_PICB PI2_PIV PI2_CR SPBAR SPCIV SPLVI SPSR SPPICB SPPIV SPCR SDM Name PCM In 2 Current Index Value PCM In 2 Last Valid Index PCM In 2 Status PCM In 2 Position in Current Buffer PCM In 2 Prefetched Index Value PCM In 2 Control S/PDIF Buffer Descriptor List Base Address S/PDIF Current Index Value S/PDIF Last Valid Index S/PDIF Status S/PDIF Position In Current Buffer S/PDIF Prefetched Index Value S/PDIF Control SData_IN Map Default 00h 00h 0001h 0000h 00h 00h 00000000h 00h 00h 0001h 0000h 00h 00h 00h Access RO R/W R/WC, RO RO RO R/W, R/W (special) R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W, RO Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers except the registers shared with the AC '97 Modem (GCR, GSR, CASR). All resume well registers will not be reset by the D3HOT to D0 transition. Core well registers and bits not reset by the D3HOT to D0 transition: * offset 2Ch-2Fh - bits 6:0 Global Control (GLOB_CNT) * offset 30h-33h - bits [29,15,11:10,0] Global Status (GLOB_STA) * offset 34h - Codec Access Semaphore Register (CAS) Resume well registers and bits will not be reset by the D3HOT to D0 transition: * offset 30h-33h - bits [17:16] Global Status (GLOB_STA) 634 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.1 x_BDBAR--Buffer Descriptor Base Address Register (Audio--D30:F2) I/O Address: NABMBAR + 00h (PIBDBAR), Attribute: NABMBAR + 10h (POBDBAR), NABMBAR + 20h (MCBDBAR) MBBAR + 40h (MC2BDBAR) MBBAR + 50h (PI2BDBAR) MBBAR + 60h (SPBAR) 00000000h Size: No Power Well: R/W Default Value: Lockable: 32 bits Core Software can read the register at offset 00h by performing a single 32-bit read from address offset 00h. Reads across DWord boundaries are not supported. Bit 31:3 2:0 Description Buffer Descriptor Base Address[31:3] -- R/W. These bits represent address bits 31:3. The data should be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can contain a maximum of 32 entries. Hardwired to 0. 16.2.2 x_CIV--Current Index Value Register (Audio--D30:F2) I/O Address: NABMBAR + 04h (PICIV), Attribute: NABMBAR + 14h (POCIV), NABMBAR + 24h (MCCIV) MBBAR + 44h (MC2CIV) MBBAR + 54h (PI2CIV) MBBAR + 64h (SPCIV) 00h Size: No Power Well: RO Default Value: Lockable: 8 bits Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 8-bit read to offset 04h. Bit 7:5 4:0 Hardwired to 0 Current Index Value [4:0] -- RO. These bits represent which buffer descriptor within the list of 32 descriptors is currently being processed. As each descriptor is processed, this value is incremented. The value rolls over after it reaches 31. Description NOTE: Reads across DWord boundaries are not supported. Intel (R) ICH7 Family Datasheet 635 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.3 x_LVI--Last Valid Index Register (Audio--D30:F2) I/O Address: NABMBAR + 05h (PILVI), Attribute: NABMBAR + 15h (POLVI), NABMBAR + 25h (MCLVI) MBBAR + 45h (MC2LVI) MBBAR + 55h (PI2LVI) MBBAR + 65h (SPLVI) 00h Size: No Power Well: R/W Default Value: Lockable: 8 bits Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 8-bit read to offset 05h. Bit 7:5 4:0 Hardwired to 0. Last Valid Index [4:0] -- R/W. This value represents the last valid descriptor in the list. This value is updated by the software each time it prepares a new buffer and adds it to the list. Description NOTE: Reads across DWord boundaries are not supported. 16.2.4 x_SR--Status Register (Audio--D30:F2) I/O Address: NABMBAR + 06h (PISR), NABMBAR + 16h (POSR), NABMBAR + 26h (MCSR) MBBAR + 46h (MC2SR) MBBAR + 56h (PI2SR) MBBAR + 66h (SPSR) 0001h No Attribute: R/WC, RO Default Value: Lockable: Size: Power Well: 16 bits Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 16-bit read to offset 06h. Reads across DWord boundaries are not supported. 636 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Bit 15:5 Reserved. Description FIFO Error (FIFOE) -- R/WC. Software clears this bit by writing a 1 to it. 0 = No FIFO error. 1 = FIFO error occurs. 4 PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers don't increment, the incoming data is not written into the FIFO, thus is lost. POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this case should be the last valid sample. The Intel(R) ICH7 will set the FIFO bit if the under-run or overrun occurs when there are more valid buffers to process. Buffer Completion Interrupt Status (BCIS) -- R/WC. 3 0 = Software clears this bit by writing a 1 to it. 1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active until cleared by software. Last Valid Buffer Completion Interrupt (LVBCI) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Last valid buffer has been processed. It remains active until cleared by software. This bit indicates the occurrence of the event signified by the last valid buffer being processed. Thus this is an event status bit that can be cleared by software once this event has been recognized. This event will cause an interrupt if the enable bit (D30:F2:NABMBAR + 0Bh, bit 2) in the Control Register is set. The interrupt is cleared when the software clears this bit. In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). While in the case of Receives, this bit is set after the data for the last buffer has been written to memory. Current Equals Last Valid (CELV) -- RO. 0 = Cleared by hardware when controller exists state (i.e., until a new value is written to the LVI register.) 1 = Current Index is equal to the value in the Last Valid Index Register (D30:F2:NABMBAR + 05h), and the buffer pointed to by the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is very similar to bit 2, except this bit reflects the state rather than the event. This bit reflects the state of the controller, and remains set until the controller exits this state. DMA Controller Halted (DCH) -- RO. 0 0 = Running. 1 = Halted. This could happen because of the Start/Stop bit being cleared and the DMA engines are idle, or it could happen once the controller has processed the last valid buffer. 2 1 Intel (R) ICH7 Family Datasheet 637 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.5 x_PICB--Position In Current Buffer Register (Audio--D30:F2) I/O Address: NABMBAR + 08h (PIPICB), Attribute: NABMBAR + 18h (POPICB), NABMBAR + 28h (MCPICB) MBBAR + 48h (MC2PICB) MBBAR + 58h (PI2PICB) MBBAR + 68h (SPPICB) 0000h Size: No Power Well: RO Default Value: Lockable: 16 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 16-bit read to offset 08h. Reads across DWord boundaries are not supported. Bit Description Position In Current Buffer [15:0] -- RO. These bits represent the number of samples left to be processed in the current buffer. This means the number of samples not yet read from memory (in the case of reads from memory) or not yet written to memory (in the case of writes to memory), irrespective of the number of samples that have been transmitted/received across AC-link. 15:0 16.2.6 x_PIV--Prefetched Index Value Register (Audio--D30:F2) I/O Address: NABMBAR + 0Ah (PIPIV), Attribute: NABMBAR + 1Ah (POPIV), NABMBAR + 2Ah (MCPIV) MBBAR + 4Ah (MC2PIV) MBBAR + 5Ah (PI2PIV) MBBAR + 6Ah (SPPIV) 00h Size: No Power Well: RO Default Value: Lockable: 8 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 8-bit read to offset 0Ah. Reads across DWord boundaries are not supported Bit 7:5 4:0 Hardwired to 0. Prefetched Index Value [4:0] -- RO. These bits represent which buffer descriptor in the list has been prefetched. The bits in this register are also modulo 32 and roll over after they reach 31. Description 638 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.7 x_CR--Control Register (Audio--D30:F2) I/O Address: NABMBAR + 0Bh (PICR), NABMBAR + 1Bh (POCR), NABMBAR + 2Bh (MCCR) MBBAR + 4Bh (MC2CR) MBBAR + 5Bh (PI2CR) MBBAR + 6Bh (SPCR) 00h No Attribute: R/W, R/W (special) Default Value: Lockable: Size: Power Well: 8 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 8-bit read to offset 0Bh. Reads across DWord boundaries are not supported. Bit 7:5 Reserved. Interrupt on Completion Enable (IOCE) -- R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. 0 = Disable. Interrupt will not occur. 1 = Enable. FIFO Error Interrupt Enable (FEIE) -- R/W. This bit controls whether the occurrence of a FIFO error will cause an interrupt or not. 0 = Disable. Bit 4 in the Status register will be set, but the interrupt will not occur. 1 = Enable. Interrupt will occur. Last Valid Buffer Interrupt Enable (LVBIE) -- R/W. This bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur. 1 = Enable. Reset Registers (RR) -- R/W (special). 0 = Removes reset condition. 1 = Contents of all Bus master related registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). Software needs to set this bit but need not clear it since the bit is self clearing. This bit must be set only when the Run/Pause bit (D30:F2:2Bh, bit 0) is cleared. Setting it when the Run bit is set will cause undefined consequences. Run/Pause Bus Master (RPBM) -- R/W. 0 0 = Pause bus master operation. This results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = Run. Bus master operation starts. Description 4 3 2 1 Intel (R) ICH7 Family Datasheet 639 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.8 GLOB_CNT--Global Control Register (Audio--D30:F2) I/O Address: Default Value: Lockable: Bit NABMBAR + 2Ch 00000000h No Attribute: Size: Power Well: Description R/W, R/W (special) 32 bits Core 31:30 S/PDIF Slot Map (SSM) -- R/W. If the run/pause bus master bit (bit 0 of offset 2Bh) is set, then the value in these bits indicate which slots S/PDIF data is transmitted on. Software must ensure that the programming here does not conflict with the PCM channels being used. If there is a conflict, unpredictable behavior will result -- the hardware will not check for a conflict. 00 = Reserved 01 = Slots 7 and 8 10 = Slots 6 and 9 11 = Slots 10 and 11 29:24 Reserved. PCM Out Mode (POM) -- R/W. Enables the PCM out channel to use 16- or 20-bit audio on PCM out. This does not affect the microphone of S/PDIF DMA. When greater than 16-bit audio is used, the data structures are aligned as 32-bits per sample, with the highest order bits representing the data, and the lower order bits as don't care. 00 = 16 bit audio (default) 01 = 20 bit audio 10 = Reserved. If set, indeterminate behavior will result. 11 = Reserved. If set, indeterminate behavior will result. PCM 4/6 Enable -- R/W. This field configures PCM Output for 2-, 4- or 6-channel mode. 23:22 21:20 00 01 10 11 = = = = 2-channel mode (default) 4-channel mode 6-channel mode Reserved 19:7 Reserved. ACZ_SDIN2 Interrupt Enable -- R/W. 0 = Disable. 1 = Enable an interrupt to occur when the codec on the ACZ_SDIN2 causes a resume event on the AC-link. NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. ACZ_SDIN1 Interrupt Enable -- R/W. 0 = Disable. 1 = Enable an interrupt to occur when the codec on the ACZ_SDIN1 causes a resume event on the AC-link. NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. ACZ_SDIN0 Interrupt Enable -- R/W. 0 = Disable. 1 = Enable an interrupt to occur when the codec on ACZ_SDIN0 causes a resume event on the AC-link. NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. 6 5 4 640 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Bit AC-LINK Shut Off (LSO) -- R/W. 3 Description 0 = Normal operation. 1 = Controller disables all outputs which will be pulled low by internal pull down resistors. NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. AC '97 Warm Reset -- R/W (special). 0 = Normal operation. 1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken a suspended codec without clearing its internal registers. If software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit is self-clearing (it remains set until the reset completes and bit_clk is seen on the AC-link, after which it clears itself). NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. AC '97 Cold Reset# -- R/W. 0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC `97 circuitry. All data in the controller and the codec will be lost. Software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. The value of this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset is not generated automatically upon resuming. NOTE: This bit is in the core well and is not affected by AC `97 Audio Function D3HOT to D0 reset. GPI Interrupt Enable (GIE) -- R/W. This bit controls whether the change in status of any GPI causes an interrupt. 2 1 0 0 = Bit 0 of the Global Status register is set, but no interrupt is generated. 1 = The change in value of a GPI causes an interrupt and sets bit 0 of the Global Status register. NOTE: This bit is not affected by AC `97 Audio Function D3HOT to D0 reset. NOTE: Reads across DWord boundaries are not supported. Intel (R) ICH7 Family Datasheet 641 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.9 GLOB_STA--Global Status Register (Audio--D30:F2) I/O Address: NABMBAR + 30h Attribute: RO, R/W, R/WC Default Value: 00x0xxx01110000000000xxxxx00xxxb Size: 32 bits Lockable: No Power Well: Core Bit 31:30 Reserved. ACZ_SDIN2 Resume Interrupt (S2RI) -- R/WC. This bit indicates a resume event occurred on ACZ_SDIN2. Software clears this bit by writing a 1 to it. 29 0 = Resume event did Not occur. 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN2 Codec Ready (S2CR) -- RO. Reflects the state of the codec ready bit on ACZ_SDIN2. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. Bit Clock Stopped (BCS) 27 Description 28 -- RO. This bit indicates that the bit clock is not running. 0 = Transition is found on BIT_CLK. 1 = Intel(R) ICH7 detected that there has been no transition on BIT_CLK for four consecutive PCI clocks. S/PDIF Interrupt (SPINT) -- RO. -- RO. -- RO. 26 0 = When the specific status bit is cleared, this bit will be cleared. 1 = S/PDIF out channel interrupt status bits have been set. PCM In 2 Interrupt (P2INT) 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM In 2 channel status bits have been set. Microphone 2 In Interrupt (M2INT) 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the Mic in channel interrupts status bits has been set. Sample Capabilities 16-bit audio. 25 24 -- RO. This field indicates the capability to support greater than 23:22 00 = Reserved 01 = 16 and 20-bit Audio supported (ICH7 value) 10 = Reserved 11 = Reserved Multichannel Capabilities-- RO. This field indicates the capability to support more 4 and 6 channels on PCM Out. Reserved. MD3 -- R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state. NOTE: This bit is not affected by D3HOT to D0 Reset. 21:20 19:18 17 642 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Bit Description AD3 -- R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state. NOTE: This bit is not affected by D3HOT to D0 Reset. Read Completion Status (RCS) -- R/WC. This bit indicates the status of codec read completions. 16 15 0 = A codec read completes normally. 1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a 1 to the bit location. NOTE: This bit is not affected by D3HOT to D0 Reset. 14 13 12 Bit 3 of Slot 12 -- RO. Display bit 3 of the most recent slot 12. Bit 2 of Slot 12 -- RO. Display bit 2 of the most recent slot 12. Bit 1 of slot 12 -- RO. Display bit 1 of the most recent slot 12. ACZ_SDIN1 Resume Interrupt (S1R1) -- R/WC. This bit indicates that a resume event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it. 11 0 = Resume event did Not occur 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN1 Resume Interrupt (S1R1) -- R/WC. This bit indicates that a resume event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it. 10 0 = Resume event did Not occur 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN0 Codec Ready (S0CR) -- RO. Reflects the state of the codec ready bit in ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. ACZ_SDIN0 Codec Ready (S0CR) -- RO. Reflects the state of the codec ready bit in ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. Microphone In Interrupt (MINT) -- RO. 9 8 7 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the Mic in channel interrupts status bits has been set. PCM Out Interrupt (POINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM out channel interrupts status bits has been set. PCM In Interrupt (PIINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM in channel interrupts status bits has been set. Reserved 6 5 4:3 Intel (R) ICH7 Family Datasheet 643 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) Bit 2 Description Modem Out Interrupt (MOINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the modem out channel interrupts status bits has been set. Modem In Interrupt (MIINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the modem in channel interrupts status bits has been set. GPI Status Change Interrupt (GSCI) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This indicates that one of the GPI's has changed state, and that the new values are available in slot 12. This bit is not affected by AC `97 Audio Function D3HOT to D0 Reset. 1 0 NOTE: Reads across DWord boundaries are not supported. 16.2.10 CAS--Codec Access Semaphore Register (Audio--D30:F2) I/O Address: Default Value: Lockable: Bit 7:1 Reserved. Codec Access Semaphore (CAS) -- R/W (special). This bit is read by software to check whether a codec access is currently in progress. 0 0 = No access in progress. 1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform an I/O access. Once the access is completed, hardware automatically clears this bit. NABMBAR + 34h 00h No Attribute: Size: Power Well: Description R/W (special) 8 bits Core NOTE: Reads across DWord boundaries are not supported. 644 Intel (R) ICH7 Family Datasheet AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 16.2.11 SDM--SDATA_IN Map Register (Audio--D30:F2) I/O Address: Default Value: Lockable: Bit NABMBAR + 80h 00h No Attribute: Size: Power Well: Description R/W, RO 8 bits Core 7:6 PCM In 2, Microphone In 2 Data In Line (DI2L)-- R/W. When the SE bit is set, these bits indicates which ACZ_SDIN line should be used by the hardware for decoding the input slots for PCM In 2 and Microphone In 2. When the SE bit is cleared, the value of these bits are irrelevant, and PCM In 2 and Mic In 2 DMA engines are not available. 00 01 10 11 = = = = ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 Reserved 5:4 PCM In 1, Microphone In 1 Data In Line (DI1L)-- R/W. When the SE bit is set, these bits indicates which ACZ_SDIN line should be used by the hardware for decoding the input slots for PCM In 1 and Microphone In 1. When the SE bit is cleared, the value of these bits are irrelevant, and the PCM In 1 and Mic In 1 engines use the OR'd ACZ_SDIN lines. 00 01 10 11 = = = = ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 Reserved 3 Steer Enable (SE) -- R/W. When set, the ACZ_SDIN lines are treated separately and not OR'd together before being sent to the DMA engines. When cleared, the ACZ_SDIN lines are OR'd together, and the "Microphone In 2" and "PCM In 2" DMA engines are not available. Reserved -- RO. Last Codec Read Data Input (LDI) -- RO. When a codec register is read, this indicates which ACZ_SDIN the read data returned on. Software can use this to determine how the codecs are mapped. The values are: 2 1:0 00 01 10 11 = = = = ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 Reserved NOTE: Reads across DWord boundaries are not supported. Intel (R) ICH7 Family Datasheet 645 AC '97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) 646 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) AC `97 is not supported on ICH7-U Ultra Mobile. Note: 17.1 Note: AC '97 Modem PCI Configuration Space (D30:F3) Registers that are not shown should be treated as Reserved. Table 17-1. AC `97 Modem PCI Register Address Map (Modem--D30:F3) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Eh 10h-13h 14h-17h 2Ch-2Dh 2Eh-2Fh 34h 3Ch 3Dh 50h-51h 52h-53h 54h-55h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC HEADTYP MMBAR MBAR SVID SID CAP_PTR INT_LN INT_PN PID PC PCS Register Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Header Type Modem Mixer Base Address Modem Base Address Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Interrupt Line Interrupt Pin PCI Power Management Capability ID Power Management Capabilities Power Management Control and Status Default 8086 See register description 0000h 0290h See register description 00h 03h 07h 00h 00000001h 00000001h 0000h 0000h 50h 00h See register description 0001h C9C2h 0000h Access RO RO R/W, RO R/WC, RO RO RO RO RO RO R/W, RO R/W, RO R/WO R/WO RO R/W RO RO RO R/W, R/WC Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers except the following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0 transition. All resume well registers will not be reset by the D3HOT to D0 transition. Core well registers not reset by the D3HOT to D0 transition: * offset 2Ch-2Dh - Subsystem Vendor ID (SVID) * offset 2Eh-2Fh - Subsystem ID (SID) Resume well registers will not be reset by the D3HOT to D0 transition: * offset 54h-55h - Power Management Control and Status (PCS) Intel (R) ICH7 Family Datasheet 647 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.1 VID--Vendor Identification Register (Modem--D30:F3) Address Offset: 00h-01h Default Value: 8086 Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 Bits Core Vendor ID -- RO. This is a 16-bit value assigned to Intel. 17.1.2 DID--Device Identification Register (Modem--D30:F3) Address Offset: 02h-03h Default Value: See bit description Lockable: No Bit 15:0 Attribute: Size: Power Well: Description RO 16 Bits Core Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 AC `97 Modem controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 17.1.3 PCICMD--PCI Command Register (Modem--D30:F3) Address Offset: 04h-05h Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/W, RO 16 bits Core PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification for complete details on each bit. Bit 15:11 Reserved. Read 0. Interrupt Disable (ID)-- R/W. 10 0 = The INTx# signals may be asserted and MSIs may be generated. 1 = The AC `97 controller's INTx# signal will be de-asserted and it may not generate MSIs. Fast Back to Back Enable (FBE) -- RO. Not implemented. Hardwired to 0. SERR# Enable (SERR_EN) -- RO. Not implemented. Hardwired to 0. Wait Cycle Control (WCC) -- RO. Not implemented. Hardwired to 0. Parity Error Response (PER) -- RO. Not implemented. Hardwired to 0. VGA Palette Snoop (VPS) -- RO. Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWIE) -- RO. Not implemented. Hardwired to 0. Special Cycle Enable (SCE) -- RO. Not implemented. Hardwired to 0. Bus Master Enable (BME) -- R/W. This bit controls standard PCI bus mastering capabilities. 0 = Disable 1 = Enable Memory Space Enable (MSE) -- RO. Hardwired to 0, AC `97 does not respond to memory accesses. I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 0 = Disable access. (default = 0). 1 = Enable access to I/O space. The Native PCI Mode Base Address register should be programmed prior to setting this bit. Description 9 8 7 6 5 4 3 2 1 648 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.4 PCISTS--PCI Status Register (Modem--D30:F3) Address Offset: 06h-07h Default Value: 0290h Lockable: No Attribute: Size: Power Well: R/WC, RO 16 bits Core PCISTS is a 16-bit status register. Refer to the PCI Local Bus Specification for complete details on each bit. Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit 15 14 13 12 11 10:9 8 7 6 5 4 Description Detected Parity Error (DPE) -- RO. Not implemented. Hardwired to 0. Signaled System Error (SSE) --RO. Not implemented. Hardwired to 0. Master Abort Status (MAS) -- R/WC. 0 = Master abort Not generated by bus master AC `97 function. 1 = Bus Master AC `97 interface function, as a master, generates a master abort. Reserved. Read as 0. Signaled Target Abort (STA) -- RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEV_STS) -- RO. This 2-bit field reflects the ICH7's DEVSEL# timing parameter. These read only bits indicate the ICH7's DEVSEL# timing when performing a positive decode. Data Parity Error Detected (DPED) -- RO. Not implemented. Hardwired to 0. Fast Back to Back Capable (FB2BC) -- RO. Hardwired to 1. This bit indicates that the ICH7 as a target is capable of fast back-to-back transactions. User Definable Features (UDF) -- RO. Not implemented. Hardwired to 0. 66 MHz Capable (66MHZ_CAP) -- RO. Hardwired to 0. Capabilities List (CAP_LIST) -- RO. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (INTS) -- RO. 3 2:0 0 = This bit is 0 after the interrupt is cleared. 1 = This bit is 1 when the INTx# is asserted. Reserved Intel (R) ICH7 Family Datasheet 649 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.5 RID--Revision Identification Register (Modem--D30:F3) Address Offset: 08h Default Value: See bit description Lockable: No Bit 7:0 Attribute: Size: Power Well: Description RO 8 Bits Core Revision ID -- RO. Refer to the I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. Intel(R) 17.1.6 PI--Programming Interface Register (Modem--D30:F3) Address Offset: 09h Default Value: 00h Lockable: No Bit 7:0 Programming Interface -- RO. Attribute: Size: Power Well: Description RO 8 bits Core 17.1.7 SCC--Sub Class Code Register (Modem--D30:F3) Address Offset: 0Ah Default Value: 03h Lockable: No Bit 7:0 Sub Class Code -- RO. 03h = Generic Modem. Attribute: Size: Power Well: Description RO 8 bits Core 17.1.8 BCC--Base Class Code Register (Modem--D30:F3) Address Offset: 0Bh Default Value: 07h Lockable: No Bit 7:0 Base Class Code -- RO. 07h = Simple Communications controller. Attribute: Size: Power Well: Description RO 8 bits Core 17.1.9 HEADTYP--Header Type Register (Modem--D30:F3) Address Offset: 0Eh Default Value: 00h Lockable: No Bit 7:0 Header Type -- RO. Attribute: Size: Power Well: Description RO 8 bits Core 650 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.10 MMBAR--Modem Mixer Base Address Register (Modem--D30:F3) Address Offset: 10-13h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Native PCI Mode Modem uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Modem Mixer software interface. The mixer requires 256 bytes of I/O space. All accesses to the mixer registers are forwarded over the AC-link to the codec where the registers reside. In the case of the split codec implementation accesses to the different codecs are differentiated by the controller by using address offsets 00h-7Fh for the primary codec and address offsets 80h-FEh for the secondary codec. Bit 31:16 Hardwired to 0's. Base Address -- R/W. These bits are used in the I/O space decode of the Modem interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC `97 Modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block size of 256 bytes for this base address. Reserved. Read as 0 Resource Type Indicator (RTE) -- RO. Hardwired to 1indicating a request for I/O space. Description 15:8 7:1 0 17.1.11 MBAR--Modem Base Address Register (Modem--D30:F3) Address Offset: 14h-17h Default Value: 00000001h Attribute: Size: R/W, RO 32 bits The Modem function uses PCI Base Address register #1 to request a contiguous block of I/O space that is to be used for the Modem software interface. The Modem Bus Mastering register space requires 128 bytes of I/O space. All Modem registers reside in the controller, therefore cycles are not forwarded over the AC-link to the codec. Bit 31:16 Hardwired to 0's. Base Address -- R/W. These bits are used in the I/O space decode of the Modem interface registers. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For the AC `97 Modem, the upper 16 bits are hardwired to 0, while bits 15:7 are programmable. This configuration yields a maximum I/O block size of 128 bytes for this base address. Reserved. Read as 0 Resource Type Indicator (RTE) -- RO. Hardwired to 1 indicating a request for I/O space. Description 15:7 6:1 0 Intel (R) ICH7 Family Datasheet 651 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.12 SVID--Subsystem Vendor Identification Register (Modem--D30:F3) Address Offset: 2Ch-2Dh Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/WO 16 bits Core The SVID register, in combination with the Subsystem ID register, enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem Vendor ID -- R/WO. Description 17.1.13 SID--Subsystem Identification Register (Modem--D30:F3) Address Offset: 2Eh-2Fh Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/WO 16 bits Core The SID register, in combination with the Subsystem Vendor ID register make it possible for the operating environment to distinguish one audio subsystem from another. This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem ID -- R/WO. Description 17.1.14 CAP_PTR--Capabilities Pointer Register (Modem--D30:F3) Address Offset: 34h Default Value: 50h Lockable: No Attribute: Size: Power Well: RO 8 bits Core This register indicates the offset for the capability pointer. Bit 7:0 Description Capabilities Pointer (CAP_PTR) -- RO. This field indicates that the first capability pointer offset is offset 50h 652 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.15 INT_LN--Interrupt Line Register (Modem--D30:F3) Address Offset: 3Ch Default Value: 00h Lockable: No Attribute: Size: Power Well: R/W 8 bits Core This register indicates which PCI interrupt line is used for the AC '97 module interrupt. Bit 7:0 Description Interrupt Line (INT_LN) -- R/W. This data is not used by the Intel(R) ICH7. It is used to communicate to software the interrupt line that the interrupt pin is connected to. 17.1.16 INT_PIN--Interrupt Pin Register (Modem--D30:F3) Address Offset: 3Dh Default Value: See description Lockable: No Attribute: Size: Power Well: RO 8 bits Core This register indicates which PCI interrupt pin is used for the AC '97 modem interrupt. The AC '97 interrupt is internally OR'd to the interrupt controller with the PIRQB# signal. Bit 7:3 2:0 Reserved Interrupt Pin (INT_PN) -- RO. This reflects the value of D30IP.AMIP in chipset configuration space. Description 17.1.17 PID--PCI Power Management Capability Identification Register (Modem--D30:F3) Address Offset: 50h Default Value: 0001h Lockable: No Bit 15:8 7:0 Attribute: Size: Power Well: Description RO 16 bits Core Next Capability (NEXT) -- RO. This field indicates that this is the last item in the list. Capability ID (CAP) -- RO. This field indicates that this pointer is a message signaled interrupt capability. Intel (R) ICH7 Family Datasheet 653 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.1.18 PC--Power Management Capabilities Register (Modem--D30:F3) Address Offset: 52h Default Value: C9C2h Lockable: No Bit 15:11 10:9 8:6 5 4 3 2:0 Attribute: Size: Power Well: Description RO 16 bits Core PME Support -- RO. This field indicates PME# can be generated from all D states. Reserved. Auxiliary Current -- RO. This field reports 375 mA maximum Suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) -- RO. This bit indicates that no device-specific initialization is required. Reserved -- RO. PME Clock (PMEC) -- RO. This bit indicates that PCI clock is not required to generate PME#. Version (VS) -- RO. This field indicates support for Revision 1.1 of the PCI Power Management Specification. 17.1.19 PCS--Power Management Control and Status Register (Modem--D30:F3) Address Offset: 54h Default Value: 0000h Lockable: No Attribute: Size: Power Well: R/W, R/WC 16 bits Resume This register is not affected by the D3HOT to D0 transition. Bit PME Status (PMES) -- R/WC. 15 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the AC '97 controller would normally assert the PME# signal independent of the state of the PME_En bit. This bit resides in the resume well. Reserved -- RO. PME Enable (PMEE) -- R/W. 8 0 = Disable. 1 = Enable. When set, and if corresponding PMES is also set, the AC '97 controller sets the AC97_STS bit in the GPE0_STS register. Reserved -- RO. Power State (PS) -- R/W. This field is used both to determine the current power state of the AC '97 controller and to set a new power state. The values are: 00 = D0 state 01 = not supported 1:0 10 = not supported 11 = D3HOT state When in the D3HOT state, the AC '97 controller's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. Description 14:9 7:2 654 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2 AC '97 Modem I/O Space (D30:F3) In the case of the split codec implementation accesses to the modem mixer registers in different codecs are differentiated by the controller by using address offsets 00h-7Fh for the primary codec and address offsets 80h-FEh for the secondary codec. Table 17-2 shows the register addresses for the modem mixer registers. Table 17-2. Intel(R) ICH7 Modem Mixer Register Configuration Register Primary 00h:38h 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 7Ch 7Eh Secondary 80h:B8h BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh D0h D2h D4h D6h D8h DAh FCh FEh Intel RESERVED Extended Modem ID Extended Modem Stat/Ctrl Line 1 DAC/ADC Rate Line 2 DAC/ADC Rate Handset DAC/ADC Rate Line 1 DAC/ADC Level Mute Line 2 DAC/ADC Level Mute Handset DAC/ADC Level Mute GPIO Pin Config GPIO Polarity/Type GPIO Pin Sticky GPIO Pin Wake Up GPIO Pin Status Misc. Modem AFE Stat/Ctrl AC '97 Reserved Vendor Reserved Vendor ID1 Vendor ID2 MMBAR Exposed Registers (D30:F3) Name NOTES: 1. Registers in italics are for functions not supported by the ICH7 2. Software should not try to access reserved registers 3. The ICH7 supports a modem codec connected to ACZ_SDIN[2:0], as long as the Codec ID is 00 or 01. However, the ICH7 does not support more than one modem codec. The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the same global registers in the audio and modem I/O space. Therefore a read/write to these registers in either audio or modem I/O space affects the same physical register. Software could access these registers as bytes, word, DWord quantities, but reads must not cross DWord boundaries. These registers exist in I/O space and reside in the AC '97 controller. The two channels, Modem in and Modem out, each have their own set of Bus Mastering registers. The following register descriptions apply to both channels. The naming prefix convention used is as follows: MI = Modem in channel MO = Modem out channel Intel (R) ICH7 Family Datasheet 655 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) Table 17-3. Modem Registers Offset 00h-03h 04h 05h 06h-07h 08h-09h 0Ah 0Bh Mnemonic MI_BDBAR MI_CIV MI_LVI MI_SR MI_PICB MI_PIV MI_CR Name Modem In Buffer Descriptor List Base Address Modem In Current Index Value Modem In Last Valid Index Modem In Status Modem In Position In Current Buffer Modem In Prefetch Index Value Modem In Control Modem Out Buffer Descriptor List Base Address Modem Out Current Index Value Modem Out Last Valid Modem Out Status Modem In Position In Current Buffer Modem Out Prefetched Index Modem Out Control Default 00000000h 00h 00h 0001h 0000h 00h 00h Access R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W RO R/W R/WC, RO RO RO R/W, R/W (special) R/W, R/W (special) RO, R/W, R/WC R/W (special) 10h-13h 14h 15h 16h-17h 18h-19h 1Ah 1Bh MO_BDBAR MO_CIV MO_LVI MO_SR MI_PICB MO_PIV MO_CR 00000000h 00h 00h 0001h 0000h 00h 00h 3Ch-3Fh GLOB_CNT Global Control 00000000h 40h-43h 44h GLOB_STA CAS Global Status Codec Access Semaphore 00300000h 00h NOTE: 1. MI = Modem in channel; MO = Modem out channel Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers except the registers shared with the AC '97 audio controller (GCR, GSR, CASR). All resume well registers will not be reset by the D3HOT to D0 transition. Core well registers and bits not reset by the D3HOT to D0 transition: * offset 3Ch-3Fh - bits [6:0] Global Control (GLOB_CNT) * offset 40h-43h - bits [29,15,11:10] Global Status (GLOB_STA) * offset 44h - Codec Access Semaphore Register (CAS) Resume well registers and bits will not be reset by the D3HOT to D0 transition: * offset 40h-43h - bits [17:16] Global Status (GLOB_STA) 656 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.1 x_BDBAR--Buffer Descriptor List Base Address Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 00h (MIBDBAR), MBAR + 10h (MOBDBAR) 00000000h No Attribute: Size: Power Well: R/W 32bits Core Software can read the register at offset 00h by performing a single, 32-bit read from address offset 00h. Reads across DWord boundaries are not supported. Bit 31:3 2:0 Description Buffer Descriptor List Base Address [31:3] -- R/W. These bits represent address bits 31:3. The entries should be aligned on 8-byte boundaries. Hardwired to 0. 17.2.2 x_CIV--Current Index Value Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 04h (MICIV), MBAR + 14h (MOCIV), 00h No Attribute: Size: Power Well: RO 8bits Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 8-bit read to offset 04h. Reads across DWord boundaries are not supported. Bit 7:5 4:0 Hardwired to 0. Current Index Value [4:0] -- RO. These bits represent which buffer descriptor within the list of 16 descriptors is being processed currently. As each descriptor is processed, this value is incremented. Description 17.2.3 x_LVI--Last Valid Index Register (Modem--D30:F3) I/O Address: Default Value: MBAR + 05h (MILVI), MBAR + 15h (MOLVI) 00h Attribute: Power Well: R/W Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 8-bit read to offset 05h. Reads across DWord boundaries are not supported. Bit 7:5 4:0 Hardwired to 0 Last Valid Index [4:0] -- R/W. These bits indicate the last valid descriptor in the list. This value is updated by the software as it prepares new buffers and adds to the list. Description Intel (R) ICH7 Family Datasheet 657 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.4 x_SR--Status Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 06h (MISR), MBAR + 16h (MOSR) 0001h No Attribute: Size: Power Well: R/WC, RO 16 bits Core Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. Software can also read this register individually by doing a single, 16-bit read to offset 06h. Reads across DWord boundaries are not supported. Bit 15:5 Reserved FIFO Error (FIFOE) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = FIFO error occurs. 4 Modem in: FIFO error indicates a FIFO overrun. The FIFO pointers don't increment, the incoming data is not written into the FIFO, thereby being lost. Modem out: FIFO error indicates a FIFO underrun. The sample transmitted in this case should be the last valid sample. The Intel(R) ICH7 will set the FIFOE bit if the under-run or overrun occurs when there are more valid buffers to process. Buffer Completion Interrupt Status (BCIS) -- R/WC. 3 0 = Software clears this bit by writing a 1 to it. 1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion (IOC) bit is set in the command byte of the buffer descriptor. Remains active until software clears bit. Last Valid Buffer Completion Interrupt (LVBCI) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when last valid buffer has been processed. It remains active until cleared by software. This bit indicates the occurrence of the event signified by the last valid buffer being processed. Thus, this is an event status bit that can be cleared by software once this event has been recognized. This event will cause an interrupt if the enable bit in the Control Register is set. The interrupt is cleared when the software clears this bit. In the case of transmits (PCM out, Modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). While in the case of Receives, this bit is set after the data for the last buffer has been written to memory. Current Equals Last Valid (CELV) -- RO. 0 = Hardware clears when controller exists state (i.e., until a new value is written to the LVI register). 1 = Current Index is equal to the value in the Last Valid Index Register, AND the buffer pointed to by the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is very similar to bit 2, except, this bit reflects the state rather than the event. This bit reflects the state of the controller, and remains set until the controller exits this state. DMA Controller Halted (DCH) -- RO. 0 0 = Running. 1 = Halted. This could happen because of the Start/Stop bit being cleared and the DMA engines are idle, or it could happen once the controller has processed the last valid buffer. Description 2 1 658 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.5 x_PICB--Position in Current Buffer Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 08h (MIPICB), MBAR + 18h (MOPICB), 0000h No Attribute: Size: Power Well: RO 16 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 16-bit read to offset 08h. Reads across DWord boundaries are not supported. Bit 15:0 Description Position In Current Buffer[15:0] -- RO. These bits represent the number of samples left to be processed in the current buffer. 17.2.6 x_PIV--Prefetch Index Value Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 0Ah (MIPIV), MBAR + 1Ah (MOPIV) 00h No Attribute: Size: Power Well: RO 8 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 8-bit read to offset 0Ah. Reads across DWord boundaries are not supported. Bit 7:5 4:0 Hardwired to 0 Prefetched Index Value [4:0] -- RO. These bits represent which buffer descriptor in the list has been prefetched. Description Intel (R) ICH7 Family Datasheet 659 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.7 x_CR--Control Register (Modem--D30:F3) I/O Address: Default Value: Lockable: MBAR + 0Bh (MICR), MBAR + 1Bh (MOCR) 00h No Attribute: Size: Power Well: R/W, R/W (special) 8 bits Core Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from the address offset 08h. Software can also read this register individually by doing a single, 8-bit read to offset 0Bh. Reads across DWord boundaries are not supported. Bit 7:5 Reserved Interrupt on Completion Enable (IOCE) -- R/W. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. 0 = Disable 1 = Enable FIFO Error Interrupt Enable (FEIE) -- R/W. This bit controls whether the occurrence of a FIFO error will cause an interrupt or not. 0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur. 1 = Enable. Interrupt will occur Last Valid Buffer Interrupt Enable (LVBIE) -- R/W. This bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur. 1 = Enable Reset Registers (RR) -- R/W (special). 1 0 = Removes reset condition. 1 = Contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). Software needs to set this bit. It must be set only when the Run/ Pause bit is cleared. Setting it when the Run bit is set will cause undefined consequences. This bit is self-clearing (software needs not clear it). Run/Pause Bus Master (RPBM) -- R/W. 0 0 = Pause bus master operation. This results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = Run. Bus master operation starts. Description 4 3 2 660 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.8 GLOB_CNT--Global Control Register (Modem--D30:F3) I/O Address: Default Value: Lockable: Bit 31:5 Reserved. ACZ_SDIN2 Interrupt Enable (S2RE) -- R/W. 6 0 = Disable. 1 = Enable an interrupt to occur when the codec on the ACZ_SDIN2 causes a resume event on the AC-link. ACZ_SDIN1 Resume Interrupt Enable (S1RE) -- R/W. 5 0 = Disable. 1 = Enable an interrupt to occur when the codec on the ACZ_SDIN1 causes a resume event on the AC-link. ACZ_SDIN0 Resume Interrupt Enable (S0RE) -- R/W. 4 0 = Disable. 1 = Enable an interrupt to occur when the codec on ACZ_SDIN0 causes a resume event on the AC-link. AC-LINK Shut Off (LSO) -- R/W. 3 0 = Normal operation. 1 = Controller disables all outputs which will be pulled low by internal pull down resistors. AC '97 Warm Reset -- R/W (special). 0 = Normal operation. 1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken a suspended codec without clearing its internal registers. If software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit is self-clearing (it remains set until the reset completes and bit_clk is seen on the AC-link, after which it clears itself). AC '97 Cold Reset# -- R/W. 0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC `97 circuitry. All data in the controller and the codec will be lost. Software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. The value of this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset is not generated automatically upon resuming. NOTE: This bit is in the Core well. GPI Interrupt Enable (GIE) -- R/W. This bit controls whether the change in status of any GPI causes an interrupt. 0 0 = Bit 0 of the Global Status Register is set, but no interrupt is generated. 1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register. NOTE: This bit is cleared by the AC `97 Modem function D3HOT to D0 reset. MBAR + 3Ch 00000000h No Attribute: Size: Power Well: Description R/W, R/W (special) 32 bits Core 2 1 Note: Reads across DWord boundaries are not supported. Intel (R) ICH7 Family Datasheet 661 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) 17.2.9 GLOB_STA--Global Status Register (Modem--D30:F3) I/O Address: Default Value: Lockable: Bit 31:30 Reserved. ACZ_SDIN2 Resume Interrupt (S2RI) occurred on ACZ_SDIN2. 29 MBAR + 40h 00300000h No Attribute: Size: Power Well: Description RO, R/W, R/WC 32 bits Core -- R/WC. This bit indicates a resume event 0 = Software clears this bit by writing a 1 to it. 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN2 Codec Ready (S2CR) -- RO. This bit reflects the state of the codec ready bit on ACZ_SDIN2. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. Bit Clock Stopped (BCS) 28 -- RO. This bit indicates that the bit clock is not running. 27 0 = Transition is found on BIT_CLK. 1 = Intel(R) ICH7 detects that there has been no transition on BIT_CLK for four consecutive PCI clocks. S/PDIF* Interrupt (SPINT) -- RO. -- RO. -- RO. 26 0 = When the specific status bit is cleared, this bit will be cleared. 1 = S/PDIF out channel interrupt status bits have been set. PCM In 2 Interrupt (P2INT) 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM In 2 channel status bits have been set. Microphone 2 In Interrupt (M2INT) 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the Mic in channel interrupts status bits has been set. Sample Capabilities 16-bit audio. 25 24 -- RO. This field indicates the capability to support greater than 23:22 00 = Reserved 01 = 16 and 20-bit Audio supported (ICH7 value) 10 = Reserved 11 = Reserved 21:20 19:18 Multichannel Capabilities channels on PCM Out. Reserved. -- RO. This field indicates the capability to support 4 and 6 17 MD3 -- R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state. NOTE: This bit is not affected by D3HOT to D0 Reset. AD3 -- R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains context across power states (except G3). The bit has no hardware function. It is used by software in conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state. NOTE: This bit is not affected by D3HOT to D0 Reset. 16 662 Intel (R) ICH7 Family Datasheet AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) Bit Description Read Completion Status (RCS) -- R/WC. This bit indicates the status of codec read completions. Software clears this bit by writing a 1 to it. 15 0 = A codec read completes normally. 1 = A codec read results in a time-out. NOTE: This bit is not affected by D3HOT to D0 Reset. 14 13 12 Bit 3 of Slot 12 -- RO. Display bit 3 of the most recent slot 12. Bit 2 of Slot 12 -- RO. Display bit 2 of the most recent slot 12. Bit 1 of Slot 12 -- RO. Display bit 1 of the most recent slot 12. ACZ_SDIN1 Resume Interrupt (S1RI) -- R/WC. This bit indicates that a resume event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it. 11 0 = Resume event did Not occur. 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN0 Resume Interrupt (S0RI) -- R/WC. This bit indicates that a resume event occurred on ACZ_SDIN0. Software clears this bit by writing a 1 to it. 10 0 = Resume event did Not occur. 1 = Resume event occurred. NOTE: This bit is not affected by D3HOT to D0 Reset. ACZ_SDIN1 Codec Ready (S1CR) -- RO. This bit reflects the state of the codec ready bit in ACZ_SDIN1. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. ACZ_SDIN0 Codec Ready (S0CR) -- RO. This bit reflects the state of the codec ready bit in ACZ_SDIN 0. Bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. Once the codec is "ready", it must not go "not ready" spontaneously. 0 = Not Ready. 1 = Ready. Microphone In Interrupt (MINT) -- RO. 9 8 7 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the Mic in channel interrupts status bits has been set. PCM Out Interrupt (POINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM out channel interrupts status bits has been set. PCM In Interrupt (PIINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the PCM in channel interrupts status bits has been set. Reserved 6 5 4:3 Intel (R) ICH7 Family Datasheet 663 AC '97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only) Bit 2 Description Modem Out Interrupt (MOINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the modem out channel interrupts status bits has been set. Modem In Interrupt (MIINT) -- RO. 0 = When the specific status bit is cleared, this bit will be cleared. 1 = One of the modem in channel interrupts status bits has been set. GPI Status Change Interrupt (GSCI) -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This indicates that one of the GPI's changed state, and that the new values are available in slot 12. NOTE: This bit is not affected by AC `97 Audio Modem function D3HOT to D0 Reset. 1 0 Note: On reads from a codec, the controller will give the codec a maximum of four frames to respond, after which if no response is received, it will return a dummy read completion to the processor (with all F's on the data) and also set the Read Completion Status bit in the Global Status Register. Reads across DWord boundaries are not supported. Note: 17.2.10 CAS--Codec Access Semaphore Register (Modem--D30:F3) I/O Address: Default Value: Lockable: Bit 7:1 Reserved Codec Access Semaphore (CAS) -- R/W (special). This bit is read by software to check whether a codec access is currently in progress. 0 0 = No access in progress. 1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform an I/O access. Once the access is completed, hardware automatically clears this bit. NABMBAR + 44h 00h No Attribute: Size: Power Well: Description R/W (special) 8 bits Core Note: Reads across DWord boundaries are not supported. 664 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18 PCI Express* Configuration Registers (Desktop and Mobile Only) PCI Express is not supported on ICH7-U Ultra Mobile. Note: 18.1 Note: / PCI Express* Configuration Registers (PCI Express--D28:F0/F1/F2/F3/F4/F5) Register address locations that are not shown in Table 18-1 should be treated as Reserved. Table 18-1. PCI Express* Configuration Registers Address Map (PCI Express--D28:F0/F1/F2/F3/F4/F5) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 18h-1Ah 1Ch-1Dh 1Eh-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 34h 3Ch-3Dh 3Eh-3Fh 40h-41h 42h-43h 44h-47h 48h-49h 4Ah-4Bh Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC CLS PLT HEADTYP BNUM IOBL SSTS MBL PMBL PMBU32 PMLU32 CAPP INTR BCTRL CLIST XCAP DCAP DCTL DSTS Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Cache Line Size Primary Latency Timer Header Type Bus Number I/O Base and Limit Secondary Status Memory Base and Limit Prefetchable Memory Base and Limit Prefetchable Memory Base Upper 32 Bits Prefetchable Memory Limit Upper 32 Bits Capabilities List Pointer Interrupt Information Bridge Control Capabilities List PCI Express* Capabilities Device Capabilities Device Control Device Status Function 0-5 Default 8086h See register description. 0000h 0010h See register description. 00h 04h 06h 00h 00h 81h 000000h 0000h 0000h 00000000h 00010001h 00000000h 00000000h 40h See bit description 0000h 8010 0041 00000FE0h 0000h 0010h Type RO RO R/W, RO R/WC, RO RO RO RO RO R/W RO RO R/W R/W, RO R/WC R/W R/W, RO R/W R/W RO R/W, RO R/W RO R/WO, RO RO R/W, RO R/WC, RO Intel (R) ICH7 Family Datasheet 665 PCI Express* Configuration Registers (Desktop and Mobile Only) Table 18-1. PCI Express* Configuration Registers Address Map (PCI Express--D28:F0/F1/F2/F3/F4/F5) (Sheet 2 of 2) Offset 4Ch-4Fh 50h-51h 52h-53h 54h-57h 58h-59h 5Ah-5Bh 5Ch-5Dh 60h-63h 80h-81h 82h-83h 84h-87h 88h-89h 90h-91h 94h-97h A0h-A1h A2h-A3h A4-A7h D8-DBh DC-DFh E1h E2-E3h 100-103h 108h-10Bh 10Ch-10Dh 10Eh-10Fh 110h-113h 114-117h 11A-11Bh 144h-147h 148h-14Bh 14Ch-14Fh 150h-153h 154h-157h 158h-15Bh 170h-173h 180h-183h 184h-187h 190h-193h 198h-19Fh 318h Mnemonic LCAP LCTL LSTS SLCAP SLCTL SLSTS RCTL RSTS MID MC MA MD SVCAP SVID PMCAP PMC PMCS MPC SMSCS RPDCGEN IPWS VCH VCAP2 PVC PVS V0CAP V0CTL V0STS UES UEM UEV CES CEM AECC RES RCTCL ESD ULD ULBA PEETM Register Name Link Capabilities Link Control Link Status Slot Capabilities Register Slot Control Slot Status Root Control Root Status Message Signaled Interrupt Identifiers Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Message Data Subsystem Vendor Capability Subsystem Vendor Identification Power Management Capability PCI Power Management Capability PCI Power Management Control and Status Miscellaneous Port Configuration SMI/SCI Status Root Port Dynamic Clock Gating Enable (Mobile/Ultra Mobile Only) Intel(R) PRO/Wireless 3945ABG Status Virtual Channel Capability Header Virtual Channel Capability 2 Port Virtual Channel Control Port Virtual Channel Status Virtual Channel 0 Resource Capability Virtual Channel 0 Resource Control Virtual Channel 0 Resource Status Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Error Severity Correctable Error Status Correctable Error Mask Advanced Error Capabilities and Control Root Error Status Root Complex Topology Capability List Element Self Description Upstream Link Description Upstream Link Base Address PCI Express Extended Test Mode Register Function 0-5 Default See bit description 0000h See bit description 00000060h 0000h 0000h 0000h 00000000h 9005h 0000h 00000000h 0000h A00Dh 00000000h 0001h C802h 00000000h 00110000h 00000000h 00h 0000h 18010002h 00000001h 0000h 0000h 00000001h 800000FFh 0000h See bit description 00000000h 00060011h 00000000h 00000000h 00000000h 00000000h 00010005h See bit description 00000001h See bit description 00h Type R/W, RO, R/WO R/W, WO, RO RO R/WO, RO R/W, RO R/WC, RO R/W R/WC, RO RO R/W, RO R/W R/W RO R/WO RO RO R/W, RO R/W R/WC R/W RO RO RO R/W RO RO R/W, RO RO R/WC, RO R/WO, RO RO R/WC R/WO RO R/WC, RO RO RO RO RO RO 666 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.1 VID--Vendor Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 00h-01h Default Value: 8086h Bit 15:0 Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel 18.1.2 DID--Device Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 02h-03h Default Value: Port 1= Bit Port 2= Bit Port 3= Bit Port 4= Bit Port 5= Bit Port 6= Bit Bit 15:0 Description Description Description Description Description Description Attribute: Size: RO 16 bits Description Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 PCI Express controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. 18.1.3 PCICMD--PCI Command Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 04h-05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable -- R/W. This bit disables pin-based INTx# interrupts on enabled Hot-Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled. 1 = Internal INTx# messages will not be generated. NOTE: This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 8 7 Fast Back to Back Enable (FBE) -- Reserved per the PCI Express* Base Specification. SERR# Enable (SEE) -- R/W. 0 = Disable. 1 = Enables the root port to generate an SERR# message when PSTS.SSE is set. Wait Cycle Control (WCC) -- Reserved per the PCI Express Base Specification. Parity Error Response (PER) -- R/W. 6 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. Attribute: Size: Description R/W, RO 16 bits 10 Intel (R) ICH7 Family Datasheet 667 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit 5 4 3 Description VGA Palette Snoop (VPS) -- Reserved per the PCI Express* Base Specification. Postable Memory Write Enable (PMWE) -- Reserved per the PCI Express* Base Specification. Special Cycle Enable (SCE) -- Reserved per the PCI Express* Base Specification. Bus Master Enable (BME) -- R/W. 0 = Disable. All cycles from the device are master aborted 1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI Express* device. Memory Space Enable (MSE) -- R/W. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the PCI Express device. I/O Space Enable (IOSE) -- R/W. This bit controls access to the I/O space registers. 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the PCI Express device. 2 1 0 18.1.4 PCISTS--PCI Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 06h-07h Default Value: 0010h Bit Attribute: Size: Description R/WC, RO 16 bits Detected Parity Error (DPE) -- R/WC. 15 0 = No parity error detected. 1 = Root port received a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set. Signaled System Error (SSE) -- R/WC. 14 0 = No system error signaled. 1 = Root port signaled a system error to the internal SERR# logic. Received Master Abort (RMA) -- R/WC. 13 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Root port received a completion with unsupported request status from the backbone. Received Target Abort (RTA) -- R/WC. 12 0 = Root port has not received a completion with completer abort from the backbone. 1 = Root port received a completion with completer abort from the backbone. Signaled Target Abort (STA) -- R/WC. 11 0 = No target abort received. 1 = Root port forwarded a target abort received from the downstream device onto the backbone. DEVSEL# Timing Status (DEV_STS) -- Reserved per the PCI Express* Base Specification. 10:9 668 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description Master Data Parity Error Detected (DPED) -- R/WC. 0 = No data parity error received. 1 = Root port received a completion with a data parity error on the backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set. Fast Back to Back Capable (FB2BC) -- Reserved per the PCI Express* Base Specification. Reserved 66 MHz Capable -- Reserved per the PCI Express* Base Specification. Capabilities List -- RO. Hardwired to 1. Indicates the presence of a capabilities list. Interrupt Status -- RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 8 7 6 5 4 3 0 = Interrupt is deasserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10). 2:0 Reserved 18.1.5 RID--Revision Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Offset Address: 08h Default Value: See bit description Bit 7:0 Attribute: Size: Description RO 8 bits Revision ID -- RO. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. 18.1.6 PI--Programming Interface Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 09h Default Value: 00h Bit 7:0 Programming Interface -- RO. 00h = No specific register level programming interface defined. Attribute: Size: Description RO 8 bits 18.1.7 SCC--Sub Class Code Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Ah Default Value: 04h Bit 7:0 Sub Class Code (SCC) -- RO. 04h = PCI-to-PCI bridge. Attribute: Size: Description RO 8 bits Intel (R) ICH7 Family Datasheet 669 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.8 BCC--Base Class Code Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Bh Default Value: 06h Bit 7:0 Base Class Code (BCC) -- RO. 06h = Indicates the device is a bridge device. Attribute: Size: Description RO 8 bits 18.1.9 CLS--Cache Line Size Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Base Class Code (BCC) -- R/W. This is read/write but contains no functionality, per the PCI Express* Base Specification. 18.1.10 PLT--Primary Latency Timer Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Dh Default Value: 00h Bit 7:3 2:0 Attribute: Size: Description RO 8 bits Latency Count. Reserved per the PCI Express* Base Specification. Reserved 18.1.11 HEADTYP--Header Type Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 0Eh Default Value: 81h Bit Multi-Function Device -- RO. 7 6:0 0 = Single-function device. 1 = Multi-function device. Configuration Layout. Hardwired to 01h, which indicates a PCI-to-PCI bridge. Attribute: Size: Description RO 8 bits 670 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.12 BNUM--Bus Number Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 18-1Ah Default Value: 000000h Bit 23:16 15:8 7:0 Attribute: Size: Description R/W 24 bits Subordinate Bus Number (SBBN) -- R/W. This field indicates the highest PCI bus number below the bridge. Secondary Bus Number (SCBN) -- R/W. This field indicates the bus number the port. Primary Bus Number (PBN) -- R/W. This field indicates the bus number of the backbone. 18.1.13 IOBL--I/O Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 1Ch-1Dh Default Value: 0000h Bit 15:12 11:8 7:4 3:0 Attribute: Size: Description R/W, RO 16 bits I/O Limit Address (IOLA) -- R/W. This field contains the I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. I/O Limit Address Capability (IOLC) -- R/O. This field indicates that the bridge does not support 32-bit I/O addressing. I/O Base Address (IOBA) -- R/W. This field contains the I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. I/O Base Address Capability (IOBC) -- R/O. This field indicates that the bridge does not support 32-bit I/O addressing. Intel (R) ICH7 Family Datasheet 671 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.14 SSTS--Secondary Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 1Eh-1Fh Default Value: 0000h Bit 15 Attribute: Size: Description R/WC 16 bits Detected Parity Error (DPE) -- R/WC. 0 = No error. 1 = The port received a poisoned TLP. Received System Error (RSE) -- R/WC. 14 0 = No error. 1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device. Received Master Abort (RMA) -- R/WC. 13 0 = Unsupported Request not received. 1 = The port received a completion with "Unsupported Request" status from the device. Received Target Abort (RTA) -- R/WC. 12 0 = Completion Abort not received. 1 = The port received a completion with "Completion Abort" status from the device. Signaled Target Abort (STA) -- R/WC. 11 0 = Completion Abort not sent. 1 = The port generated a completion with "Completion Abort" status to the device. Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification. Data Parity Error Detected (DPD) -- R/WC. 8 0 = Conditions below did not occur. 1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of the following two conditions occurs: -- Port receives completion marked poisoned. -- Port poisons a write request to the secondary side. 10:9 7 6 5 4:0 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification. Reserved Secondary 66 MHz Capable (SC66). Reserved per PCI Express* Base Specification. Reserved 672 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.15 MBL--Memory Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 20h-23h Default Value: 00000000h Attribute: Size: R/W 32 bits Accesses that are within the ranges specified in this register will be sent to the attached device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5:04:bit 1) is set. Accesses from the attached device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/F2/F3/F4/F5:04:bit 2) is set. The comparison performed is: MB AD[31:20] ML. Bit 31:20 19:16 15:4 3:0 Description Memory Limit (ML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. Reserved Memory Base (MB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. Reserved 18.1.16 PMBL--Prefetchable Memory Base and Limit Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 24h-27h Default Value: 00010001h Attribute: Size: R/W, RO 32 bits Accesses that are within the ranges specified in this register will be sent to the device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5;04, bit 1) is set. Accesses from the device that are outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/ F2/F3/F4/F5;04, bit 2) is set. The comparison performed is: PMBU32:PMB AD[63:32]:AD[31:20] PMLU32:PML. Bit 31:20 19:16 15:4 3:0 Description Prefetchable Memory Limit (PML) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value of the range. 64-bit Indicator (I64L) -- RO. This field indicates support for 64-bit addressing Prefetchable Memory Base (PMB) -- R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range. 64-bit Indicator (I64B) -- RO. This field indicates support for 64-bit addressing Intel (R) ICH7 Family Datasheet 673 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.17 PMBU32--Prefetchable Memory Base Upper 32 Bits Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 28h-2Bh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Base Upper Portion (PMBU) -- R/W. This field contains the Upper 32-bits of the prefetchable address base. 18.1.18 PMLU32--Prefetchable Memory Limit Upper 32 Bits Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 2Ch-2Fh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Prefetchable Memory Limit Upper Portion (PMLU) -- R/W. This field contains the Upper 32-bits of the prefetchable address limit. 18.1.19 CAPP--Capabilities List Pointer Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 34h Default Value: 40h Bit 7:0 Attribute: Size: Description R0 8 bits Capabilities Pointer (PTR) -- RO. This field indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. 674 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.20 INTR--Interrupt Information Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 3Ch-3Dh Default Value: See bit description Bit Attribute: Size: Description R/W, RO 16 bits Interrupt Pin (IPIN) -- RO. This field indicates the interrupt pin driven by the root port. At reset, this register takes on the following values that reflect the reset state of the D28IP register in chipset configuration space: Port 1 15:8 2 3 4 5 6 Reset Value D28IP.P1IP D28IP.P2IP D28IP.P3IP D28IP.P4IP D28IP.P5IP D28IP.P6IP NOTE: The value that is programmed into D28IP is always reflected in this register. 7:0 Interrupt Line (ILINE) -- R/W. Default = 00h. This field is a software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Intel (R) ICH7 Family Datasheet 675 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.21 BCTRL--Bridge Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 3Eh-3Fh Default Value: 0000h Bit 15:12 11 10 9 8 7 6 5 Reserved Discard Timer SERR# Enable (DTSE). Reserved per PCI Express* Base Specification, Revision 1.0a Discard Timer Status (DTS). Reserved per PCI Express* Base Specification, Revision 1.0a. Secondary Discard Timer (SDT). Reserved per PCI Express* Base Specification, Revision 1.0a. Primary Discard Timer (PDT). Reserved per PCI Express* Base Specification, Revision 1.0a. Fast Back to Back Enable (FBE). Reserved per PCI Express* Base Specification, Revision 1.0a. Secondary Bus Reset (SBR) -- R/W. This bit triggers a hot reset on the PCI Express* port. Master Abort Mode (MAM): Reserved per Express specification. VGA 16-Bit Decode (V16) -- R/W. 4 0 = VGA range is enabled. 1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled, and only the base I/O ranges can be decoded VGA Enable (VE)-- R/W. 3 0 = The ranges below will not be claimed off the backbone by the root port. 1 = The following ranges will be claimed off the backbone by the root port: -- Memory ranges A0000h-BFFFFh -- I/O ranges 3B0h - 3BBh and 3C0h - 3DFh, and all aliases of bits 15:10 in any combination of 1s Attribute: Size: Description R/W 16 bits ISA Enable (IE) -- R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. 2 0 = The root port will not block any forwarding from the backbone as described below. 1 = The root port will block any forwarding from the backbone to the device of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). SERR# Enable (SE) -- R/W. 1 0 = The messages described below are not forwarded to the backbone. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to the backbone. Parity Error Response Enable (PERE) -- R/W. 0 0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8). 1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8). 676 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.22 CLIST--Capabilities List Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 40-41h Default Value: 8010h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) -- RO. Value of 80h indicates the location of the next pointer. Capability ID (CID) -- RO. This field indicates this is a PCI Express* capability. 18.1.23 XCAP--PCI Express* Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 42h-43h Default Value: 0041h Bit 15:14 13:9 Reserved Interrupt Message Number (IMN) -- RO. The Intel(R) ICH7 does not have multiple MSI interrupt numbers. Slot Implemented (SI) -- R/WO. This field indicates whether the root port is connected to a slot. Slot support is platform specific. BIOS programs this field, and it is maintained until a platform reset. Device / Port Type (DT) -- RO. This field indicates this is a PCI Express* root port. Capability Version (CV) -- RO. This field indicates PCI Express 1.0. Attribute: Size: Description R/WO, RO 16 bits 8 7:4 3:0 Intel (R) ICH7 Family Datasheet 677 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.24 DCAP--Device Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 44h-47h Default Value: 00000FE0h Bit 31:28 27:26 25:18 17:15 14 13 12 11:9 8:6 5 4:3 2:0 Reserved Captured Slot Power Limit Scale (CSPS) -- RO. Not supported. Captured Slot Power Limit Value (CSPV) -- RO. Not supported. Reserved Power Indicator Present (PIP) -- RO. This bit indicates no power indicator is present on the root port. Attention Indicator Present (AIP) -- RO. This bit indicates no attention indicator is present on the root port. Attention Button Present (ABP) -- RO. This bit indicates no attention button is present on the root port. Endpoint L1 Acceptable Latency (E1AL) -- RO. This field indicates more than 4 s. This field essentially has no meaning for root ports since root ports are not endpoints. Endpoint L0 Acceptable Latency (E0AL) -- RO. This field indicates more than 64 s. This field essentially has no meaning for root ports since root ports are not endpoints. Extended Tag Field Supported (ETFS) -- RO. This bit indicates that 8-bit tag fields are supported. Phantom Functions Supported (PFS) -- RO. This field indicates No phantom functions supported. Max Payload Size Supported (MPS) -- RO. This field indicates the maximum payload size supported is 128B. Attribute: Size: Description RO 32 bits 678 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.25 DCTL--Device Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 48h-49h Default Value: 0000h Bit 15 14:12 11 10 9 8 7:5 4 3 Reserved Max Read Request Size (MRRS) -- RO. Hardwired to 0. Enable No Snoop (ENS) -- RO. Not supported. The root port will not issue non-snoop requests. Aux Power PM Enable (APME) -- R/W. The OS will set this bit to 1 if the device connected has detected aux power. It has no effect on the root port otherwise. Phantom Functions Enable (PFE) -- RO. Not supported. Extended Tag Field Enable (ETFE) -- RO. Not supported. Max Payload Size (MPS) -- R/W. The root port only supports 128-B payloads, regardless of the programming of this field. Enable Relaxed Ordering (ERO) -- RO. Not supported. Unsupported Request Reporting Enable (URE) -- R/W. 0 = Disable. The root port will ignore unsupported request errors. 1 = Enable. The root port will generate errors when detecting an unsupported request. Fatal Error Reporting Enable (FEE) -- R/W. 2 0 = Disable. The root port will ignore fatal errors. 1 = Enable. The root port will generate errors when detecting a fatal error. Non-Fatal Error Reporting Enable (NFE) -- R/W. 1 0 = Disable. The root port will ignore non-fatal errors. 1 = Enable. The root port will generate errors when detecting a non-fatal error. Correctable Error Reporting Enable (CEE) -- R/W. 0 0 = Disable. The root port will ignore correctable errors. 1 = Enable. The root port will generate errors when detecting a correctable error. Attribute: Size: Description R/W, RO 16 bits Intel (R) ICH7 Family Datasheet 679 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.26 DSTS--Device Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 4Ah-4Bh Default Value: 0010h Bit 15:6 5 4 3 Reserved Transactions Pending (TDP) -- RO. This bit has no meaning for the root port since only one transaction may be pending to the Intel(R) ICH7, so a read of this bit cannot occur until it has already returned to 0. AUX Power Detected (APD) -- RO. The root port contains AUX power for wakeup. Unsupported Request Detected (URD) -- R/WC. This bit indicates an unsupported request was detected. Fatal Error Detected (FED) -- R/WC. This bit indicates a fatal error was detected. 2 0 = Fatal has not occurred. 1 = A fatal error occurred from a data link protocol error, link training error, buffer overflow, or malformed TLP. Non-Fatal Error Detected (NFED) -- R/WC. This bit indicates a non-fatal error was detected. 1 0 = Non-fatal has not occurred. 1 = A non-fatal error occurred from a poisoned TLP, unexpected completions, unsupported requests, completer abort, or completer timeout. Correctable Error Detected (CED) -- R/WC. This bit indicates a correctable error was detected. 0 0 = Correctable has not occurred. 1 = The port received an internal correctable error from receiver errors / framing errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout. Attribute: Size: Description R/WC, RO 16 bits 680 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.27 LCAP--Link Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 4Ch-4Fh Default Value: See bit description Bit Attribute: Size: Description R/W, RO 32 bits Port Number (PN) -- RO. This field indicates the port number for the root port. This value is different for each implemented port: Function D28:F0 31:24 D28:F1 D28:F2 D28:F3 D28:F4 D28:F5 23:21 20 19:18 17:15 Reserved Link Active Reporting Capable (LARC) -- RO. Hardwired to 1 to indicate that this port supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. Reserved L1 Exit Latency (EL1) -- RO. Set to 010b to indicate an exit latency of 2 s to 4 s. L0s Exit Latency (EL0) -- RO. This field indicates as exit latency based upon common-clock configuration. LCLT.CCC 14:12 0 1 Value of EL0 (these bits) MPC.UCEL (D28:F0/F1/F2/ F3:D8h:bits20:18) MPC.CCEL (D28:F0/F1/F2/ F3:D8h:bits17:15) Port # 1 2 3 4 5 6 Value of PN Field 01h 02h 03h 04h 05h 06h NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6 Active State Link PM Support (APMS) -- R/WO. This field indicates what level of active state link power management is supported on the root port. Bits 11:10 00b 01b 10b 11b Definition Neither L0s nor L1 are supported L0s Entry Supported L1 Entry Supported Both L0s and L1 Entry Supported Intel (R) ICH7 Family Datasheet 681 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description Maximum Link Width (MLW) -- RO. For the root ports, several values can be taken, based upon the value of the chipset configuration register field RPC.PC1 (Chipset Configuration Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Configuration Registers:Offset 0224h:bits1:0) for Ports 5 and 6. Value of MLW Field Port # RPC.PC1=00b 01h 01h 01h 01h RPC.PC2=00b 01h 01h RPC.PC1=11b 04h 01h 01h 01h RPC.PC2=11b N/A N/A 1 2 3 4 Port # 5 6 9:4 3:0 Maximum Link Speed (MLS) -- RO. Set to 1h to indicate the link speed is 2.5 Gb/s. 18.1.28 LCTL--Link Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 50h-51h Default Value: 0000h Bit 15:8 Reserved Extended Synch (ES) -- R/W. 7 0 = Extended synch disabled. 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. Common Clock Configuration (CCC) -- R/W. 6 0 = The Intel(R) ICH7 and device are not using a common reference clock. 1 = The ICH7 and device are operating with a distributed common reference clock. Retrain Link (RL) -- WO. 5 0 = This bit always returns 0 when read. 1 = The root port will train its downstream link. NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status of training. Link Disable (LD) -- R/W. 4 0 = Link enabled. 1 = The root port will disable the link. Read Completion Boundary Control (RCBC) -- RO. This bit indicates that the read completion boundary is 64 bytes. Reserved Attribute: Size: Description R/W, WO, RO 16 bits 3 2 682 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description Active State Link PM Control (APMC) -- R/W. This bit indicates whether the root port should enter L0s or L1 or both. Bits Definition Disabled L0s Entry is Enabled L1 Entry is Enabled L0s and L1 Entry Enabled 1:0 00b 01b 10b 11b 18.1.29 LSTS--Link Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 52h-53h Default Value: See bit description Bit 15:14 Reserved Data Link Layer Active (DLLA) -- RO. D 13 0 = Data Link Control and Management State Machine is not in the DL_Active state. (Default) 1 = Data Link Control and Management State Machine is in the DL_Active state. Slot Clock Configuration (SCC) -- RO. Set to 1b to indicate that the Intel(R) ICH7 uses the same reference clock as on the platform and does not generate its own clock. Link Training (LT) -- RO. 11 10 0 = Link training completed. (Default) 1 = Link training is occurring. Link Training Error (LTE) -- RO. Not supported. Set value is 0b. Negotiated Link Width (NLW) -- RO. This field indicates the negotiated width of the given PCI Express* link. The contents of this NLW field is undefined if the link has not successfully trained. Port # 1 9:4 2 3 4 5 6 Possible Values 000001b, 000010b, 000100b 000001b 000001b 000001b 000001b, 000010b 000001b Attribute: Size: Description RO 16 bits 12 NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported), 000100 = x4 linkwidth 3:0 Link Speed (LS) -- RO. This field indicates the negotiated Link speed of the given PCI Express* link. 01h = Link is 2.5 Gb/s. Intel (R) ICH7 Family Datasheet 683 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.30 SLCAP--Slot Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 54h-57h Default Value: 00000060h Bit 31:19 18:17 Attribute: Size: Description R/WO, RO 32 bits Physical Slot Number (PSN) -- R/WO. This is a value that is unique to the slot number. BIOS sets this field and it remains set until a platform reset. Reserved Slot Power Limit Scale (SLS) -- R/WO. This field specifies the scale used for the slot power limit value. BIOS sets this field and it remains set until a platform reset. Range of Values: 16:15 00b = 1.0 x 01b = 0.1 x 10b = 0.01 x 11b = 0.001 x Slot Power Limit Value (SLV) -- R/WO. This field specifies the upper limit (in conjunction with SLS value), on the upper limit on power supplied by the slot. The two values together indicate the amount of power in watts allowed for the slot. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. BIOS sets this field and it remains set until a platform reset. Hot Plug Capable (HPC) -- RO. 1b = Hot-Plug is supported. Hot Plug Surprise (HPS) -- RO. 1b = Device may be removed from the slot without prior notification. Power Indicator Present (PIP) -- RO. 0b = Power indicator LED is not present for this slot. Attention Indicator Present (AIP) -- RO. 0b = Attention indicator LED is not present for this slot. MRL Sensor Present (MSP) -- RO. 0b = MRL sensor is not present. Power Controller Present (PCP) -- RO. 0b = Power controller is not implemented for this slot. Attention Button Present (ABP) -- RO. 0b =Attention button is not implemented for this slot. 14:7 6 5 4 3 2 1 0 684 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.31 SLCTL--Slot Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 58h-59h Default Value: 0000h Bit 15:13 Reserved Link Active Changed Enable (LACE) -- RW. 12 0 = Disable. 1 = Enables generation of a hot plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed. Reserved Power Controller Control (PCC) -- RO.This bit has no meaning for module based Hot-Plug. Power Indicator Control (PIC) -- R/W. When read, the current state of the power indicator is returned. When written, the appropriate POWER_INDICATOR_* messages are sent. Defined encodings are: 9:8 Bits 00b 01b 10b 11b Definition Reserved On Blink Off Attribute: Size: Description R/W, RO 16 bits 11 10 Attention Indicator Control (AIC) -- R/W. When read, the current state of the attention indicator is returned. When written, the appropriate ATTENTION_INDICATOR_* messages are sent. Defined encodings are: 7:6 Bits 00b 01b 10b 11b Definition Reserved On Blink Off Hot Plug Interrupt Enable (HPE) -- R/W. 5 0 = Disable. Hot plug interrupts based on Hot-Plug events is disabled. 1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events. Command Completed Interrupt Enable (CCE) -- R/W. 4 0 = Disable. Hot plug interrupts based on command completions is disabled. 1 = Enables the generation of a Hot-Plug interrupt when a command is completed by the Hot-Plug controller. Presence Detect Changed Enable (PDE) -- R/W. 3 0 = Disable. Hot plug interrupts based on presence detect logic changes is disabled. 1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence detect logic changes state. Intel (R) ICH7 Family Datasheet 685 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit 2 1 Description MRL Sensor Changed Enable (MSE) -- R/W. MSE not supported. Power Fault Detected Enable (PFE) -- R/W. PFE not supported. Attention Button Pressed Enable (ABE) -- R/W. When set, enables the generation of a Hot-Plug interrupt when the attention button is pressed. 0 0 = Disable. Hot plug interrupts based on the attention button being pressed is disabled. 1 = Enables the generation of a Hot-Plug interrupt when the attention button is pressed. 18.1.32 SLSTS--Slot Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 5Ah-5Bh Default Value: 0000h Bit 15:9 Reserved Link Active State Changed (LASC) -- R/WC. 0 = No Change. 1 = Value reported in Data Link Layer Link Active field of the Link Status register (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed. In response to a Data Link Layer State Changed event, software must read Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device. Reserved Presence Detect State (PDS) -- RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5:42h:bit 8) is set indicating that this root port spawns a slot), then this bit: 6 0 = Slot is empty. 1 = Slot has a device connected. Otherwise; if XCAP.SI is cleared, this bit is always set to 1. 5 MRL Sensor State (MS) -- Reserved as the MRL sensor is not implemented. Command Completed (CC) -- R/WC. 4 0 = Issued command not completed. 1 = The Hot-Plug controller completed an issued command. This is set when the last message of a command is sent and indicates that software can write a new command to the slot controller. Presence Detect Changed (PDC) -- R/WC. 3 2 1 0 0 = No change in the PDS bit. 1 = The PDS bit changed states. MRL Sensor Changed (MSC) -- Reserved as the MRL sensor is not implemented. Power Fault Detected (PFD) -- Reserved as a power controller is not implemented. Attention Button Pressed (ABP) -- R/WC. 0 = The attention button has not been pressed. 1 = The attention button is pressed. Attribute: Size: Description R/WC, RO 16 bits 8 7 686 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.33 RCTL--Root Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 5Ch-5Dh Default Value: 0000h Bit 15:4 Reserved PME Interrupt Enable (PIE) -- R/W. 3 0 = Interrupt generation disabled. 1 = Interrupt generation enabled when PCISTS.Interrupt Status (D28:F0/F1/F2/F3/F4/ F5:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.IS already set). System Error on Fatal Error Enable (SFE) -- R/W. 2 0 = Disable. An SERR# will not be generated. 1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/ F5:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. System Error on Non-Fatal Error Enable (SNE) -- R/W. 1 0 = Disable. An SERR# will not be generated. 1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/ F5:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. System Error on Correctable Error Enable (SCE) -- R/W. 0 0 = Disable. An SERR# will not be generated. 1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/ F5:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. Attribute: Size: Description R/W 16 bits 18.1.34 RSTS--Root Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 60h-63h Default Value: 00000000h Bit 31:18 Reserved PME Pending (PP) -- RO. 17 0 = Indicates no more PMEs are pending. 1 = Indicates another PME is pending (this is implicit because of the definition of this bit being 1). Hardware will set the PME Status bit again and update the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending. PME Status (PS) -- R/WC. 16 0 = PME was not asserted. 1 = PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending until this bit is cleared. PME Requestor ID (RID) -- RO. This field indicates the PCI requestor ID of the last PME requestor. The value in this field is valid only when PS is set. Attribute: Size: Description R/WC, RO 32 bits 15:0 Intel (R) ICH7 Family Datasheet 687 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.35 MID--Message Signaled Interrupt Identifiers Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 80h-81h Default Value: 9005h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Pointer (NEXT) -- RO. This field indicates the location of the next pointer in the list. Capability ID (CID) -- RO. Capabilities ID indicates MSI. 18.1.36 MC--Message Signaled Interrupt Message Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 82-83h Default Value: 0000h Bit 15:8 7 6:4 3:1 Reserved 64 Bit Address Capable (C64) -- RO. Capable of generating a 32-bit message only. Multiple Message Enable (MME) -- R/W. These bits are R/W for software compatibility, but only one message is ever sent by the root port. Multiple Message Capable (MMC) -- RO. Only one message is required. MSI Enable (MSIE) -- R/W. 0 = Disabled. 1 = Enabled and traditional interrupt pins are not used to generate interrupts. NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5:04h:bit 2) must be set for an MSI to be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even pin based) are generated. Attribute: Size: Description R/W, RO 16 bits 0 18.1.37 MA--Message Signaled Interrupt Message Address Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 84h-87h Default Value: 00000000h Bit 31:2 1:0 Attribute: Size: Description R/W 32 bits Address (ADDR) -- R/W. This field contains the lower 32 bits of the system specified message address; always DWord aligned. Reserved 688 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.38 MD--Message Signaled Interrupt Message Data Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 88h-89h Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16 bits Data (DATA) -- R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI memory write transaction. 18.1.39 SVCAP--Subsystem Vendor Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 90h-91h Default Value: A00Dh Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) -- RO. This field indicates the location of the next pointer in the list. Capability Identifier (CID) -- RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. 18.1.40 SVID--Subsystem Vendor Identification Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 94h-97h Default Value: 00000000h Bit 31:16 Attribute: Size: Description R/WO 32 bits Subsystem Identifier (SID) -- R/WO. This field indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). Subsystem Vendor Identifier (SVID) -- R/WO. This field indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 18.1.41 PMCAP--Power Management Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: A0h-A1h Default Value: 0001h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (NEXT) -- RO. This field indicates that this is the last item in the list. Capability Identifier (CID) -- RO. Value of 01h indicates this is a PCI power management capability. Intel (R) ICH7 Family Datasheet 689 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.42 PMC--PCI Power Management Capabilities Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: A2h-A3h Default Value: C802h Bit Attribute: Size: Description RO 16 bits 15:11 PME_Support (PMES) -- RO. This field indicates PME# is supported for states D0, D3HOT and D3COLD. The root port does not generate PME#, but reporting that it does is necessary for some legacy operating systems to enable PME# in devices connected behind this root port. D2_Support (D2S) -- RO. The D2 state is not supported. D1_Support (D1S) -- RO The D1 state is not supported. Aux_Current (AC) -- RO. This field reports 375 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) -- RO. This bit indicates that no device-specific initialization is required. Reserved PME Clock (PMEC) -- RO. This bit indicates that PCI clock is not required to generate PME#. Version (VS) -- RO. This field indicates support for Revision 1.1 of the PCI Power Management Specification. 10 9 8:6 5 4 3 2:0 18.1.43 PMCS--PCI Power Management Control and Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: A4h-A7h Default Value: 00000000h Bit 31:24 23 22 21:16 15 14:9 Reserved Bus Power / Clock Control Enable (BPCE). Reserved per PCI Express* Base Specification, Revision 1.0a. B2/B3 Support (B23S). Reserved per PCI Express* Base Specification, Revision 1.0a. Reserved PME Status (PMES) -- RO. This bit indicates a PME was received on the downstream link. Reserved PME Enable (PMEE) -- R/W. Indicates PME is enabled. The root port takes no action on this bit, but it must be R/W for some legacy operating systems to enable PME# on devices connected to this root port. 8 0 = Disable. 1 = Enable. NOTE: This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which is not asserted during a warm reset. 7:2 Reserved Attribute: Size: Description R/W, RO 32 bits 690 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description Power State (PS) -- R/W. This field is used both to determine the current power state of the root port and to set a new power state. The values are: 00 = D0 state 11 = D3HOT state 1:0 NOTE: When in the D3HOT state, the controller's configuration space is available, but the I/O and memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are not required to be blocked as software will disable interrupts prior to placing the port into D3HOT. If software attempts to write a `10' or `01' to these bits, the write will be ignored. 18.1.44 MPC--Miscellaneous Port Configuration Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: D8h-DBh Default Value: 00110000h Bit Attribute: Size: Description R/W 32 bits Power Management SCI Enable (PMCE) -- R/W. 31 0 = Disable. SCI generation based on a power management event is disabled. 1 = Enables the root port to generate SCI whenever a power management event is detected. Hot Plug SCI Enable (HPCE) -- R/W. 30 0 = Disable. SCI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected. Link Hold Off (LHO)-- R/W. 29 0 = Not in Link Hold Off. 1 = The port will not take any TLP. This is used during loopback mode to fill up the downstream queue. Address Translator Enable (ATE) -- R/W. This bit is used to enable address translation via the AT bits in this register during loopback mode. 0 = Disable. 1 = Enable. Reserved. Invalid Receive Bus Number Check Enable (IRBNCE) -- R/W. 0 = Disable. 1 = Enable. Receive transaction layer will signal an error if the bus number of a Memory request does not fall within the range between SCBN and SBBN. If this check is enabled and the request is a memory write, it is treated as an Unsupported Request. If this check is enabled and the request is a non-posted memory read request, the request is considered a Malformed TLP and a fatal error. NOTE: Messages, IO, Configuration, and Completions are not checked for valid bus number. Invalid Receive Range Check Enable (IRRCE) -- R/W. 0 = Disable. 1 = Enable. Receive transaction layer will treat the TLP as an Unsupported Request error if the address range of a memory request does not outside the range between prefetchable and non-prefetchable base and limit. NOTE: Messages, I/O, Configuration, and Completions are not checked for valid address ranges. 28 27 26 25 Intel (R) ICH7 Family Datasheet 691 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description BME Receive Check Enable (BMERCE) -- R/W. 0 = Disable. 1 = Enable. Receive transaction layer will treat the TLP as an Unsupported Request error if a memory read or write request is received and the Bus Master Enable bit is not set. NOTE: Messages, IO, Configuration, and Completions are not checked for BME. 24 23:21 20:18 Reserved Unique Clock Exit Latency (UCEL) -- R/W. This value represents the L0s Exit Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/ F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 s, but may be overridden by BIOS. Common Clock Exit Latency (CCEL) -- R/W. This value represents the L0s Exit Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/ F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden by BIOS. Reserved Port I/OxApic Enable (PAE) -- R/W. 0 = Hole is disabled. 1 = A range is opened through the bridge for the following memory addresses: Port # Address FEC1_0000h - FEC1_7FFFh FEC1_8000h - FEC1_FFFFh FEC2_0000h - FEC2_7FFFh FEC2_8000h - FEC2_FFFFh FEC3_0000h - FEC3_7FFFh FEC3_8000h - FEC3_FFFFh 1 2 3 4 5 6 17:15 14:8 7 6:2 1 Reserved Hot Plug SMI Enable (HPME) -- R/W. 0 = Disable. SMI generation based on a Hot-Plug event is disabled. 1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected. Power Management SMI Enable (PMME) -- R/W. 0 = Disable. SMI generation based on a power management event is disabled. 1 = Enables the root port to generate SMI whenever a power management event is detected. 0 692 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.45 SMSCS--SMI/SCI Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: DCh-DFh Default Value: 00000000h Bit Attribute: Size: Description R/WC 32 bits Power Management SCI Status (PMCS) -- R/WC. 31 0 = Interrupt Not needed. 1 = PME control logic needs to generate an interrupt, and this interrupt has been routed to generate an SCI. Hot Plug SCI Status (HPCS) -- R/WC. 30 0 = Interrupt Not needed. 1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been routed to generate an SCI. Reserved Hot Plug Link Active State Changed SMI Status (HPLAS) -- R/WC. 4 0 = No change 1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5:5A, bit 8) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Command Completed SMI Status (HPCCM) -- R/WC. 3 0 = No change 1 = SLSTS.CC (D28:F0/F1/F2/F3/F4/F5:5A, bit 4) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Attention Button SMI Status (HPABM) -- R/WC. 2 0 = No change 1 = SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5:5A, bit 0) transitioned from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Hot Plug Presence Detect SMI Status (HPPDM) -- R/WC. 1 0 = No change 1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5:5A, bit 3) transitions from 0-to-1, and MPC.HPME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be generated. Power Management SMI Status (PMMS) -- R/WC. 0 0 = No change 1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5:60, bit 16) transitions from 0-to-1, and MPC.PMME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. 29:5 Intel (R) ICH7 Family Datasheet 693 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.46 RPDCGEN - Root Port Dynamic Clock Gating Enable (PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only) Address Offset: E1h Default Value: 00h Bits 7:4 Reserved. RO Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) -- RW. 3 0 = Disables dynamic clock gating of the shared resource link clock domain. 1 = Enables dynamic clock gating on the root port shared resouce link clock domain. Only the value from Port 1 is used for ports 1-4. Only the value from Port 5 is used for ports 5-6. Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) -- RW. 2 0 = Disables dynamic clock gating of the shared resource backbone clock domain. 1 = Enables dynamic clock gating on the root port shared resouce backbone clock domain. Only the value from Port 1 is used for ports 1-4. Only the value from Port 5 is used for ports 5-6. Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) -- RW. 1 0 = Disables dynamic clock gating of the root port link clock domain. 1 = Enables dynamic clock gating on the root port link clock domain. Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) -- RW. 0 0 = Disables dynamic clock gating of the root port backbone clock domain. 1 = Enables dynamic clock gating on the root port backbone clock domain. Attribute: Size: Description R/W 8-bits 18.1.47 IPWS--Intel(R) PRO/Wireless 3945ABG Status (PCI Express--D28:F0/F1/F2/F3/F4/F5) (Mobile Only) Address Offset: E2h-E3h Default Value: 0007h Bit 15 14:0 Attribute: Size: Description RO 16 bits Intel PRO/Wireless 3945ABG Status (IPWSTAT) -- RO. This bit is set if the link has trained to L0 in Intel PRO/Wireless 3945ABG mode. Reserved 694 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.48 VCH--Virtual Channel Capability Header Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 100h-103h Default Value: 18010002h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability Offset (NCO) -- RO. This field indicates the next item in the list. Capability Version (CV) -- RO. This field indicates that this is version 1 of the capability structure by the PCI SIG. Capability ID (CID) -- RO. This field indicates that this is the Virtual Channel capability item. 18.1.49 VCAP2--Virtual Channel Capability 2 Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 108h-10Bh Default Value: 00000001h Bit 31:24 23:0 Attribute: Size: Description RO 32 bits VC Arbitration Table Offset (ATO) -- RO. This field indicates that no table is present for VC arbitration since it is fixed. Reserved. 18.1.50 PVC--Port Virtual Channel Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 10Ch-10Dh Default Value: 0000h Bit 15:4 3:1 Reserved. VC Arbitration Select (AS) -- R/W. This field indicates which VC should be programmed in the VC arbitration table. The root port takes no action on the setting of this field since there is no arbitration table. Load VC Arbitration Table (LAT) -- R/W. This bit indicates that the table programmed should be loaded into the VC arbitration table. This bit always returns 0 when read. Attribute: Size: Description R/W 16 bits 0 Intel (R) ICH7 Family Datasheet 695 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.51 PVS -- Port Virtual Channel Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 10Eh-10Fh Default Value: 0000h Bit 15:1 0 Reserved. VC Arbitration Table Status (VAS) -- RO. This bit indicates the coherency status of the VC Arbitration table when it is being updated. This field is always 0 in the root port since there is no VC arbitration table. Attribute: Size: Description RO 16 bits 18.1.52 V0CAP -- Virtual Channel 0 Resource Capability Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 110h-113h Default Value: 00000001h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset (AT) -- RO. This VC implements no port arbitration table since the arbitration is fixed. Reserved. Maximum Time Slots (MTS) -- RO. This VC implements fixed arbitration; therefore, this field is not used. Reject Snoop Transactions (RTS) -- RO. This VC must be able to take snoopable transactions. Advanced Packet Switching (APS) -- RO. This VC is capable of all transactions, not just advanced packet switching transactions. Reserved. Port Arbitration Capability (PAC) -- RO. This field indicates that this VC uses fixed port arbitration. 696 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.53 V0CTL -- Virtual Channel 0 Resource Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 114h-117h Default Value: 800000FFh Bit 31 30:27 26:24 23:20 19:17 Attribute: Size: Description R/W, RO 32 bits Virtual Channel Enable (EN) -- RO. Always set to 1. Virtual Channel 0 cannot be disabled. Reserved. Virtual Channel Identifier (VCID) -- RO. This field indicates the ID to use for this virtual channel. Reserved. Port Arbitration Select (PAS) -- R/W. This field indicates which port table is being programmed. The root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. Load Port Arbitration Table (LAT) -- RO. The root port does not implement an arbitration table for this virtual channel. Reserved. Transaction Class / Virtual Channel Map (TVM) -- R/W. This field indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. Bit 7 6 Transaction Class Transaction Class 7 Transaction Class 6 Transaction Class 5 Transaction Class 4 Transaction Class 3 Transaction Class 2 Transaction Class 1 Transaction Class 0 16 15:8 7:1 5 4 3 2 1 0 0 Reserved. Transaction class 0 must always be mapped to VC0. 18.1.54 V0STS -- Virtual Channel 0 Resource Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 11Ah-11Bh Default Value: 0000h Bit 15:2 1 Reserved. VC Negotiation Pending (NP) -- RO. 0 = Negotiation is not pending. 1 = Virtual Channel is still being negotiated with ingress ports. Port Arbitration Tables Status (ATS). There is no port arbitration table for this VC; this bit is reserved as 0. Attribute: Size: Description RO 16 bits 0 Intel (R) ICH7 Family Datasheet 697 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.55 UES -- Uncorrectable Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 144h-147h Attribute: R/WC, RO Default Value: 00000000000x0xxx0x0x0000000x0000bSize:32 bits This register maintains its state through a platform reset. It loses its state upon suspend. Bit 31:21 20 19 18 Reserved Unsupported Request Error Status (URE) -- R/WC. 0 = Unsupported request was Not received. 1 = Unsupported request was received. ECRC Error Status (EE) -- RO. ECRC is not supported. Malformed TLP Status (MT) -- R/WC. 0 = Malformed TLP was Not received. 1 = Malformed TLP was received. Receiver Overflow Status (RO) -- R/WC. 17 0 = Receiver overflow did Not occur. 1 = Receiver overflow occurred. Unexpected Completion Status (UC) -- R/WC. 16 0 = Unexpected completion was Not received. 1 = Unexpected completion was received. Completion Abort Status (CA) -- R/WC. 15 0 = Completer abort was Not received. 1 = Completer abort was received. Completion Timeout Status (CT) -- R/WC. 14 0 = Completion did Not time out. 1 = Completion timed out. Flow Control Protocol Error Status (FCPE) -- RO. Flow Control Protocol Errors not supported. Poisoned TLP Status (PT) -- R/WC. 12 11:5 4 3:1 0 0 = Poisoned TLP was Not received. 1 = Poisoned TLP was received. Reserved Data Link Protocol Error Status (DLPE) -- R/WC. 0 = Data link protocol error did Not occur. 1 = Data link protocol error occurred. Reserved Training Error Status (TE) -- RO. Training Errors not supported. Description 13 698 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.56 UEM -- Uncorrectable Error Mask (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 148h-14Bh Default Value: 00000000h Attribute: Size: R/WO, RO 32 bits When set, the corresponding error in the UES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:21 Reserved Unsupported Request Error Mask (URE) -- R/WO. 20 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. ECRC Error Mask (EE) -- RO. ECRC is not supported. Malformed TLP Mask (MT) -- R/WO. 18 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Receiver Overflow Mask (RO) -- R/WO. 17 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Unexpected Completion Mask (UC) -- R/WO. 16 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Completion Abort Mask (CA) -- R/WO. 15 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Completion Timeout Mask (CT) -- R/WO. 14 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Flow Control Protocol Error Mask (FCPE) -- RO. Flow Control Protocol Errors not supported. Poisoned TLP Mask (PT) -- R/WO. 12 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Reserved Description 19 13 11:5 Intel (R) ICH7 Family Datasheet 699 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Description Data Link Protocol Error Mask (DLPE) -- R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is masked. Reserved Training Error Mask (TE) -- RO. Training Errors not supported 4 3:1 0 18.1.57 UEV -- Uncorrectable Error Severity (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 14Ch-14Fh Default Value: 00060011h Bit 31:21 20 19 18 Reserved Unsupported Request Error Severity (URE) -- RO. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. ECRC Error Severity (EE) -- RO. ECRC is not supported. Malformed TLP Severity (MT) -- RO. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Receiver Overflow Severity (RO) -- RO. 17 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Unexpected Completion Severity (UC) -- RO. 16 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Completion Abort Severity (CA) -- RO. 15 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Completion Timeout Severity (CT) -- RO. 14 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Flow Control Protocol Error Severity (FCPE) -- RO. Flow Control Protocol Errors not supported. Poisoned TLP Severity (PT) -- RO. 12 11:5 4 3:1 0 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Reserved Data Link Protocol Error Severity (DLPE) -- RO. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Reserved Training Error Severity (TE) -- RO. TE is not supported. Attribute: Size: Description RO 32 bits 13 700 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.58 CES -- Correctable Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 150h-153h Default Value: 00000000h Bit 31:13 12 11:9 8 Reserved Replay Timer Timeout Status (RTT) -- R/WC. 0 = Replay timer did Not time out. 1 = Replay timer timed out. Reserved Replay Number Rollover Status (RNR) -- R/WC. 0 = Replay number did Not roll over. 1 = Replay number rolled over. Bad DLLP Status (BD) -- R/WC. 7 0 = Bad DLLP was Not received. 1 = Bad DLLP was received. Bad TLP Status (BT) -- R/WC. 6 5:1 0 0 = Bad TLP was Not received. 1 = Bad TLP was received. Reserved Receiver Error Status (RE) -- R/WC. 0 = Receiver error did Not occur. 1 = Receiver error occurred. Attribute: Size: Description R/WC 32 bits 18.1.59 CEM -- Correctable Error Mask Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 154h-157h Default Value: 00000000h Attribute: Size: R/WO 32 bits When set, the corresponding error in the CES register is masked, and the logged error will cause no action. When cleared, the corresponding error is enabled. Bit 31:13 12 11:9 8 Reserved Replay Timer Timeout Mask (RTT) -- R/WO. 0 = No mask 1 = Mask for replay timer timeout. Reserved Replay Number Rollover Mask (RNR) -- R/WO. 0 = No mask 1 = Mask for replay number rollover. Bad DLLP Mask (BD) -- R/WO. 7 0 = No mask 1 = Mask for bad DLLP reception. Description Intel (R) ICH7 Family Datasheet 701 PCI Express* Configuration Registers (Desktop and Mobile Only) Bit Bad TLP Mask (BT) -- R/WO. 6 5:1 0 0 = No mask 1 = Mask for bad TLP reception. Reserved Description Receiver Error Mask (RE) -- R/WO. 0 = No mask 1 = Mask for receiver errors. 18.1.60 AECC -- Advanced Error Capabilities and Control Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 158h-15Bh Default Value: 00000000h Bit 31:9 8 7 6 5 4:0 Reserved ECRC Check Enable (ECE) -- RO. ECRC is not supported. ECRC Check Capable (ECC) -- RO. ECRC is not supported. ECRC Generation Enable (EGE) -- RO. ECRC is not supported. ECRC Generation Capable (EGC) -- RO. ECRC is not supported. First Error Pointer (FEP) -- RO. Attribute: Size: Description RO 32 bits 18.1.61 RES -- Root Error Status Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 170h-173h Default Value: 00000000h Bit 31:27 26:4 3 Attribute: Size: Description R/WC, RO 32 bits Advanced Error Interrupt Message Number (AEMN) -- RO. There is only one error interrupt allocated. Reserved Multiple ERR_FATAL/NONFATAL Received (MENR) -- RO. For Intel(R) ICH7, only one error will be captured. ERR_FATAL/NONFATAL Received (ENR) -- R/WC. 0 = No error message received. 1 = Either a fatal or a non-fatal error message is received. Multiple ERR_COR Received (MCR) -- RO. For ICH7, only one error will be captured. ERR_COR Received (CR) -- R/WC. 0 = No error message received. 1 = A correctable error message is received. 2 1 0 702 Intel (R) ICH7 Family Datasheet PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.62 RCTCL -- Root Complex Topology Capability List Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 180-183h Default Value: 00010005h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability (NEXT) -- RO. This field indicates the next item in the list, in this case, end of list. Capability Version (CV) -- RO. This field indicates the version of the capability structure. Capability ID (CID) -- RO. This field indicates this is a root complex topology capability. 18.1.63 ESD -- Element Self Description Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 184h-187h Default Value: See Description Bit Attribute: Size: Description RO 32 bits Port Number (PN) -- RO. This field indicates the ingress port number for the root port. There is a different value per port: Port # 1 31:24 2 3 4 5 6 Value 01h 02h 03h 04h 05h 06h 23:16 Component ID (CID) -- RO. This field returns the value of the ESD.CID field (Chipset Configuration Space: Offset 0104h:bits 23:16) of the chip configuration section, that is programmed by platform BIOS, since the root port is in the same component as the RCRB. Number of Link Entries (NLE) -- RO. (Default value is 01h). This field indicates one link entry (corresponding to the RCRB). Reserved. Element Type (ET) -- RO. (Default value is 0h). This field indicates that the element type is a root port. 15:8 7:4 3:0 Intel (R) ICH7 Family Datasheet 703 PCI Express* Configuration Registers (Desktop and Mobile Only) 18.1.64 ULD -- Upstream Link Description Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 190h-193h Default Value: 00000001h Bit 31:24 Attribute: Size: Description RO 32 bits Target Port Number (PN) -- RO. This field indicates the port number of the RCRB. Target Component ID (TCID) -- RO. This field returns the value of the ESD.CID field (Chipset Configuration Space: Offset 0104h:bits 23:16) of the chip configuration section, that is programmed by platform BIOS, since the root port is in the same component as the RCRB. Reserved. Link Type (LT) -- RO. This bit indicates that the link points to the Intel(R) ICH7 RCRB. Link Valid (LV) -- RO. This bit indicates that this link entry is valid. 23:16 15:2 1 0 18.1.65 ULBA -- Upstream Link Base Address Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 198h-19Fh Default Value: See Description Bit 63:32 31:0 Attribute: Size: Description RO 64 bits Base Address Upper (BAU) -- RO. The RCRB of the Intel(R) ICH7 is in 32-bit space. Base Address Lower (BAL) -- RO. This field matches the RCBA register (D31:F0:Offset F0h) value in the LPC bridge. 18.1.66 PEETM -- PCI Express Extended Test Mode Register (PCI Express--D28:F0/F1/F2/F3/F4/F5) Address Offset: 318h Default Value: See Description Bit 7:3 Reserved Scrambler Bypass Mode (BAU) -- R/W. 0 = Normal operation. Scrambler and descrambler are used. 1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive direction. NOTE: This functionality intended for debug/testing only. NOTE: If bypassing scrambler with Intel(R) ICH7 root port 1 in x4 configuration, each ICH7 root port must have this bit set. 1:0 Reserved Attribute: Size: Description RO 8 bits 2 704 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19 Intel(R) High Definition Audio Controller Registers (D27:F0) The Intel(R) High Definition Audio controller resides in PCI Device 27, Function 0 on bus 0. This function contains a set of DMA engines that are used to move samples of digitally encoded data between system memory and external codecs. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and D-word quantities. The software must always make register accesses on natural boundaries (i.e. D-word accesses must be on D-word boundaries; word accesses on word boundaries, etc.) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the Intel High Definition Audio memory-mapped space, the results are undefined. Users interested in providing feedback on the Intel High Definition Audio specification or planning to implement the Intel High Definition Audio specification into a future product will need to execute the Intel(R) High Definition Audio Specification Developer's Agreement. For more information, contact nextgenaudio@intel.com. Note: 19.1 Note: Intel(R) High Definition Audio PCI Configuration Space (Intel(R) High Definition Audio-- D27:F0) Address locations that are not shown should be treated as Reserved. Table 19-1. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 1 of 2) Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 10h-13h 14h-17h 2Ch-2Dh 2Eh-2Fh 34h Mnemonic VID DID PCICMD PCISTS RID PI SCC BCC CLS LT HEADTYP HDBARL HDBARU SVID SID CAPPTR Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer Header Type Intel(R) High Definition Audio Lower Base Address (Memory) Intel(R) High Definition Audio Upper Base Address (Memory) Subsystem Vendor Identification Subsystem Identification Capability List Pointer Default 8086h See register description. 0000h 0010h See register description. 00h 03h 04h 00h 00h 00h 00000004h 00000000h 0000h 0000h 50h Access RO RO R/W, RO R/WC, RO RO RO RO RO R/W RO RO R/W, RO R/W R/WO R/WO RO Intel (R) ICH7 Family Datasheet 705 Intel(R) High Definition Audio Controller Registers (D27:F0) Table 19-1. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 2 of 2) Offset 3Ch 3Dh 40h 44h 4Ch 4Dh 50h-51h 52h-53h 54h-57h 60h-61h 62h-63h 64h-67h 68h-6Bh 6Ch-6Dh 70h-71h 72h-73h 74h-77h 78h-79h 7Ah-7Bh 100h-103h 104h-107h 108h-10Bh 10Ch-10D 10Eh-10Fh 110h-103h 114h-117h 11Ah-11Bh 11Ch-11Fh 120h-123h 126h-127h 130h-133h 134h-137h 140h-143h 148h-14Bh 14Ch-14Fh Mnemonic INTLN INTPN HDCTL TCSEL DCKCTL DCKSTS PID PC PCS MID MMC MMLA MMUA MMD PXID PXC DEVCAP DEVC DEVS VCCAP PVCCAP1 PVCCAP2 PVCCTL PVCSTS VC0CAP VC0CTL VC0STS VCiCAP VCiCTL VCiSTS RCCAP ESD L1DESC L1ADDL L1ADDU Register Name Interrupt Line Interrupt Pin Intel High Definition Audio Control Traffic Class Select Docking Control (Mobile Only) Docking Status (Mobile Only) PCI Power Management Capability ID Power Management Capabilities Power Management Control and Status MSI Capability ID MSI Message Control MSI Message Lower Address SMI Message Upper Address MSI Message Data PCI Express* Capability Identifiers (Desktop and Mobile Only) PCI Express Capabilities (Desktop and Mobile Only) Device Capabilities Device Control Device Status Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control Port VC Status VC0 Resource Capability VC0 Resource Control VC0 Resource Status VCi Resource Capability VCi Resource Control VCi Resource Status Root Complex Link Declaration Enhanced Capability Header Element Self Description Link 1 Description Link 1 Lower Address Link 1 Upper Address Default 00h See Register Description 00h 00h 00h 80h 6001h C842 00000000h 7005h 0080h 00000000h 00000000h 0000h 0010h 0091h 00000000h 0800h 0010h 13010002h 00000001h 00000000h 0000h 0000h 00000000h 800000FFh 0000h 00000000h 00000000h 0000h 00010005h 0F000100h 00000001h See Register Description 00000000h Access R/W RO R/W, RO R/W R/W, RO R/WO, RO RO RO R/W, RO, R/WC RO R/W, RO R/W, RO R/W R/W RO RO RO, R/WO R/W, RO RO RO RO RO RO RO RO R/W, RO RO RO R/W, RO RO RO RO RO RO RO 706 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.1 VID--Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Offset: Default Value: Bit 15:0 00h-01h 8086h Attribute: Size: Description RO 16 bits Vendor ID -- RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h 19.1.2 DID--Device Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Offset Address: 02h-03h Default Value: See bit description Bit 15:0 Attribute: Size: Description RO 16 bits Device ID -- RO. This is a 16-bit value assigned to the Intel(R) ICH7 Intel High Definition Audio controller. Refer to the Intel(R) I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID Register. Intel (R) ICH7 Family Datasheet 707 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.3 PCICMD--PCI Command Register (Intel(R) High Definition Audio Controller--D27:F0) Offset Address: 04h-05h Default Value: 0000h Bit 15:11 Reserved Interrupt Disable (ID) -- R/W. 0= The INTx# signals may be asserted. 10 1= The Intel(R) High Definition Audio controller's INTx# signal will be de-asserted NOTE: This bit does not affect the generation of MSIs. 9 8 7 6 5 4 3 Fast Back to Back Enable (FBE) -- RO. Not implemented. Hardwired to 0. SERR# Enable (SERR_EN) -- R/W. SERR# is not generated by the Intel(R) ICH7 Intel High Definition Audio Controller. Wait Cycle Control (WCC) -- RO. Not implemented. Hardwired to 0. Parity Error Response (PER) -- RO. Not implemented. Hardwired to 0. VGA Palette Snoop (VPS). Not implemented. Hardwired to 0. Memory Write and Invalidate Enable (MWIE) -- RO. Not implemented. Hardwired to 0. Special Cycle Enable (SCE). Not implemented. Hardwired to 0. Bus Master Enable (BME) -- R/W. Controls standard PCI Express* bus mastering capabilities for Memory and I/O, reads and writes. Note that this bit also controls MSI generation since MSIs are essentially memory writes. 0 = Disable 1 = Enable Memory Space Enable (MSE) -- R/W. Enables memory space addresses to the Intel High Definition Audio controller. 0 = Disable 1 = Enable I/O Space Enable (IOSE)--RO. Hardwired to 0 since the Intel High Definition Audio controller does not implement I/O space. Attribute: Size: Description R/W, RO 16 bits 2 1 0 708 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.4 PCISTS--PCI Status Register (Intel(R) High Definition Audio Controller--D27:F0) Offset Address: 06h-07h Default Value: 0010h Bit 15 14 Attribute: Size: Description RO, R/WC 16 bits Detected Parity Error (DPE) -- RO. Not implemented. Hardwired to 0. SERR# Status (SERRS) -- RO. Not implemented. Hardwired to 0. Received Master Abort (RMA) -- R/WC. Software clears this bit by writing a 1 to it. 0 = No master abort received. 1 = The Intel(R) High Definition Audio controller sets this bit when, as a bus master, it receives a master abort. When set, the Intel High Definition Audio controller clears the run bit for the channel that received the abort. Received Target Abort (RTA) -- RO. Not implemented. Hardwired to 0. Signaled Target Abort (STA) -- RO. Not implemented. Hardwired to 0. DEVSEL# Timing Status (DEV_STS) -- RO. Does not apply. Hardwired to 0. Data Parity Error Detected (DPED) -- RO. Not implemented. Hardwired to 0. Fast Back to Back Capable (FB2BC) -- RO. Does not apply. Hardwired to 0. Reserved. 66 MHz Capable (66MHZ_CAP) -- RO. Does not apply. Hardwired to 0. Capabilities List (CAP_LIST) -- RO. Hardwired to 1. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status (IS) -- RO. 0 = This bit is 0 after the interrupt is cleared. 1 = This bit is 1 when the INTx# is asserted. Note that this bit is not set by an MSI. Reserved. 13 12 11 10:9 8 7 6 5 4 3 2:0 19.1.5 RID--Revision Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Offset: Default Value: Bit 7:0 08h See bit description Attribute: Size: Description RO 8 Bits Revision ID -- RO. Refer to the Intel I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID Register. (R) Intel (R) ICH7 Family Datasheet 709 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.6 PI--Programming Interface Register (Intel(R) High Definition Audio Controller--D27:F0) Offset: Default Value: Bit 7:0 Programming Interface -- RO. 09h 00h Attribute: Size: Description RO 8 bits 19.1.7 SCC--Sub Class Code Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 0Ah Default Value: 03h Bit 7:0 Sub Class Code (SCC) -- RO. 03h = Audio Device Attribute: Size: Description RO 8 bits 19.1.8 BCC--Base Class Code Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 0Bh Default Value: 04h Bit 7:0 Base Class Code (BCC) -- RO. 04h = Multimedia device Attribute: Size: Description RO 8 bits 19.1.9 CLS--Cache Line Size Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Cache Line Size -- R/W. Implemented as R/W register, but has no functional impact to the Intel(R) ICH7 19.1.10 LT--Latency Timer Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 0Dh Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Latency Timer -- RO. Hardwired to 00 710 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.11 HEADTYP--Header Type Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 0Eh Default Value: 00h Bit 7:0 Header Type -- RO. Hardwired to 00. Attribute: Size: Description RO 8 bits 19.1.12 HDBARL--Intel(R) High Definition Audio Lower Base Address Register (Intel(R) High Definition Audio--D27:F0) Address Offset: 10h-13h Default Value: 00000004h Bit 31:14 13:4 3 2:1 0 Attribute: Size: Description R/W, RO 32 bits Lower Base Address (LBA) -- R/W. This field contains the base address for the Intel(R) High Definition Audio controller's memory mapped configuration registers; 16 KB are requested by hardwiring bits 13:4 to 0s. RO. Hardwired to 0s Prefetchable (PREF) -- RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable. Address Range (ADDRNG) -- RO. Hardwired to 10b, indicating that this BAR can be located anywhere in 64-bit address space. Space Type (SPTYP) -- RO. Hardwired to 0. Indicates this BAR is located in memory space. 19.1.13 HDBARU--Intel(R) High Definition Audio Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 14h-17h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Upper Base Address (UBA) -- R/W. This field provides the upper 32 bits of the Base address for the Intel(R) High Definition Audio controller's memory mapped configuration registers. Intel (R) ICH7 Family Datasheet 711 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.14 SVID--Subsystem Vendor Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 2Ch-2Dh Default Value: 0000h Attribute: Size: R/WO 16 bits The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh), enable the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem Vendor ID -- R/WO. Description 19.1.15 SID--Subsystem Identification Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 2Eh-2Fh Default Value: 0000h Attribute: Size: R/WO 16 bits The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). This register is implemented as write-once register. Once a value is written to it, the value can be read back. Any subsequent writes will have no effect. T This register is not affected by the D3HOT to D0 transition. Bit 15:0 Subsystem ID -- R/WO. Description 712 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.16 CAPPTR--Capabilities Pointer Register (Audio--D30:F2) Address Offset: 34h Default Value: 50h Attribute: Size: RO 8 bits This register indicates the offset for the capability pointer. Bit 7:0 Description Capabilities Pointer (CAP_PTR) -- RO. This field indicates that the first capability pointer offset is offset 50h (Power Management Capability) 19.1.17 INTLN--Interrupt Line Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 3Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Interrupt Line (INT_LN) -- R/W. This data is not used by the Intel(R) ICH7. It is used to communicate to software the interrupt line that the interrupt pin is connected to. 19.1.18 INTPN--Interrupt Pin Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 3Dh Default Value: See Description Bit 7:4 3:0 Reserved. Interrupt Pin -- RO. This reflects the value of D27IP.ZIP (Chipset Config Registers:Offset 3110h: bits 3:0). Attribute: Size: Description RO 8 bits Intel (R) ICH7 Family Datasheet 713 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.19 HDCTL--Intel(R) High Definition Audio Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 40h Default Value: 00h Bit 7:4 Reserved. BITCLK Detect Clear (CLKDETCLR) -- R/W. 3 0 = lock detect circuit is operational and maybe enabled. 1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains clear when this bit is set to 1. NOTE: This bit is not affected by the D3HOT to D0 transition. BITCLK Detect Enable (CLKDETEN) -- R/W. 0 = Latches the current state of bit 1 (CLKDET#) in this register 2 1 = Enables the clock detection circuit NOTE: This bit is not affected by the D3HOT to D0 transition. BITCLK Detected Inverted (CLKDET#) -- RO. This bit is modified by hardware. It is set to 0 when the Intel(R) ICH7 detects that the BITCLK is toggling, indicating the presence of an AC'97 codec on the link. 1 NOTES: 1. Bit 2 (CLKDETEN) and bit 3 (CLKDETCLR) in this register control the operation of this bit and must be manipulated correctly in order to get a valid CLKDET# indicator. 2. This bit is not affected by the D3HOT to D0 transition. Intel(R) High Definition Audio/AC `97 Signal Mode -- R/W. This bit selects the shared Intel High Definition Audio/AC `97 signals. 0 = AC '97 mode is selected (Default) 1 = Intel High Definition Audio mode is selected 0 NOTES: 1. This bit has no effect on the visibility of the Intel High Definition Audio and AC '97 function configuration space. 2. This bit is in the resume well and only clear on a power-on reset. Software must not makes assumptions about the reset state of this bit and must set it appropriately. 3. For the ICH7-U Ultra Mobile, this bit must be programmed to 1. Attribute: Size: Description R/W, RO 8 bits 714 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.20 TCSEL--Traffic Class Select Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 44h Default Value: 00h Attribute: Size: R/W 8 bits This register assigned the value to be placed in the TC field. CORB and RIRB data will always be assigned TC0. Bit 7:3 Reserved. Intel(R) HIgh Definition Audio Traffic Class Assignment (TCSEL)-- R/W. This register assigns the value to be placed in the Traffic Class field for input data, output data, and buffer descriptor transactions. 000 = TC0 001 = TC1 010 = TC2 2:0 011 = TC3 100 = TC4 101 = TC5 110 = TC6 111 = TC7 NOTE: These bits are not reset on D3HOT to D0 transition; however, they are reset by PLTRST#. Description 19.1.21 DCKCTL--Docking Control Register (Mobile Only) (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 4Ch Default Value: 00h Bit 7:1 Reserved. Dock Attach (DA) -- R/W / RO: 0 = Software writes a 0 to this bit to initiate the undocking sequence on the AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the undocking sequence is complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0. 1 = Software writes a 1 to this bit to initiate the docking sequence on the AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the docking sequence is complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1. NOTE: Software must check the state of the Dock Mated (GSTS.DM) bit prior to writing to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1. If these rules are not followed, the results are undefined. NOTE: This bit is Read Only when the DCKSTS.DS bit = 0. Attribute: Size: Description R/W, RO 8 bits 0 Intel (R) ICH7 Family Datasheet 715 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.22 DCKSTS--Docking Status Register (Intel(R) High Definition Audio Controller--D27:F0) (Mobile Only) Address Offset: 4Dh Default Value: 80h Bit 7 6:1 0) BIOS is required to clear this bit. Reserved. Reserved. Attribute: Size: Description R/WO, RO 8 bits 19.1.23 PID--PCI Power Management Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 50h-51h Default Value: 6001h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (Next) -- RO. Hardwired to 60h. Points to the next capability structure (MSI) Cap ID (CAP) -- RO. Hardwired to 01h. Indicates that this pointer is a PCI power management capability. 19.1.24 PC--Power Management Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 52h-53h Default Value: C842h Bit 15:11 10 9 8:6 5 4 3 2:0 Attribute: Size: Description RO 16 bits PME Support -- RO. Hardwired to 11001b. Indicates PME# can be generated from D3 and D0 states. D2 Support -- RO. Hardwired to 0. Indicates that D2 state is not supported. D1 Support --RO. Hardwired to 0. Indicates that D1 state is not supported. Aux Current -- RO. Hardwired to 001b. Reports 55 mA maximum suspend well current required when in the D3COLD state. Device Specific Initialization (DSI) -- RO. Hardwired to 0. Indicates that no device specific initialization is required. Reserved PME Clock (PMEC) -- RO. Does not apply. Hardwired to 0. Version -- RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power Management Specification. 716 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.25 PCS--Power Management Control and Status Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 54h-57h Default Value: 00000000h Bit 31:24 23 22 21:16 Attribute: Size: Description RO, R/W, R/WC 32 bits Data -- RO. Does not apply. Hardwired to 0. Bus Power/Clock Control Enable -- RO. Does not apply. Hardwired to 0. B2/B3 Support -- RO. Does not apply. Hardwired to 0. Reserved. PME Status (PMES) -- R/WC. 0 = Software clears the bit by writing a 1 to it. 1 = This bit is set when the Intel(R) High Definition Audio controller would normally assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this register) This bit is in the resume well and only cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. 15 14:9 Reserved PME Enable (PMEE) -- R/W. 0 = Disable 1 = when set and if corresponding PMES also set, the Intel High Definition Audio controller sets the AC97_STS bit in the GPE0_STS register (PMBASE +28h). The AC97_STS bit is shared by AC '97 and Intel High Definition Audio functions since they are mutually exclusive. This bit is in the resume well and only cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. 8 7:2 Reserved Power State (PS) -- R/W. This field is used both to determine the current power state of the Intel High Definition Audio controller and to set a new power state. 00 = D0 state 11 = D3HOT state Others = reserved 1:0 NOTES: 1. If software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 2. When in the D3HOT states, the Intel High Definition Audio controller's configuration space is available, but the I/O and memory space are not. Additionally, interrupts are blocked. 3. When software changes this value from D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. Intel (R) ICH7 Family Datasheet 717 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.26 MID--MSI Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 60h-61h Default Value: 7005h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (Next) -- RO. Hardwired to 70h. Points to the PCI Express* capability structure. Cap ID (CAP) -- RO. Hardwired to 05h. Indicates that this pointer is a MSI capability 19.1.27 MMC--MSI Message Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 62h-63h Default Value: 0080h Bit 15:8 7 6:4 3:1 Reserved 64b Address Capability (64ADD) -- RO. Hardwired to 1 indicating the ability to generate a 64-bit message address Multiple Message Enable (MME) -- RO. Normally this is a R/W register. However, since only 1 message is supported, these bits are hardwired to 000 = 1 message. Multiple Message Capable (MMC) -- RO. Hardwired to 0 indicating request for 1 message. MSI Enable (ME) -- R/W. 0 0 = an MSI may not be generated 1 = an MSI will be generated instead of an INTx signal. Attribute: Size: Description RO, R/W 16 bits 19.1.28 MMLA--MSI Message Lower Address Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 64h-67h Default Value: 00000000h Bit 31:2 1:0 Attribute: Size: Description RO, R/W 32 bits Message Lower Address (MLA) -- R/W. Lower address used for MSI message. Reserved. 19.1.29 MMUA--MSI Message Upper Address Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 68h-6Bh Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits Message Upper Address (MUA) -- R/W. Upper 32-bits of address used for MSI message. 718 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.30 MMD--MSI Message Data Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 6Ch-6Dh Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16 bits Message Data (MD) -- R/W. Data used for MSI message. 19.1.31 PXID--PCI Express* Capability ID Register (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) Address Offset: 70h-71h Default Value: 0010h Bit 15:8 7:0 Attribute: Size: Description RO 16 bits Next Capability (Next) -- RO. Hardwired to 0. Indicates that this is the last capability structure in the list. Cap ID (CAP) -- RO. Hardwired to 10h. Indicates that this pointer is a PCI Express* capability structure 19.1.32 PXC--PCI Express* Capabilities Register (Desktop and Mobile Only) (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 72h-73h Default Value: 0091h Bit 15:14 13:9 8 7:4 3:0 Reserved Interrupt Message Number (IMN) -- RO. Hardwired to 0. Slot Implemented (SI) -- RO. Hardwired to 0. Device/Port Type (DPT) -- RO. Hardwired to 1001b. Indicates that this is a Root Complex Integrated endpoint device. Capability Version (CV) -- RO. Hardwired to 0001b. Indicates version #1 PCI Express capability Attribute: Size: Description RO 16 bits Intel (R) ICH7 Family Datasheet 719 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.33 DEVCAP--Device Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 74h-77h Default Value: 00000000h Bit 31:28 27:26 25:18 17:15 14 13 12 11:9 8:6 5 4:3 2:0 Reserved Captured Slot Power Limit Scale (SPLS) -- RO. Hardwired to 0. Captured Slot Power Limit Value (SPLV) -- RO. Hardwired to 0. Reserved Power Indicator Present -- RO. Hardwired to 0. Attention Indicator Present -- RO. Hardwired to 0. Attention Button Present -- RO. Hardwired to 0. Endpoint L1 Acceptable Latency -- R/WO. Endpoint L0s Acceptable Latency -- R/WO. Extended Tag Field Support -- RO. Hardwired to 0. Indicates 5-bit tag field support Phantom Functions Supported -- RO. Hardwired to 0. Indicates that phantom functions are not supported Max Payload Size Supported -- RO. Hardwired to 0. Indicates 128-B maximum payload size capability Attribute: Size: Description R/WO, RO 32 bits 720 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.34 DEVC--Device Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 78h-79h Default Value: 0800h Bit 15 14:12 Reserved Max Read Request Size -- RO. Hardwired to 0 enabling 128B maximum read request size. No Snoop Enable (NSNPEN) -- R/W. 0 = The Intel(R) High Definition Audio controller will not set the No Snoop bit. In this case, isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is not snooped. Isochronous transfers will use VC0. 1 = The Intel High Definition Audio controller is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may be used for isochronous transfers. Note: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. 10 9 8 7:5 4 3 2 1 0 Auxiliary Power Enable -- RO. Hardwired to 0, indicating that Intel High Definition Audio device does not draw AUX power Phantom Function Enable -- RO. Hardwired to 0 disabling phantom functions. Extended Tag Field Enable -- RO. Hardwired to 0 enabling 5-bit tag. Max Payload Size -- RO. Hardwired to 0 indicating 128B. Enable Relaxed Ordering -- RO. Hardwired to 0 disabling relaxed ordering. Unsupported Request Reporting Enable -- RO. Not implemented. Hardwired to 0. Fatal Error Reporting Enable -- RO. Not implemented. Hardwired to 0. Non-Fatal Error Reporting Enable -- RO. Not implemented. Hardwired to 0. Correctable Error Reporting Enable -- RO. Not implemented. Hardwired to 0. Attribute: Size: Description R/W, RO 16 bits 11 19.1.35 DEVS--Device Status Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 7Ah-7Bh Default Value: 0010h Bit 15:6 Reserved Transactions Pending -- RO. 5 0 = Indicates that completions for all non-posted requests have been received. 1 = Indicates that Intel(R) High Definition Audio controller has issued non-posted requests that have not been completed. AUX Power Detected -- RO. Hardwired to 1 indicating the device is connected to resume power. Unsupported Request Detected -- RO. Not implemented. Hardwired to 0. Fatal Error Detected -- RO. Not implemented. Hardwired to 0. Non-Fatal Error Detected -- RO. Not implemented. Hardwired to 0. Correctable Error Detected -- RO. Not implemented. Hardwired to 0. Attribute: Size: Description RO 16 bits 4 3 2 1 0 Intel (R) ICH7 Family Datasheet 721 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.36 VCCAP--Virtual Channel Enhanced Capability Header (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) Address Offset: 100h-103h Default Value: 13010002h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability Offset -- RO. Hardwired to 130h. Points to the next capability header that is the Root Complex Link Declaration Enhanced Capability Header. Capability Version -- RO. Hardwired to 1h. PCI Express* Extended Capability -- RO. Hardwired to 0002h. 19.1.37 PVCCAP1--Port VC Capability Register 1 (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) Address Offset: 104h-107h Default Value: 00000001h Bit 31:12 11:10 9:8 7 6:4 3 2:0 Reserved. Port Arbitration Table Entry Size -- RO. Hardwired to 0 since this is an endpoint device. Reference Clock -- RO. Hardwired to 0 since this is an endpoint device. Reserved. Low Priority Extended VC Count -- RO. Hardwired to 0. Indicates that only VC0 belongs to the low priority VC group. Reserved. Extended VC Count -- RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is supported by the Intel(R) High Definition Audio controller. Attribute: Size: Description RO 32 bits 19.1.38 PVCCAP2 -- Port VC Capability Register 2 (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 108h-10Bh Default Value: 00000000h Bit 31:24 23:8 7:0 Attribute: Size: Description RO 32 bits VC Arbitration Table Offset -- RO. Hardwired to 0 indicating that a VC arbitration table is not present. Reserved. VC Arbitration Capability -- RO. Hardwired to 0. These bits are not applicable since the Intel(R) High Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register. 722 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.39 PVCCTL -- Port VC Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 10Ch-10Dh Default Value: 0000h Bit 15:4 3:1 Reserved. VC Arbitration Select -- RO. Hardwired to 0. Normally these bits are R/W. However, these bits are not applicable since the Intel(R) High Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1 register. Load VC Arbitration Table -- RO. Hardwired to 0 since an arbitration table is not present. Attribute: Size: Description RO 16 bits 0 19.1.40 PVCSTS--Port VC Status Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 10Eh-10Fh Default Value: 0000h Bit 15:1 0 Reserved. VC Arbitration Table Status -- RO. Hardwired to 0 since an arbitration table is not present. Attribute: Size: Description RO 16 bits 19.1.41 VC0CAP--VC0 Resource Capability Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 110h-113h Default Value: 00000000h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. Maximum Time Slots -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reject Snoop Transactions -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Advanced Packet Switching -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. Port Arbitration Capability -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Intel (R) ICH7 Family Datasheet 723 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.42 VC0CTL--VC0 Resource Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 114h-117h Default Value: 800000FFh Bit 31 30:27 26:24 23:20 19:17 16 15:8 7:0 Attribute: Size: Description R/W, RO 32 bits VC0 Enable -- RO. Hardwired to 1 for VC0. Reserved. VC0 ID -- RO. Hardwired to 0 since the first VC is always assigned as VC0. Reserved. Port Arbitration Select -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Load Port Arbitration Table -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. TC/VC0 Map -- R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits [7:1] are implemented as R/W bits. 19.1.43 VC0STS--VC0 Resource Status Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 11Ah-11Bh Default Value: 0000h Bit 15:2 1 0 Reserved. VC0 Negotiation Pending -- RO. Hardwired to 0 since this bit does not apply to the integrated Intel(R) High Definition Audio device. Port Arbitration Table Status -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Attribute: Size: Description RO 16 bits 724 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.44 VCiCAP--VCi Resource Capability Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 11Ch-11Fh Default Value: 00000000h Bit 31:24 23 22:16 15 14 13:8 7:0 Attribute: Size: Description RO 32 bits Port Arbitration Table Offset -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. Maximum Time Slots -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reject Snoop Transactions -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Advanced Packet Switching -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved Port Arbitration Capability -- RO. Hardwired to 0 since this field is not valid for endpoint devices. 19.1.45 VCiCTL--VCi Resource Control Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 120h-123h Default Value: 00000000h Bit VCi Enable -- R/W. 0 = VCi is disabled 31 1 = VCi is enabled NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#. 30:27 26:24 23:20 19:17 16 15:8 Reserved. VCi ID -- R/W. This field assigns a VC ID to the VCi resource. This field is not used by the Intel(R) ICH7 hardware, but it is R/W to avoid confusing software. Reserved. Port Arbitration Select -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Load Port Arbitration Table -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Reserved. TC/VCi Map -- R/W, RO. This field indicates the TCs that are mapped to the VCi resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1] are implemented as R/W bits. This field is not used by the ICH7 hardware, but it is R/W to avoid confusing software. Attribute: Size: Description R/W, RO 32 bits 7:0 Intel (R) ICH7 Family Datasheet 725 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.46 VCiSTS--VCi Resource Status Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 126h-127h Default Value: 0000h Bit 15:2 1 0 Reserved. VCi Negotiation Pending -- RO. Does not apply. Hardwired to 0. Port Arbitration Table Status -- RO. Hardwired to 0 since this field is not valid for endpoint devices. Attribute: Size: Description RO 16 bits 19.1.47 RCCAP--Root Complex Link Declaration Enhanced Capability Header Register (Intel(R) High Definition Audio Controller--D27:F0) (Desktop and Mobile Only) Address Offset: 130h-133h Default Value: 00010005h Bit 31:20 19:16 15:0 Attribute: Size: Description RO 32 bits Next Capability Offset -- RO. Hardwired to 0 indicating this is the last capability. Capability Version -- RO. Hardwired to 1h. PCI Express* Extended Capability ID -- RO. Hardwired to 0005h. 19.1.48 ESD--Element Self Description Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 134h-137h Default Value: 0F000100h Bit 31:24 23:16 15:8 7:4 3:0 Attribute: Size: Description RO 32 bits Port Number -- RO. Hardwired to 0Fh indicating that the Intel(R) High Definition Audio controller is assigned as Port #15d. Component ID -- RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. Number of Link Entries -- RO. The Intel High Definition Audio only connects to one device, the Intel(R) ICH7 egress port. Therefore this field reports a value of 1h. Reserved. Element Type (ELTYP) -- RO. The Intel High Definition Audio controller is an integrated Root Complex Device. Therefore, the field reports a value of 0h. 726 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.1.49 L1DESC--Link 1 Description Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 140h-143h Default Value: 00000001h Bit 31:24 23:16 15:2 1 0 Attribute: Size: Description RO 32 bits Target Port Number -- RO. The Intel High Definition Audio controller targets the Intel(R) ICH7's Port #0. Target Component ID -- RO. This field returns the value of the ESD.CID field of the chip configuration section. ESD.CID is programmed by BIOS. Reserved. Link Type -- RO. Hardwired to 0 indicating Type 0. Link Valid -- RO. Hardwired to 1. 19.1.50 L1ADDL--Link 1 Lower Address Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 148h-14Bh Default Value: See Register Description Bit 31:14 13:0 Attribute: Size: RO 32 bits Description Link 1 Lower Address -- RO. Hardwired to match the RCBA register value in the PCI-LPC bridge (D31:F0:F0h). Reserved. 19.1.51 L1ADDU--Link 1 Upper Address Register (Intel(R) High Definition Audio Controller--D27:F0) Address Offset: 14Ch-14Fh Default Value: 00000000h Bit 31:0 Attribute: Size: Description RO 32 bits Link 1 Upper Address -- RO. Hardwired to 00000000h. Intel (R) ICH7 Family Datasheet 727 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2 Intel(R) High Definition Audio Memory-Mapped Configuration Registers (Intel(R) High Definition Audio-- D27:F0) The base memory location for these memory mapped configuration registers is specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The individual registers are then accessible at HDBAR + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Table 19-2. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 1 of 4) HDBAR + Offset 00h-01h 02h 03h 04h-05h 06h-07h 08h-0Bh 0Ch-0Dh 0Eh-0Fh 10h-11h 12h-13h 14h-17h 1 8h-19h 1Ah-1Bh 1Ch-1Fh 20h-23h 24h-27h 30h-33h 34h-37h 40h-43h 44h-47h 48h-49h 4Ah-4Bh 4Ch 4Dh 4Eh 50h-53h 54h-57h Mnemonic GCAP VMIN VMAJ OUTPAY INPAY GCTL WAKEEN STATESTS GSTS -- ECAP OUTSTRMPAY INSTRMPAY -- INTCTL INTSTS WALCLK SSYNC CORBLBASE CORBUBASE CORBWP CORBRP CORBCTL CORBST CORBSIZE RIRBLBASE RIRBUBASE Register Name Global Capabilities Minor Version Major Version Output Payload Capability Input Payload Capability Global Control Wake Enable State Change Status Global Status Reserved Extended Capabilities (Mobile/Ultra Mobile Only) Output Stream Payload Capability Input Stream Payload Capability Reserved Interrupt Control Interrupt Status Wall Clock Counter Stream Synchronization CORB Lower Base Address CORB Upper Base Address CORB Write Pointer CORB Read Pointer CORB Control CORB Status CORB Size RIRB Lower Base Address RIRB Upper Base Address Default 4401h 00h 01h 003Ch 001Dh 00000000h 0000h 0000h 0000h 0000h 00000001h 0030h 0018h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0000h 0000h 00h 00h 42h 00000000h 00000000h Access RO RO RO RO RO R/W R/W R/WC R/WC RO RO RO RO RO R/W RO RO R/W R/W, RO R/W R/W R/W R/W R/WC RO R/W, RO R/W 728 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Table 19-2. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 2 of 4) HDBAR + Offset 58h-59h 5Ah-5Bh 5Ch 5Dh 5Eh 60h-63h 64h-67h 68h-69h 70h-73h 74h-77h 80-82h 83h 84h-87h 88h-8Bh 8Ch-8Dh 8Eh-8F 90h-91h 92h-93h 98h-9Bh 9Ch-9Fh A0h-A2h A3h A4h-A7h A8h-ABh ACh-ADh AEh-AFh B0h-B1h B2-B3h B8-BBh BCh-BFh C0h-C2h Mnemonic RIRBWP RINTCNT RIRBCTL RIRBSTS RIRBSIZE IC IR IRS DPLBASE DPUBASE ISD0CTL ISD0STS ISD0LPIB ISD0CBL ISD0LVI ISD0FIFOW ISD0FIFOS ISD0FMT ISD0BDPL ISD0BDPU ISD1CTL ISD1STS ISD1LPIB ISD1CBL ISD1LVI ISD1FIFOW ISD1FIFOS ISD1FMT ISD1BDPL ISD1BDPU ISD2CTL Register Name RIRB Write Pointer Response Interrupt Count RIRB Control RIRB Status RIRB Size Immediate Command Immediate Response Immediate Command Status DMA Position Lower Base Address DMA Position Upper Base Address Input Stream Descriptor 0 (ISD0) Control ISD0 Status ISD0 Link Position in Buffer ISD0 Cyclic Buffer Length ISD0 Last Valid Index ISD0 FIFO Watermark ISD0 FIFO Size ISD0 Format ISD0 Buffer Descriptor List PointerLower Base Address ISD0 Buffer Description List PointerUpper Base Address Input Stream Descriptor 1(ISD01) Control ISD1 Status ISD1 Link Position in Buffer ISD1 Cyclic Buffer Length ISD1 Last Valid Index ISD1 FIFO Watermark ISD1 FIFO Size ISD1 Format ISD1 Buffer Descriptor List PointerLower Base Address ISD1 Buffer Description List PointerUpper Base Address Input Stream Descriptor 2 (ISD2) Control Default 0000h 0000h 00h 00h 42h 00000000h 00000000h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h Access R/W, RO R/W R/W R/WC RO R/W RO R/W, R/ WC R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO Intel (R) ICH7 Family Datasheet 729 Intel(R) High Definition Audio Controller Registers (D27:F0) Table 19-2. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 3 of 4) HDBAR + Offset C3h Ch4-C7h C8h-CBh CCh-CDh CEh-CFh D0h-D1h D2h-D3h D8h-DBh DCh-DFh E0h-E2h E3h E4h-E7h E8h-EBh ECh-EDh EEh-EFh F0h-F1h F2h-F3h F8h-FBh FCh-FFh 100h-102h 103h 104h-107h 108h-10Bh 10Ch-10Dh 10Eh-10Fh 110h-111h 112-113h 118h-11Bh 11Ch-11Fh 120h-122h Mnemonic ISD2STS ISD2LPIB ISD2CBL ISD2LVI ISD1FIFOW ISD2FIFOS ISD2FMT ISD2BDPL ISD2BDPU ISD3CTL ISD3STS ISD3LPIB ISD3CBL ISD3LVI ISD3FIFOW ISD3FIFOS ISD3FMT ISD3BDPL ISD3BDPU OSD0CTL OSD0STS OSD0LPIB OSD0CBL OSD0LVI OSD0FIFOW OSD0FIFOS OSD0FMT OSD0BDPL OSD0BDPU OSD1CTL Register Name ISD2 Status ISD2 Link Position in Buffer ISD2 Cyclic Buffer Length ISD2 Last Valid Index ISD1 FIFO Watermark ISD2 FIFO Size ISD2 Format ISD2 Buffer Descriptor List PointerLower Base Address ISD2 Buffer Description List PointerUpper Base Address Input Stream Descriptor 3 (ISD3) Control ISD3 Status ISD3 Link Position in Buffer ISD3 Cyclic Buffer Length ISD3 Last Valid Index ISD3 FIFO Watermark ISD3 FIFO Size ISD3 Format ISD3 Buffer Descriptor List PointerLower Base Address ISD3 Buffer Description List PointerUpper Base Address Output Stream Descriptor 0 (OSD0) Control OSD0 Status OSD0 Link Position in Buffer OSD0 Cyclic Buffer Length OSD0 Last Valid Index OSD0 FIFO Watermark OSD0 FIFO Size OSD0 Format OSD0 Buffer Descriptor List PointerLower Base Address OSD0 Buffer Description List PointerUpper Base Address Output Stream Descriptor 1 (OSD1) Control Default 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 0077h 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h Access R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W RO R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W R/W, RO 730 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Table 19-2. Intel(R) High Definition Audio PCI Register Address Map (Intel(R) High Definition Audio D27:F0) (Sheet 4 of 4) HDBAR + Offset 123h 124h-127h 128h-12Bh 12Ch-12Dh 12Eh-12Fh 130h-131h 132h-133h 138h-13Bh 13Ch-13Fh 140h-142h 143h 144h-147h 148h-14Bh 14Ch-14Dh 14Eh-14Fh 150h-151h 152h-153h 158h-15Bh 15Ch-15Fh 160h-162h 163h 164h-167h 168h-16Bh 16Ch-16Dh 16Eh-16Fh 170h-171h 172h-173h 178h-17Bh 17Ch-17Fh Mnemonic OSD1STS OSD1LPIB OSD1CBL OSD1LVI OSD1FIFOW OSD1FIFOS OSD1FMT OSD1BDPL OSD1BDPU OSD2CTL OSD2STS OSD2LPIB OSD2CBL OSD2LVI OSD2FIFOW OSD2FIFOS OSD2FMT OSD2BDPL OSD2BDPU OSD3CTL OSD3STS OSD3LPIB OSD3CBL OSD3LVI OSD3FIFOW OSD3FIFOS OSD3FMT OSD3BDPL OSD3BDPU Register Name OSD1 Status OSD1 Link Position in Buffer OSD1 Cyclic Buffer Length OSD1 Last Valid Index OSD1 FIFO Watermark OSD1 FIFO Size OSD1 Format OSD1 Buffer Descriptor List PointerLower Base Address OSD1 Buffer Description List PointerUpper Base Address Output Stream Descriptor 2 (OSD2) Control OSD2 Status OSD2 Link Position in Buffer OSD2 Cyclic Buffer Length OSD2 Last Valid Index OSD2 FIFO Watermark OSD2 FIFO Size OSD2 Format OSD2 Buffer Descriptor List PointerLower Base Address OSD2 Buffer Description List PointerUpper Base Address Output Stream Descriptor 3 (OSD3) Control OSD3 Status OSD3 Link Position in Buffer OSD3 Cyclic Buffer Length OSD3 Last Valid Index OSD3 FIFO Watermark OSD3 FIFO Size OSD3 Format OSD3 Buffer Descriptor List PointerLower Base Address OSD3 Buffer Description List PointerUpper Base Address Default 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h 040000h 00h 00000000h 00000000h 0000h 0004h 00BFh 0000h 00000000h 00000000h Access R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W R/W, RO R/WC, RO RO R/W R/W R/W R/W R/W R/W, RO R/W Intel (R) ICH7 Family Datasheet 731 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.1 GCAP--Global Capabilities Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 00h Default Value: 4401h Bit 15:12 11:8 7:3 2 1 Attribute: Size: Description RO 16 bits Number of Output Stream Supported -- RO. Hardwired to 0100b indicating that the Intel(R) ICH7 Intel(R) High Definition Audio controller supports 4 output streams. Number of Input Stream Supported -- RO. Hardwired to 0100b indicating that the ICH7 Intel High Definition Audio controller supports 4 input streams. Number of Bidirectional Stream Supported -- RO. Hardwired to 0 indicating that the ICH7 Intel High Definition Audio controller supports 0 bidirectional stream. Reserved. Number of Serial Data Out Signals -- RO. Hardwired to 0 indicating that the ICH7 Intel High Definition Audio controller supports 1 serial data output signal. 64-bit Address Supported -- RO. Hardwired to 1b indicating that the ICH7 Intel High Definition Audio controller supports 64-bit addressing for BDL addresses, data buffer addressees, and command buffer addresses. 0 19.2.2 VMIN--Minor Version Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 02h Default Value: 00h Bit 7:0 Attribute: Size: Description RO 8 bits Minor Version -- RO. Hardwired to 0 indicating that the Intel(R) ICH7 supports minor revision number 00h of the Intel(R) High Definition Audio specification. 19.2.3 VMAJ--Major Version Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 03h Default Value: 01h Bit 7:0 Attribute: Size: Description RO 8 bits Major Version -- RO. Hardwired to 01h indicating that the Intel(R) ICH7 supports major revision number 1 of the Intel(R) High Definition Audio specification. 732 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.4 OUTPAY--Output Payload Capability Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 04h Default Value: 003Ch Bit 15:7 Reserved. Output Payload Capability -- RO. Hardwired to 3Ch indicating 60 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for command and control. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. Attribute: Size: Description RO 16 bits 6:0 19.2.5 INPAY--Input Payload Capability Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 06h Default Value: 001Dh Bit 15:7 Reserved. Input Payload Capability -- RO. Hardwired to 1Dh indicating 29 word payload. This field indicates the total output payload available on the link. This does not include bandwidth used for response. This measurement is in 16-bit word quantities per 48 MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... FFh = 256 word payload. Attribute: Size: Description RO 16 bits 6:0 Intel (R) ICH7 Family Datasheet 733 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.6 GCTL--Global Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 08h Default Value: 00000000h Bit 31:9 Reserved. Accept Unsolicited Response Enable -- R/W. 8 0 = Unsolicited responses from the codecs are not accepted. 1 = Unsolicited response from the codecs are accepted by the controller and placed into the Response Input Ring Buffer. Reserved. Flush Control -- R/W. 0 = Flush Not in progress. 1 = Writing a 1 to this bit initiates a flush. When the flush completion is received by the controller, hardware sets the Flush Status bit and clears this Flush Control bit. Before a flush cycle is initiated, the DMA Position Buffer must be programmed with a valid memory address by software, but the DMA Position Buffer bit 0 needs not be set to enable the position reporting mechanism. Also, all streams must be stopped (the associated RUN bit must be 0). When the flush is initiated, the controller will flush the pipelines to memory to ensure that the hardware is ready to transition to a D3 state. Setting this bit is not a critical step in the power state transition if the content of the FIFIOs is not critical. Controller Reset # -- R/W. 0 = Writing a 0 to this bit causes the Intel High Definition Audio controller to be reset. All state machines, FIFOs, and non-resume well memory mapped configuration registers (not PCI configuration registers) in the controller will be reset. The Intel High Definition Audio link RESET# signal will be asserted, and all other link signals will be driven to their default values. After the hardware has completed sequencing into the reset state, it will report a 0 in this bit. Software must read a 0 from this bit to verify the controller is in reset. 1 = Writing a 1 to this bit causes the controller to exit its reset state and deassert the Intel High Definition Audio link RESET# signal. Software is responsible for setting/ clearing this bit such that the minimum Intel High Definition Audio link RESET# signal assertion pulse width specification is met. When the controller hardware is ready to begin operation, it will report a 1 in this bit. Software must read a 1 from this bit before accessing any controller registers. This bit defaults to a 0 after Hardware reset, therefore, software needs to write a 1 to this bit to begin operation. NOTES: 1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. When setting or clearing this bit, software must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met. 3. When this bit is 0 indicating that the controller is in reset, writes to all Intel High Definition Audio memory mapped registers are ignored as if the device is not present. The only exception is this register itself. The Global Control register is write-able as a DWord, Word, or Byte even when CRST# (this bit) is 0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes to the Global Control register will be ignored when CRST# is 0. When CRST# is 0, reads to Intel High Definition Attribute: Size: Description R/W 32 bits 7:2 1 0 734 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.7 WAKEEN--Wake Enable Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 0Ch Default Value: 0000h Bit 15:3 Reserved. SDIN Wake Enable Flags -- R/W. These bits control which SDI signal(s) may generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is enabled to generate a wake. Bit 0 is used for SDI0 2:0 Bit 1 is used for SDI1 Bit 2 is used for SDI2 NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. Attribute: Size: Description R/W 16 bits 19.2.8 STATESTS--State Change Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 0Eh Default Value: 0000h Bit 15:3 Reserved. SDIN State Change Status Flags -- R/WC. Flag bits that indicate which SDI signal(s) received a state change event. The bits are cleared by writing 1's to them. Bit 0 = SDI0 2:0 Bit 1 = SDI1 Bit 2 = SDI2 NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not make assumptions about the reset state of these bits and must set them appropriately. Attribute: Size: Description R/WC 16 bits Intel (R) ICH7 Family Datasheet 735 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.9 GSTS--Global Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 10h Default Value: 0000h Bit 15:4 3 (Desktop /Ultra Mobile Only) Reserved. Attribute: Size: Description R/WC 16 bits Reserved Dock Mated Interrupt Status (DMIS) -- RW/C. 0 = Software clears this bit by writing a 1 to it. 1 = Dock mating or unmating process has completed. For the docking process, it indicates that dock is electrically connected and that software may detect and enumerate the docked codecs. For the undocking process, it indicates that the dock is electrically isolated and that software may report to the user that physical undocking may commence. This bit gets set to a 1 by hardware when the DM bit transitions from 0-to-1 (docking) or from 1-to-0 (undocking). Note that this bit is set regardless of the state of the DMIE bit. 3 (Mobile Only) 2 (Desktop /Ultra Mobile Only) Reserved Dock Mated (DM) -- RO. This bit effectively communicates to software that an Intel(R) HD Audio docked codec is physically and electrically attached. 2 (Mobile Only) 0 = Controller hardware sets this bit to 0 after the undocking sequence triggered by writing a 0 to the Dock Attach (GCTL.DA) bit is completed (DOCK_EN# deasserted). This bit indicates to software that the docked codec(s) may be physically undocked. 1 = Controller hardware sets this bit to 1 after the docking sequence triggered by writing a 1 to the Dock Attach (GCTL.DA) bit is completed (AZ_DOCK_RST# deassertion). This bit indicates to software that the docked codec(s) may be discovered via the STATESTS register and then enumerated. Flush Status -- R/WC. 0 = Flush not completed 1 = This bit is set to 1 by hardware to indicate that the flush cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has completed. NOTE: Software must write a 1 to clear this bit before the next time the Flush Control bit is set to clear the bit. 0 Reserved. 1 736 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.10 ECAP--Extended Capabilities (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 14h Default Value: 00000001h Bit 31:1 Reserved Docking Supported (DS)-- R/WO. A 1 indicates that Intel(R) ICH7 supports Intel(R) HD Audio Docking. The GCTL.DA bit is only writable when this DS bit is 1. Intel HD Audio driver software should only branch to its docking routine when this DS bit is 1. BIOS may clear this bit to 0 to prohibit the Intel HD Audio driver software from attempting to run the docking routines. NOTE: This bit is reset to its default value only on a PLTRST#, but not on a CRST# or D3hot-to-D0 transition. Attribute: Size: Description R/WO 32 bits 0 (Mobile Only) 19.2.11 OUTSTRMPAY--Output Stream Payload Capability (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 18h Default Value: 0030h Bit Attribute: Size: Description RO 16 bits Output FIFO Padding Type (OPADTYPE) -- RO. This field indicates how the controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may pad to byte or memory container sizes. 15:14 0h 1h 2h 3h = = = = Controller pads all samples to bytes Reserved Controller pads to memory container size Controller does not pad and uses samples directly 13:0 Output Stream Payload Capability (OUTSTRMPAY) -- RO. This field indicates maximum number of words per frame for any single output stream. This measurement is in 16 bit word quantities per 48 kHz frame. The maximum supported is 48 Words (96B); therefore, a value of 30h is reported in this register. The value does not specify the number of words actually transmitted in the frame, but is the size of the data in the controller buffer (FIFO) after the samples are padded as specified by OPADTYPE. Thus, to compute the supported streams, each sample is padded according to OPADTYPE and then multiplied by the number of channels and samples per frame. If this computed value is larger than OUTSTRMPAY, then that stream is not supported. The value specified is not affected by striping. Software must ensure that a format that would cause more Words per frame than indicated is not programmed into the Output Stream Descriptor Register. The value may be larger than the OUTPAY register value in some cases. Intel (R) ICH7 Family Datasheet 737 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.12 INSTRMPAY--Input Stream Payload Capability (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 1Ah Default Value: 0018h Bit Attribute: Size: Description RO 16 bits Input FIFO Padding Type (IPADTYPE) -- RO. This field indicates how the controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may pad to byte or memory container sizes. 15:14 0h 1h 2h 3h = = = = Controller pads all samples to bytes Reserved Controller pads to memory container size Controller does not pad and uses samples directly Input Stream Payload Capability (INSTRMPAY) -- RO. This field indicates the maximum number of Words per frame for any single input stream. This measurement is in 16-bit Word quantities per 48-kHz frame. The maximum supported is 24 Words (48B); therefore, a value of 18h is reported in this register. The value does not specify the number of words actually transmitted in the frame, but is the size of the data as it will be placed into the controller's buffer (FIFO). Thus, samples will be padded according to IPADTYPE before being stored into controller buffer. To compute the supported streams, each sample is padded according to IPADTYPE and then multiplied by the number of channels and samples per frame. If this computed value is larger than INSTRMPAY, then that stream is not supported. As the inbound stream tag is not stored with the samples it is not included in the word count. The value may be larger than INPAY register value in some cases, although values less than INPAY may also be invalid due to overhead. Software must ensure that a format that would cause more Words per frame than indicated is not programmed into the Input Stream Descriptor Register. 13:0 738 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.13 INTCTL--Interrupt Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 20h Default Value: 00000000h Bit Attribute: Size: Description R/W 32 bits Global Interrupt Enable (GIE) -- R/W. Global bit to enable device interrupt generation. 31 0 = Disable. 1 = Enable. The Intel(R) High Definition Audio function is enabled to generate an interrupt. This control is in addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI configuration space. NOTE: This bit is not affected by the D3HOT to D0 transition. Controller Interrupt Enable (CIE) -- R/W. Enables the general interrupt for controller functions. 30 0 = Disable. 1 = Enable. The controller generates an interrupt when the corresponding status bit gets set due to a Response Interrupt, a Response Buffer Overrun, and State Change events. NOTE: This bit is not affected by the D3HOT to D0 transition. 29:8 Reserved Stream Interrupt Enable (SIE) -- R/W. 0 = Disable. 1 = Enable. When set to 1, the individual streams are enabled to generate an interrupt when the corresponding status bits get set. A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control over the generation of each of these sources is in the associated Stream Descriptor. 7:0 The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 Intel (R) ICH7 Family Datasheet 739 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.14 INTSTS--Interrupt Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 24h Default Value: 00000000h Bit Attribute: Size: Description RO 32 bits 31 Global Interrupt Status (GIS) -- RO. This bit is an OR of all the interrupt status bits in this register. NOTE: This bit is not affected by the D3HOT to D0 transition. Controller Interrupt Status (CIS) -- RO. Status of general controller interrupt. 0 = An interrupt condition did Not occur as described below. 1 = An interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. This bit is an OR of all of the stated interrupt status bits for this register. NOTES: 1. This bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be generated unless the corresponding enable bit is set. 2. This bit is not affected by the D3HOT to D0 transition. 30 29:8 Reserved Stream Interrupt Status (SIS) -- RO. 0 = An interrupt condition did Not occur on the corresponding stream. 1 = An interrupt condition occurred on the corresponding stream. This bit is an OR of all of the stream's interrupt status bits. NOTE: These bits are set regardless of the state of the corresponding interrupt enable bits. 7:0 The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 740 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.15 WALCLK--Wall Clock Counter Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 30h Default Value: 00000000h Bit Attribute: Size: Description RO 32 bits 31:0 Wall Clock Counter -- RO. This 32-bit counter field is incremented on each link BCLK period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0 with a period of approximately 179 seconds. This counter is enabled while the BCLK bit is set to 1. Software uses this counter to synchronize between multiple controllers. Will be reset on controller reset. 19.2.16 SSYNC--Stream Synchronization Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 34h Default Value: 00000000h Bit 31:8 Reserved Stream Synchronization (SSYNC) -- R/W. 0 = Data is Not blocked from being sent on or received from the link 1 = The set bits block data from being sent on or received from the link. Each bit controls the associated stream descriptor (i.e., bit 0 corresponds to the first stream descriptor, etc.) To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits for the associated stream descriptors are then set to 1 to start the DMA engines. When all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame. To synchronously stop the streams, first these bits are set, and then the individual RUN bits in the stream descriptor are cleared by software. 7:0 If synchronization is not desired, these bits may be left as 0, and the stream will simply begin running normally when the stream's RUN bit is set. The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set. Bit 0 = input stream 1 Bit 1 = input stream 2 Bit 2 = input stream 3 Bit 3 = input stream 4 Bit 4 = output stream 1 Bit 5 = output stream 2 Bit 6 = output stream 3 Bit 7 = output stream 4 Attribute: Size: Description R/W 32 bits Intel (R) ICH7 Family Datasheet 741 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.17 CORBLBASE--CORB Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 40h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 CORB Lower Base Address -- R/W. This field is the lower address of the Command Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. CORB Lower Base Unimplemented Bits -- RO. Hardwired to 0. This requires the CORB to be allocated with 128B granularity to allow for cache line fetch optimizations. 6:0 19.2.18 CORBUBASE--CORB Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 44h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits CORB Upper Base Address -- R/W. This field is the upper 32 bits of the address of the Command Output Ring buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. 19.2.19 CORBWP--CORB Write Pointer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 48h Default Value: 0000h Bit 15:8 Reserved. CORB Write Pointer -- R/W. Software writes the last valid CORB entry offset into this field in DWord granularity. The DMA engine fetches commands from the CORB until the Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB). This register field may be written when the DMA engine is running. Attribute: Size: Description R/W 16 bits 7:0 742 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.20 CORBRP--CORB Read Pointer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 4Ah Default Value: 0000h Bit Attribute: Size: Description R/W 16 bits 15 CORB Read Pointer Reset -- R/W. Software writes a 1 to this bit to reset the CORB Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel(R) High Definition Audio controller. The hardware will physically update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify that the reset completed correctly. Software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. The CORB DMA engine must be stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted. Reserved. CORB Read Pointer (CORBRP) -- RO. Software reads this field to determine how many commands it can write to the CORB without over-running. The value read indicates the CORB Read Pointer offset in DWord granularity. The offset entry read from this field has been successfully fetched by the DMA controller and may be over-written by software. Supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA engine is running. 14:8 7:0 19.2.21 CORBCTL--CORB Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 4Ch Default Value: 00h Bit 7:2 Reserved. Enable CORB DMA Engine -- R/W. After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. 0 = DMA stop 1 = DMA run CORB Memory Error Interrupt Enable -- R/W. 0 0 = Disable. 1 = Enable. The controller will generate an interrupt if the CMEI status bit (HDBAR + 4Dh: bit 0) is set. Attribute: Size: Description R/W 8 bits 1 Intel (R) ICH7 Family Datasheet 743 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.22 CORBST--CORB Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 4Dh Default Value: 00h Bit 7:1 Reserved. CORB Memory Error Indication (CMEI) -- R/WC. 0 = Error Not detected. 1 = The controller has detected an error in the path way between the controller and memory. This may be an ECC bit error or any other type of detectable data error which renders the command data fetched invalid. NOTE: Software can clear this bit by writing a 1 to it. However, this type of error leaves the audio subsystem in an un-viable state and typically requires a controller reset by writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0). Attribute: Size: Description R/WC 8 bits 0 19.2.23 CORBSIZE--CORB Size Register Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 4Eh Default Value: 42h Bit 7:4 3:2 1:0 Attribute: Size: Description RO 8 bits CORB Size Capability -- RO. Hardwired to 0100b indicating that the ICH7 only supports a CORB size of 256 CORB entries (1024B). Reserved. CORB Size -- RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B). 19.2.24 RIRBLBASE--RIRB Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 50h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 RIRB Lower Base Address -- R/W. This field is the lower address of the Response Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B boundary. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. RIRB Lower Base Unimplemented Bits -- RO. Hardwired to 0. This required the RIRB to be allocated with 128-B granularity to allow for cache line fetch optimizations. 6:0 744 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.25 RIRBUBASE--RIRB Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 54h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits RIRB Upper Base Address -- R/W. This field is the upper 32 bits of the address of the Response Input Ring Buffer. This register field must not be written when the DMA engine is running or the DMA transfer may be corrupted. 19.2.26 RIRBWP--RIRB Write Pointer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 58h Default Value: 0000h Bit Attribute: Size: Description R/W, RO 16 bits 15 RIRB Write Pointer Reset -- R/W. Software writes a 1 to this bit to reset the RIRB Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit is always read as 0. Reserved. RIRB Write Pointer (RIRBWP) -- RO. This field is the indicates the last valid RIRB entry written by the DMA controller. Software reads this field to determine how many responses it can read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 DWord RIRB entry units (since each RIRB entry is 2 DWords long). Supports up to 256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the DMA engine is running. 14:8 7:0 Intel (R) ICH7 Family Datasheet 745 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.27 RINTCNT--Response Interrupt Count Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 5Ah Default Value: 0000h Bit 15:8 Reserved. N Response Interrupt Count -- R/W. 0000 0001b = 1 response sent to RIRB ........... 1111 1111b = 255 responses sent to RIRB 0000 0000b = 256 responses sent to RIRB 7:0 The DMA engine should be stopped when changing this field or else an interrupt may be lost. Note that each response occupies 2 DWords in the RIRB. This is compared to the total number of responses that have been returned, as opposed to the number of frames in which there were responses. If more than one codec responds in one frame, then the count is increased by the number of responses received in the frame. Attribute: Size: Description R/W 16 bits 19.2.28 RIRBCTL--RIRB Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 5Ch Default Value: 00h Bit 7:3 Reserved. Response Overrun Interrupt Control -- R/W. 2 0 = Hardware will Not generated an interrupt as described below. 1 = The hardware will generate an interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh: bit 2) is set. Enable RIRB DMA Engine -- R/W. After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from this bit to verify that the DMA engine is truly stopped. 0 = DMA stop 1 = DMA run Response Interrupt Control -- R/W. 0 0 = Disable Interrupt 1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). The N counter is reset when the interrupt is generated. Attribute: Size: Description R/W 8 bits 1 746 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.29 RIRBSTS--RIRB Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 5Dh Default Value: 00h Bit 7:3 Reserved. Response Overrun Interrupt Status -- R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses that overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is set. Note that this status bit is set even if an interrupt is not enabled for this event. Reserved. Response Interrupt -- R/WC. 0 0 = Software clears this bit by writing a 1 to it. 1 = Hardware sets this bit to 1 when an interrupt has been generated after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit is set even if an interrupt is not enabled for this event. Attribute: Size: Description R/WC 8 bits 2 1 19.2.30 RIRBSIZE--RIRB Size Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 5Eh Default Value: 42h Bit 7:4 3:2 1:0 Attribute: Size: Description RO 8 bits RIRB Size Capability -- RO. Hardwired to 0100b indicating that the ICH7 only supports a RIRB size of 256 RIRB entries (2048B) Reserved. RIRB Size -- RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B) 19.2.31 IC--Immediate Command Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 60h Default Value: 00000000h Bit Attribute: Size: Description R/W 32 bits 31:0 Immediate Command Write -- R/W. The command to be sent to the codec via the Immediate Command mechanism is written to this register. The command stored in this register is sent out over the link during the next available frame after a 1 is written to the ICB bit (HDBAR + 68h: bit 0) Intel (R) ICH7 Family Datasheet 747 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.32 IR--Immediate Response Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 64h Default Value: 00000000h Bit Attribute: Size: Description RO 32 bits Immediate Response Read (IRR) -- RO. This register contains the response received from a codec resulting from a command sent via the Immediate Command mechanism. 31:0 If multiple codecs responded in the same time, there is no assurance as to which response will be latched. Therefore, broadcast-type commands must not be issued via the Immediate Command mechanism. 19.2.33 IRS--Immediate Command Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 68h Default Value: 0000h Bit 15:2 Reserved. Immediate Result Valid (IRV) -- R/WC. 1 0 = Software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. 1 = Set to 1 by hardware when a new response is latched into the Immediate Response register (HDBAR + 64). This is a status flag indicating that software may read the response from the Immediate Response register. Immediate Command Busy (ICB) -- R/W. When this bit is read as 0, it indicates that a new command may be issued using the Immediate Command mechanism. When this bit transitions from 0-to-1 (via software writing a 1), the controller issues the command currently stored in the Immediate Command register to the codec over the link. When the corresponding response is latched into the Immediate Response register, the controller hardware sets the IRV flag and clears the ICB bit back to 0. NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism is operating, otherwise the responses conflict. This must be enforced by software. Attribute: Size: Description R/W, R/WC 16 bits 0 748 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.34 DPLBASE--DMA Position Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 70h Default Value: 00000000h Bit Attribute: Size: Description R/W, RO 32 bits 31:7 DMA Position Lower Base Address -- R/W. Lower 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. This same address is used by the Flush Control and must be programmed with a valid value before the Flush Control bit (HDBAR+08h:bit 1) is set. DMA Position Lower Base Unimplemented bits -- RO. Hardwired to 0 to force the 128byte buffer alignment for cache line write optimizations. DMA Position Buffer Enable -- R/W. 0 = Disable. 1 = Enable. The controller will write the DMA positions of each of the DMA engines to the buffer in the main memory periodically (typically once per frame). Software can use this value to dtermine what data in memory is valid data. 6:1 0 19.2.35 DPUBASE--DMA Position Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:HDBAR + 74h Default Value: 00000000h Bit 31:0 Attribute: Size: Description R/W 32 bits DMA Position Upper Base Address -- R/W. Upper 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. Intel (R) ICH7 Family Datasheet 749 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.36 SDCTL--Stream Descriptor Control Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 80h Input Stream[1]: HDBAR + A0h Input Stream[2]: HDBAR + C0h Input Stream[3]: HDBAR + E0h Output Stream[0]: HDBAR + 100h Output Stream[1]: HDBAR + 120h Output Stream[2]: HDBAR + 140h Output Stream[3]: HDBAR + 160h Default Value: Bit Attribute: R/W, RO 040000h Description Size: 24 bits Stream Number -- R/W. This value reflects the Tag associated with the data being transferred on the link. When data controlled by this descriptor is sent out over the link, it will have its stream number encoded on the SYNC signal. When an input stream is detected on any of the SDI signals that match this value, the data samples are loaded into FIFO associated with this descriptor. 23:20 Note that while a single SDI input may contain data from more than one stream number, two different SDI inputs may not be configured with the same stream number. 0000 = Reserved 0001 = Stream 1 ........ 1110 = Stream 14 1111 = Stream 15 19 18 (Desktop and Mobile Only) 18 (Ultra Mobile Only) 17:16 15:5 4 Bidirectional Direction Control -- RO. This bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. Traffic Priority -- RO. Hardwired to 1 indicating that all streams will use VC1 if it is enabled through the PCI Express* registers. Reserved Stripe Control -- RO. This bit is only meaningful for input streams; therefore, this bit is hardwired to 0. Reserved Descriptor Error Interrupt Enable -- R/W. 0 = Disable 1 = An interrupt is generated when the Descriptor Error Status bit is set. FIFO Error Interrupt Enable -- R/W. 0 = Disable. 1 = Enable. This bit controls whether the occurrence of a FIFO error (overrun for input or underrun for output) will cause an interrupt or not. If this bit is not set, bit 3 in the Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped. 3 750 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) Bit Description Interrupt on Completion Enable -- R/W. 0 = Disable. 1 = Enable. This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set, but the interrupt will not occur. Stream Run (RUN) -- R/W. 0 = Disable. The DMA engine associated with this input stream will be disabled. The hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine. 1 = Enable. The DMA engine associated with this input stream will be enabled to transfer data from the FIFO to the main memory. The SSYNC bit must also be cleared in order for the DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit is set. Stream Reset (SRST) -- R/W. 0 = Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers. 1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) and FIFO's for the corresponding stream are reset. After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset. The RUN bit must be cleared before SRST is asserted. 2 1 0 Intel (R) ICH7 Family Datasheet 751 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.37 SDSTS--Stream Descriptor Status Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 83h Input Stream[1]: HDBAR + A3h Input Stream[2]: HDBAR + C3h Input Stream[3]: HDBAR + E3h Output Stream[0]: HDBAR + 103h Output Stream[1]: HDBAR + 123h Output Stream[2]: HDBAR + 143h Output Stream[3]: HDBAR + 163h Default Value: Bit 7:6 Reserved. FIFO Ready (FIFORDY) -- RO. 5 For output streams, the controller hardware will set this bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the link. This bit defaults to 0 on reset because the FIFO is cleared on a reset. For input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the RUN bit to be set. Descriptor Error -- R/WC. 0 = No error detected. 1 = A serious error occurred during the fetch of a descriptor. This could be a result of a Master Abort, a parity or ECC error on the bus, or any other error which renders the current Buffer Descriptor or Buffer Descriptor list useless. This error is treated as a fatal stream error, as the stream cannot continue running. The RUN bit will be cleared and the stream will stop. NOTE: Software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. FIFO Error -- R/WC. The bit is cleared by writing a 1 to it. 0 = No error detected. 1 = FIFO error occurred. This bit is set even if an interrupt is not enabled. 3 For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set. When this happens, the FIFO pointers do not increment and the incoming data is not written into the FIFO, thereby being lost. For an output stream, this indicates a FIFO underrun when there are still buffers to send. The hardware should not transmit anything on the link for the associated stream if there is not valid data to send. Buffer Completion Interrupt Status -- R/WC. 2 0 = Last sample of a buffer has Not been processed as described below. 1 = Set to 1 by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion bit is set in the command byte of the buffer descriptor. It remains active until software clears it by writing a 1 to it. Reserved. Attribute: R/WC, RO 00h Description Size: 8 bits 4 1:0 752 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.38 SDLPIB--Stream Descriptor Link Position in Buffer Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 84h Input Stream[1]: HDBAR + A4h Input Stream[2]: HDBAR + C4h Input Stream[3]: HDBAR + E4h Output Stream[0]: HDBAR + 104h Output Stream[1]: HDBAR + 124h Output Stream[2]: HDBAR + 144h Output Stream[3]: HDBAR + 164h Default Value: Bit 31:0 Attribute:RO 00000000h Description Size: 32 bits Link Position in Buffer -- RO. Indicates the number of bytes that have been received off the link. This register will count from 0 to the value in the Cyclic Buffer Length register and then wrap to 0. 19.2.39 SDCBL--Stream Descriptor Cyclic Buffer Length Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 88h Input Stream[1]: HDBAR + A8h Input Stream[2]: HDBAR + C8h Input Stream[3]: HDBAR + E8h Output Stream[0]: HDBAR + 108h Output Stream[1]: HDBAR + 128h Output Stream[2]: HDBAR + 148h Output Stream[3]: HDBAR + 168h Default Value: Bit Attribute: R/W 00000000h Description Size: 32 bits Cyclic Buffer Length -- R/W. Indicates the number of bytes in the complete cyclic buffer. This register represents an integer number of samples. Link Position in Buffer will be reset when it reaches this value. 31:0 Software may only write to this register after Global Reset, Controller Reset, or Stream Reset has occurred. This value should be only modified when the RUN bit is 0. Once the RUN bit has been set to enable the engine, software must not write to this register until after the next reset is asserted, or transfer may be corrupted. Intel (R) ICH7 Family Datasheet 753 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.40 SDLVI--Stream Descriptor Last Valid Index Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Ch Input Stream[1]: HDBAR + ACh Input Stream[2]: HDBAR + CCh Input Stream[3]: HDBAR + ECh Output Stream[0]: HDBAR + 10Ch Output Stream[1]: HDBAR + 12Ch Output Stream[2]: HDBAR + 14Ch Output Stream[3]: HDBAR + 16Ch Default Value: Bit 15:8 Reserved. Last Valid Index -- R/W. The value written to this register indicates the index for the last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it will wrap back to the first descriptor in the list and continue processing. This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer descriptor list before DMA operations can begin). This value should only be modified when the RUN bit is 0. Attribute: R/W 0000h Description Size: 16 bits 7:0 19.2.41 SDFIFOW--Stream Descriptor FIFO Watermark Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 8Eh Input Stream[1]: HDBAR + AEh Input Stream[2]: HDBAR + CEh Input Stream[3]: HDBAR + EEh Output Stream[0]: HDBAR + 10Eh Output Stream[1]: HDBAR + 12Eh Output Stream[2]: HDBAR + 14Eh Output Stream[3]: HDBAR + 16Eh Default Value: Bit 15:3 Reserved. FIFO Watermark (FIFOW) -- R/W. This field indicates the minimum number of bytes accumulated/free in the FIFO before the controller will start a fetch/eviction of data. 010 = 8B 011 = 16B 100 = 32B (Default) 2:0 Others = Unsupported NOTES: 1. When the bit field is programmed to an unsupported size, the hardware sets itself to the default value. 2. Software must read the bit field to test if the value is supported after setting the bit field. Attribute: R/W 0004h Description Size: 16 bits 754 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.42 SDFIFOS--Stream Descriptor FIFO Size Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 90h Input Stream[1]: HDBAR + B0h Input Stream[2]: HDBAR + D0h Input Stream[3]: HDBAR + F0h Output Stream[0]: HDBAR + 110h Output Stream[1]: HDBAR + 130h Output Stream[2]: HDBAR + 150h Output Stream[3]: HDBAR + 170h Default Value: Input Stream: 0077h Output Stream: 00BFh Description Reserved. FIFO Size -- RO (Input stream), R/W (Output stream). This field indicates the maximum number of bytes that could be fetched by the controller at one time. This is the maximum number of bytes that may have been DMA'd into memory but not yet transmitted on the link, and is also the maximum possible value that the PICB count will increase by at one time. The value in this field is different for input and output streams. It is also dependent on the Bits per Samples setting for the corresponding stream. Following are the values read/written from/to this register for input and output streams, and for non-padded and padded bit formats: Output Stream R/W value: Value 0Fh = 16B 1Fh = 32B 3Fh = 64B 7Fh = 128B 7:0 BFh = 192B FFh = 256B Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, 20, 24, or 32 bit Output Streams 8, 16, or 32 bit Output Streams 20, 24 bit Output Streams Attribute: Input: RO Output: R/W Size: 16 bits Bit 15:8 NOTES: 1. All other values not listed are not supported. 2. When the output stream is programmed to an unsupported size, the hardware sets itself to the default value (BFh). 3. Software must read the bit field to test if the value is supported after setting the bit field. Input Stream RO value: Value 77h = 120B 9Fh = 160B Input Streams 8, 16, 32 bit Input Streams 20, 24 bit Input Streams NOTE: The default value is different for input and output streams, and reflects the default state of the BITS fields (in Stream Descriptor Format registers) for the corresponding stream. Intel (R) ICH7 Family Datasheet 755 Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.43 SDFMT--Stream Descriptor Format Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 92h Input Stream[1]: HDBAR + B2h Input Stream[2]: HDBAR + D2h Input Stream[3]: HDBAR + F2h Output Stream[0]: HDBAR + 112h Output Stream[1]: HDBAR + 132h Output Stream[2]: HDBAR + 152h Output Stream[3]: HDBAR + 172h Default Value: Bit 15 14 Reserved. Sample Base Rate -- R/W 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple -- R/W 13:11 000 = 48 kHz, 44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) Others = Reserved. Sample Base Rate Divisor -- R/W. 000 001 010 011 100 101 110 111 = = = = = = = = Divide Divide Divide Divide Divide Divide Divide Divide by by by by by by by by 1(48 kHz, 44.1 kHz) 2 (24 kHz, 22.05 kHz) 3 (16 kHz, 32 kHz) 4 (11.025 kHz) 5 (9.6 kHz) 6 (8 kHz) 7 8 (6 kHz) Attribute: R/W 0000h Description Size: 16 bits 10:8 7 Reserved. Bits per Sample (BITS) -- R/W. 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries 001 = 16 bits. The data will be packed in memory in 16-bit quantities on 16-bit boundaries 010 = 20 bits. The data will be packed in memory in 32-bit quantities on 32-bit boundaries 011 = 24 bits. The data will be packed in memory in 32-bit quantities on 32-bit boundaries 100 = 32 bits. The data will be packed in memory in 32-bit quantities on 32-bit boundaries Others = Reserved. Number of Channels (CHAN) -- R/W. Indicates number of channels in each frame of the stream. 6:4 3:0 0000 =1 0001 =2 ........ 1111 =16 756 Intel (R) ICH7 Family Datasheet Intel(R) High Definition Audio Controller Registers (D27:F0) 19.2.44 SDBDPL--Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 98h Input Stream[1]: HDBAR + B8h Input Stream[2]: HDBAR + D8h Input Stream[3]: HDBAR + F8h Output Stream[0]: HDBAR + 118h Output Stream[1]: HDBAR + 138h Output Stream[2]: HDBAR + 158h Output Stream[3]: HDBAR + 178h Default Value: Bit 31:7 6:0 Attribute: R/W,RO 00000000h Description Size: 32 bits Buffer Descriptor List Pointer Lower Base Address -- R/W. This field is the lower address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. Hardwired to 0 forcing alignment on 128-B boundaries. 19.2.45 SDBDPU--Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (Intel(R) High Definition Audio Controller--D27:F0) Memory Address:Input Stream[0]: HDBAR + 9Ch Input Stream[1]: HDBAR + BCh Input Stream[2]: HDBAR + DCh Input Stream[3]: HDBAR + FCh Output Stream[0]: HDBAR + 11Ch Output Stream[1]: HDBAR + 13Ch Output Stream[2]: HDBAR + 15Ch Output Stream[3]: HDBAR + 17Ch Default Value: Bit 31:0 Attribute: R/W 00000000h Description Size: 32 bits Buffer Descriptor List Pointer Upper Base Address -- R/W. This field is the upper 32-bit address of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be corrupted. Intel (R) ICH7 Family Datasheet 757 Intel(R) High Definition Audio Controller Registers (D27:F0) 758 Intel (R) ICH7 Family Datasheet High Precision Event Timer Registers 20 High Precision Event Timer Registers The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to directly access each register without having to use an index register. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors. There are four possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h., 4) FED0_4000h. The choice of address range will be selected by configuration bits in the High Precision Timer Configuration Register (Chipset Configuration Registers:Offset 3404h). Behavioral Rules: 1. Software must not attempt to read or write across register boundaries. For example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh. Any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. However, these accesses should not result in system hangs. 64bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. Software should not write to read-only registers. 3. Software should not expect any particular or consistent value when reading reserved registers or bits. 20.1 Memory Mapped Registers Table 20-1. Memory-Mapped Registers (Sheet 1 of 2) Offset 000-007h 008-00Fh 010-017h 018-01Fh 020-027h 028-0EFh 0F0-0F7h 0F8-0FFh 100-107h 108-10Fh 110-11Fh 120-127h 128-12Fh 130-13Fh Mnemonic GCAP_ID -- GEN_CONF -- GINTR_STA -- MAIN_CNT -- TIM0_CONF TIM0_COMP -- TIM1_CONF TIM1_COMP -- Register General Capabilities and Identification Reserved General Configuration Reserved General Interrupt Status Reserved Main Counter Value Reserved Timer 0 Configuration and Capabilities Timer 0 Comparator Value Reserved Timer 1 Configuration and Capabilities Timer 1 Comparator Value Reserved Default 0429B17F8 086A201h -- 0000h -- 00000000 00000000h -- N/A -- N/A N/A -- N/A N/A -- Type RO -- R/W -- R/WC, R/ W -- R/W -- R/W, RO R/W -- R/W, RO R/W -- Intel (R) ICH7 Family Datasheet 759 High Precision Event Timer Registers Table 20-1. Memory-Mapped Registers (Sheet 2 of 2) Offset 140-147h 148-14Fh 150-15Fh 160-3FFh Mnemonic TIM2_CONF TIM2_COMP -- -- Register Timer 2 Configuration and Capabilities Timer 2 Comparator Value Reserved Reserved Default N/A N/A -- -- Type R/W, RO R/W -- -- NOTES: 1. Reads to reserved registers or bits will return a value of 0. 2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 20.1.1 GCAP_ID--General Capabilities and Identification Register Address Offset: 00h Default Value: 0429B17F8086A201h Bit Attribute: Size: Description RO 64 bits 63:32 Main Counter Tick Period (COUNTER_CLK_PER_CAP) -- RO. This field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). This will return 0429B17Fh when read. This indicates a period of 69841279h fs (69.841279 ns). Vendor ID Capability (VENDOR_ID_CAP) -- RO. This is a 16-bit value assigned to Intel. Legacy Replacement Rout Capable (LEG_RT_CAP) -- RO. Hardwired to 1. Legacy Replacement Interrupt Rout option is supported. Reserved. This bit returns 0 when read. Counter Size Capability (COUNT_SIZE_CAP) -- RO. Hardwired to 1. Counter is 64-bit wide. Number of Timer Capability (NUM_TIM_CAP) -- RO. This field indicates the number of timers in this block. 02h = Three timers. Revision Identification (REV_ID) -- RO. This indicates which revision of the function is implemented. Default value will be 01h. 31:16 15 14 13 12:8 7:0 760 Intel (R) ICH7 Family Datasheet High Precision Event Timer Registers 20.1.2 GEN_CONF--General Configuration Register Address Offset: 010h Default Value: 00000000 00000000h Bit 63:2 Attribute: Size: Description R/W 64 bits Reserved. These bits return 0 when read. Legacy Replacement Rout (LEG_RT_CNF) -- R/W. If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the interrupts will be routed as follows: * * * * * * Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC Timer 2-n is routed as per the routing in the timer n config registers. If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC) will have no impact. If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers are used. This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy replacement routing. 1 Overall Enable (ENABLE_CNF) -- R/W. This bit must be set to enable any of the timers to generate interrupts. 0 = Disable. The main counter will halt (will not increment) and no interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1-to-0, the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear the interrupts. 1 = Enable. NOTE: This bit will default to 0. BIOS can set it to 1 or 0. 0 20.1.3 GINTR_STA--General Interrupt Status Register Address Offset: 020h Default Value: 00000000 00000000h Attribute: Size: Description Reserved. These bits will return 0 when read. Timer 2 Interrupt Active (T02_INT_STS) -- R/W. Same functionality as Timer 0. Timer 1 Interrupt Active (T01_INT_STS) -- R/W. Same functionality as Timer 0. Timer 0 Interrupt Active (T00_INT_STS) -- R/WC. The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) If set to level-triggered mode: 0 This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have no effect. If set to edge-triggered mode: This bit should be ignored by software. Software should always write 0 to this bit. NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes will have no effect. R/W, R/WC 64 bits . Bit 63:3 2 1 Intel (R) ICH7 Family Datasheet 761 High Precision Event Timer Registers 20.1.4 MAIN_CNT--Main Counter Value Register Address Offset: 0F0h Default Value: N/A Attribute: Size: Description Counter Value (COUNTER_VAL[63:0]) -- R/W. Reads return the current value of the counter. Writes load the new value to the counter. NOTES: 1. Writes to this register should only be done while the counter is halted. 2. Reads to this register return the current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. If 32-bit software attempts to read a 64-bit counter, it should first halt the counter. Since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. It is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. Reads to this register are monotonic. No two consecutive reads return the same value. The second of two reads always returns a larger value (unless the timer has rolled over to 0). R/W 64 bits . Bit 63:0 20.1.5 TIMn_CONF--Timer n Configuration and Capabilities Register Address Offset: Timer 0: Timer 1: Timer 2: Default Value: N/A 100-107h, 120-127h, 140-147h Attribute: Size: RO, R/W 64 bits Note: The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2. Bit 63:56 Description Reserved. These bits will return 0 when read. Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) -- RO. Timer 0, 1: Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and 23) have a value of 1. Writes will have no effect. 55:52, 43 Timer 2: Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have a value of 1. Writes will have no effect. NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. 51:44, 42:14 Reserved. These bits return 0 when read. 762 Intel (R) ICH7 Family Datasheet High Precision Event Timer Registers Bit Description Interrupt Rout (TIMERn_INT_ROUT_CNF) -- R/W. This 5-bit field indicates the routing for the interrupt to the I/O (x) APIC. Software writes to this field to select which interrupt in the I/O (x) will be used for this timer's interrupt. If the value is not supported by this particular timer, then the value read back will not match what is written. The software must only write valid values. NOTES: 1. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 2. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. The ICH7 logic does not check the validity of the value written. 3. Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. The ICH7 logic does not check the validity of the value written. Timer n 32-bit Mode (TIMERn_32MODE_CNF) -- R/W or RO. Software can set this bit to force a 64-bit timer to behave as a 32-bit timer. This is typically needed if software is not willing to halt the main counter to read or write a particular timer, and the software is not capable of atomic 64-bit operations to the timer. This bit is only relevant if the timer is operating in 64-bit mode in which case that timer can be forced to 32-bit mode by setting this bit. When Timer 0 is switched to 32-bit mode, the upper 32-bits are loaded with 0's which will remain when the timer is switched back to 64-bit mode. If the timer is not in 64-bit mode, then this bit will always be read as 0 and writes will have no effect. Timer 0: Timers 1, 2: Bit is read/write (default to 0). 0 = 64 bit; 1= 32 bit Hardwired to 0. Writes have no effect since these timers are 32-bit only. 13:9 8 7 Reserved. This bit returns 0 when read. Timer n Value Set (TIMERn_VAL_SET_CNF) -- R/W. Software uses this bit only for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set the timer's accumulator. Software does not have to write this bit back to 1 (it automatically clears). 6 Software should not write a 1 to this bit position if the timer is set to non-periodic mode. NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1 and 2. Timer n Size (TIMERn_SIZE_CAP) -- RO. This read only field indicates the size of the timer. Timer 0: Timers 1, 2: Value is 1 (64-bits). Value is 0 (32-bits). 5 4 Periodic Interrupt Capable (TIMERn_PER_INT_CAP) -- RO. If this bit is 1, the hardware supports a periodic mode for this timer's interrupt. Timer 0: Timers 1, 2: Timer 0: Timers 1, 2: Hardwired to 1 (supports the periodic interrupt). Hardwired to 0 (does not support periodic interrupt). Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to generate a periodic interrupt. Hardwired to 0. Writes have no effect. Timer n Type (TIMERn_TYPE_CNF) -- R/W or RO. 3 Intel (R) ICH7 Family Datasheet 763 High Precision Event Timer Registers Bit Description Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) -- R/W. This bit must be set to enable timer n to cause an interrupt when it times out. 2 0 = Enable. 1 = Disable (Default). The timer can still count and generate appropriate status bits, but will not cause an interrupt. Timer Interrupt Type (TIMERn_INT_TYPE_CNF) -- R/W. 0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If another interrupt occurs, another edge will be generated. 1 = The timer interrupt is level triggered. This means that a level-triggered interrupt is generated. The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will remain active. Reserved. These bits will return 0 when read. 1 0 NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any unimplemented registers will return an undetermined value. 20.1.6 TIMn_COMP--Timer n Comparator Value Register Address Offset: Timer 0: Timer 1: Timer 2: Attribute: R/W Default Value: N/A Bit 108h-10Fh, 128h-12Fh, 148h-14Fh Size: Description 64 bit Timer Compare Value -- R/W. Reads to this register return the current value of the comparator Timers 0, 1, or 2 are configured to non-periodic mode: Writes to this register load the value against which the main counter should be compared for this timer. * * * * When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). The value in this register does not change based on the interrupt being generated. When the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). After the main counter equals the value in this register, the value in this register is increased by the value last written to the register. For example, if the value written to the register is 00000123h, then 1. 2. 3. 4. * An interrupt will be generated when the main counter reaches 00000123h. The value in this register will then be adjusted by the hardware to 00000246h. Another interrupt will be generated when the main counter reaches 00000246h The value in this register will then be adjusted by the hardware to 00000369h Timer 0 is configured to periodic mode: 63:0 As each periodic interrupt occurs, the value in this register will increment. When the incremented value is greater than the maximum value possible for this register (FFFFFFFFh for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around through 0. For example, if the current value in a 32-bit timer is FFFF0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h Default value for each timer is all 1s for the bits that are implemented. For example, a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a default value of FFFFFFFFFFFFFFFFh. 764 Intel (R) ICH7 Family Datasheet Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) The Serial Peripheral Interface resides in memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. Note: All registers in this function (including memory-mapped registers) must be addressable in Byte, Word, and DWord quantities. The software must always make register accesses on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word accesses on word boundaries, etc.) In addition, the memory-mapped register space must not be accessed with the LOCK semantic exclusive-access mechanism. If software attempts exclusive-access mechanisms to the SPI memory-mapped space, the results are undefined. 21.1 Serial Peripheral Interface Memory Mapped Configuration Registers The SPI Host Interface registers are memory-mapped in the RCRB Chipset Register Space with a base address (SPIBAR) of 3020h and are located within the range of 3020h to 308Fh. The individual registers are then accessible at SPIBAR + Offset as indicated in the following table. These memory mapped registers must be accessed in byte, word, or DWord quantities. Table 21-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 1 of 2) SPIBAR + Offset 00h-01h 02h-03h 04h-07h 08h-0Fh 10h-17h 18h-1Fh 20h-27h 28h-2Fh 30h-37h 38h-3Fh 40h-47h Mnemonic SPIS SPIC SPIA SPID0 SPID1 SPID2 SPID3 SPID4 SPID5 SPID6 SPID7 SPI Status SPI Control SPI Address SPI Data 0 SPI Data 1 SPI Data 2 SPI Data 3 SPI Data 4 SPI Data 5 SPI Data 6 SPI Data 7 Register Name Default See Register Description 0001h 00000000h See Register Description 00000000 00000000h 00000000 00000000h 00000000 00000000h 00000000 00000000h 00000000 00000000h 00000000 00000000h 00000000 00000000h Access RO, R/WC, R/WLO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Intel (R) ICH7 Family Datasheet 765 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) Table 21-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 2 of 2) SPIBAR + Offset 50h-53h 54h-55h 56h-57h 58h-5Fh 60h-63h 64h-67h 68h-6Bh 6Ch-6Fh Mnemonic BBAR PREOP OPTYPE OPMENU PBR0 PBR1 PBR2 -- Register Name BIOS Base Address Configuration Prefix Opcode Configuration Opcode Type Configuration Opcode Menu Configuration Protected BIOS Range 0 Protected BIOS Range 1 Protected BIOS Range 2 Reserved Default 00000000h 0004h 0000h 00000000 00000005h 00000000h 00000000h 00000000h -- Access R/W R/W R/W R/W R/W R/W R/W -- 766 Intel (R) ICH7 Family Datasheet Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.1 SPIS--SPI Status Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 00h Default Value: See bit description Bit Attribute: Size: Description RO, R/WC, R/WLO 16 bits SPI Configuration Lock-Down -- R/WLO. 15 14:4 0 = No Lock-Down (Default) 1 = SPI Static Configuration information in offsets 50h through 6Fh can not be overwritten. Once set to 1, this bit can only be cleared by a hardware reset. Reserved Blocked Access Status -- R/WC. 0 = Not blocked (Default) 1 = Hardware sets this bit to 1 when an access is blocked from running on the SPI interface due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit is set for both programmed accesses and direct memory reads that get blocked. NOTE: This bit remains asserted until cleared by software writing a 1 or hardware reset. Cycle Done Status-- R/WC. 0 = Not done (Default) 1 = The Intel(R) ICH7 sets this bit to 1 when the SPI Cycle completes (i.e., SCIP bit is 0) after software sets the SCGO bit. 2 NOTE: This bit remains asserted until cleared by software writing a 1 or hardware reset. NOTE: Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access. NOTE: This bit gets set after the Status Register Polling sequence completes after reset deasserts. It is cleared before and during that sequence. SPI Access Grant -- RO. This bit is used by the software to know when the other SPI master will not be initiating any long transactions on the SPI bus. 1 0 = Default 1 = It is set by hardware in response to software setting the SPI Access Request bit and completing the Future Pending handshake with the LAN component. NOTE: This bit is cleared in response to software clearing the SPI Access Request bit. SPI Cycle In Progress (SCIP) -- RO. 0 = Cycle Not in Progress (Default) 1 = Hardware sets this bit when software sets the SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. This bit reports 1b during the Status Register Polling sequence after reset deasserts; it is cleared when that sequence completes. NOTE: Software must only program the next command when this bit is 0. 3 0 Intel (R) ICH7 Family Datasheet 767 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.2 SPIC--SPI Control Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 02h Default Value: 4005h Bit SPI SMI# Enable -- R/W. 15 0 = Disable. 1 = Enable. The SPI asserts an SMI# request when the Cycle Done Status bit is 1. DATA Cycle-- R/W. 14 0 = No data is delivered for this cycle, and the DBC and data fields themselves are don't cares. 1 = There is data that corresponds to this transaction. Data Byte Count (DBC) -- R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal) are any value from 0 to 63. The number of bytes transferred is the value of this field plus 1. For example, when this field is 000000b, then there is 1 byte to transfer and that 111111b means there are 64 bytes to transfer. 7 6:4 Reserved Cycle Opcode Pointer -- R/W. This field selects one of the programmed opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic Cycle Sequence, this determines the second command. Sequence Prefix Opcode Pointer -- R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. By making this programmable, the Intel(R) ICH7 supports flash devices that have different opcodes for enabling writes to the data space vs. status register 0 = A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. Atomic Cycle Sequence (ACS) -- R/W. 2 0 = No atomic cycle sequence. 1 = When set to 1 along with the SCGO assertion, the ICH7 will execute a sequence of commands on the SPI interface without allowing the LAN component to arbitrate and interleave cycles. SPI Cycle Go (SCGO) -- R/W. This bit always returns 0 on reads. 0 = SPI cycle Not started. 1 = A write to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this register. The "SPI Cycle in Progress" (SCIP) bit gets set by this action. NOTE: Writes to this bit while the Cycle In Progress bit is set are ignored. NOTE: Other bits in this register can be programmed for the same transaction when writing this bit to 1. SPI Access Request -- R/W. This bit is used by software to request that the other SPI master stop initiating long transactions on the SPI bus. 0 0 = No request. 1 = Request that the other SPI master stop initiating long transactions on the SPI bus. NOTE: This bit defaults to a 1 and must be cleared by BIOS after completing the accesses for the boot process. Attribute: Size: Description R/W 16 bits 13:8 3 1 768 Intel (R) ICH7 Family Datasheet Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.3 SPIA--SPI Address Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 04h Default Value: 00000000h Bit 31:24 23:0 Reserved SPI Cycle Address (SCA) -- R/W. This field is shifted out as the SPI Address (MSb first). Bits 23:0 correspond to Address bits 23:0. Attribute: Size: Description R/W 32 bits 21.1.4 SPID[N] --SPI Data N Register (SPI Memory Mapped Configuration Registers) Memory Address:SPI Data [0]: SPIBAR + SPI Data [1]: SPIBAR + SPI Data [2]: SPIBAR + SPI Data [3]: SPIBAR + SPI Data [4]: SPIBAR + SPI Data [5]: SPIBAR + SPI Data [6]: SPIBAR + SPI Data [7]: SPIBAR + Default Value: See Notes 1 and 2 below Bit 08hAttribute: 10h 18h 20h 28h 30h 38h 40h Size: Description R/W 64 bits SPI Cycle Data [N] (SCD[N]) -- R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. The SCD[N] register does not begin shifting until SPID[N-1] has completely shifted in/out. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle. 63:0 NOTE: The data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13...8-23-22-...16-31...24-39..32...etc. Bit 56 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always represents the value specified by the cycle address. NOTE: The data in this register may be modified by the hardware during any programmed SPI transaction. Direct Memory Reads do not modify the contents of this register. NOTES: 1. For SPI Data [7:1] Registers Only: Default value is 0000000000000000h. 2. For SPI Data 0 Register default value only: This register is initialized to 0 by the reset assertion. However, the least significant byte of this register is loaded with the first Status Register read of the Atomic Cycle Sequence that the hardware automatically runs out of reset. Therefore, bit 0 of this register can be read later to determine if the platform encountered the boundary case in which the SPI flash was busy with an internal instruction when the platform reset deasserted. Intel (R) ICH7 Family Datasheet 769 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.5 BBAR--BIOS Base Address Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 50h Default Value: 00000000h Bit 31:24 Reserved. Bottom of System Flash -- R/W. This field determines the bottom of the System BIOS. The Intel(R) ICH7 will not run programmed commands nor memory reads whose address field is less than this value. This field corresponds to bits 23:8 of the 3-byte address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential SPI address. 23:8 NOTE: Software must always program 1s into the upper, Don't Care, bits of this field based on the flash size. Hardware does not know the size of the flash array and relies upon the correct programming by software. The default value of 0000h results in all cycles allowed. NOTE: In the event that this value is programmed below some of the BIOS Memory segments, described above, this protection policy takes precedence. Reserved Attribute: Size: Description R/W 32 bits 7:0 NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 21.1.6 PREOP--Prefix Opcode Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 54h Default Value: 0004h Bit 15:8 7:0 Attribute: Size: Description R/W 16 bits Prefix Opcode 1-- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. Prefix Opcode 0 -- R/W. Software programs an SPI opcode into this field that is permitted to run as the first command in an atomic cycle sequence. NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 770 Intel (R) ICH7 Family Datasheet Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.7 OPTYPE--Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 56h Default Value: 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them. Therefore, any erase or write opcodes that do not use an address should be avoided (for example, "Chip Erase" and "Auto-Address Increment Byte Program") Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 Description Opcode Type 7 -- R/W. See the description for bits 1:0 Opcode Type 6 -- R/W. See the description for bits 1:0 Opcode Type 5 -- R/W. See the description for bits 1:0 Opcode Type 4 -- R/W. See the description for bits 1:0 Opcode Type 3 -- R/W. See the description for bits 1:0 Opcode Type 2 -- R/W. See the description for bits 1:0 Opcode Type 1 -- R/W. See the description for bits 1:0 Opcode Type 0 -- R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to, 1) know whether to use the address field and, 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two bits is: 00 = No address associated with this Opcode; Read cycle type 01 = No address associated with this Opcode; Write cycle type 10 = Address required; Read cycle type 11 = Address required; Write cycle type NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 1:0 Intel (R) ICH7 Family Datasheet 771 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) 21.1.8 OPMENU--Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address:SPIBAR + 58h Default Value: 0000000000000005h Attribute: Size: R/W 64 bits Eight entries are available in this register to give BIOS a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. This keeps the hardware flexible enough to operate with a wide variety of SPI devices. Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu. Malicious software could then perform writes and erases to the SPI flash without using the atomic cycle mechanism. This could cause functional failures in a shared flash environment. Write Enable opcodes should only be programmed in the Prefix Opcodes. Bit 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Description Allowable Opcode 7 -- R/W. See the description for bits 7:0 Allowable Opcode 6 -- R/W. See the description for bits 7:0 Allowable Opcode 5 -- R/W. See the description for bits 7:0 Allowable Opcode 4 -- R/W. See the description for bits 7:0 Allowable Opcode 3 -- R/W. See the description for bits 7:0 Allowable Opcode 2 -- R/W. See the description for bits 7:0 Allowable Opcode 1 -- R/W. See the description for bits 7:0 Allowable Opcode 0 -- R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 21.1.9 PBR[N]--Protected BIOS Range [N] (SPI Memory Mapped Configuration Registers) Memory Address:PBR[0]: SPIBAR + 60h PBR[1]: SPIBAR + 64h PBR[2]: SPIBAR + 68h Default Value: 00000000h Bit Write Protection Enable -- R/W. 31 30:24 0 = Disable. The base and limit fields are ignored when this bit is cleared. 1 = Enable. The Base and Limit fields in this register are valid. Reserved Protected Range Limit -- R/W. This field corresponds to SPI address bits 23:12 and specifies the upper limit of the protected range. 23:12 NOTE: Any address greater than the value programmed in this field is unaffected by this protected range. Protected Range Base -- R/W. This field corresponds to SPI address bits 23:12 and specifies the lower base of the protected range. 11:0 NOTE: Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Attribute: Size: Description R/W 32 bits NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 772 Intel (R) ICH7 Family Datasheet Ballout Definition 22 22.1 Ballout Definition This chapter contains the Intel(R) ICH7 family ballout information. Desktop, Mobile, and Digital Home Component Ballout Figure 22-1 and Figure 22-2 are the ballout map of the ICH7 Desktop, Mobile, and Digital Home components. These components are in a 652 BGA package. Table 22-1 is a BGA ball list, sorted alphabetically by signal name. Note: 1. -- Throughout this section, the symbol "" indicates a signal that is Reserved on the 82801GB ICH7 base component but is used by other ICH7 Desktop/Mobile/ Digital Home Family components. This pertains to the signals for PCI Express Ports 5 and 6; these signals are not on the ICH7 base and are reserved (Marked as "Reserved"). 2. -- Throughout this section, the symbol "" indicates a Digital Home Only signal. These signals are only on the 82801GDH ICH7DH. 3. * -- Throughout this section, the symbol "*" indicates a Mobile Only signal. These signals are only on the 82801GBM ICH7-M and 82801GHM ICH7-M DH. 4. ** -- Throughout this section, the symbol "**" indicates a Desktop Only signal (82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH). 5. NC = No Connect Intel (R) ICH7 Family Datasheet 773 Ballout Definition Figure 22-1. Desktop and Mobile Component Ballout (Topview-Left Side) 1 2 OC6# / GPIO30 CLK48 3 4 5 6 7 8 9 10 11 12 13 REQ4# / GPIO22 Vcc3_3 14 GNT4# / GPIO48 Vss A Vcc1_5_A PIRQA# OC7# / GPIO31 OC5# / GPIO29 OC0# Vss Vcc3_3 AD27 IRDY# AD26 PCICLK AD20 AD19 DEVSEL# B Vss PIRQB# PIRQD# AD29 Vcc3_3 Vss GPIO1 / REQ5# GPIO17 / GNT5# Vss GPIO4 / PIRQG# GPIO2 / PIRQE# AD25 SERR# Vss AD12 C VccUSBPLL Vss OC1# PIRQC# Vss AD28 PERR# Vcc3_3 AD17 C/BE1# AD13 AD9 D USBRBIAS USBRBIAS# OC3# OC2# AD31 REQ0# AD24 Vss AD18 C/BE2# Vss AD11 E Vss Vss VccSus3_3 Vss OC4# AD30 GNT0# GPIO3 / PIRQF# GPIO5 / PIRQH# Vcc1_5_A Vcc1_5_A VccSus1_05 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 AD23 PAR PLOCK# AD16 REQ3# AD10 F USBP0N USBP0P Vss Vss Vss V5REF_Sus Vcc3_3 AD22 AD21 Vss GNT3# TRDY# G Vss Vss USBP1P USBP1N Vss Vss Vss V5REF Vcc3_3 Vcc3_3 AD15 Vss H J K L M N P USBP2N Vss USBP4N VccSus3_3 USBP6N Vss SPI_ARB USBP2P Vss USBP4P VccSus3_3 USBP6P Vss SPI_MISO Vss USBP3P VccSus3_3 VccSus3_3 Vss USBP7P Vss Vss USBP3N VccSus3_3 USBP5N Vss USBP7N Vss Vss Vss VccSus3_3 USBP5P Vss Vss SPI_MOSI Vcc1_5_A Vcc1_5_A VccSus3_3 VccSus3_3 VccSus3_3 Vss SPI_CS# Vcc1_05 Vcc1_05 Vss Vcc1_05 Vcc1_05 Vss Vss Vss Vss Vss Vss Vss Vcc1_05 Vss Vss Vss R Vss SPI_CLK GPIO24 GPIO14 ACZ_RST# VccSus3_3 / ACZ_SYNC VccSusHDA* Vss Vcc1_5_A Vss Vss Vss Vss T ACZ_SDIN2 ACZ_SDIN0 GPIO34 / AZ_DOCK_ RST#* Vss VccSus3_3 / VccLAN3_3* EE_DOUT VccSus1_05 / VccLAN1_05* RTCX2 Vss ACZ_SDIN1 ACZ_SDOUT LAN_RXD2 Vcc1_05 Vss Vss Vss U ACZ_BIT_CLK LAN_ RSTSYNC Vss LAN_RXD0 Vcc3_3 / VccHDA* LAN_TXD0 Vcc1_05 Vss Vss Vss V VccSus3_3 / VccLAN3_3* EE_CS LAN_CLK LAN_RXD1 VccSus3_3 / LAN_TXD1 VccLAN3_3* VccRTC Vss LAN_TXD2 VccSus3_3 / VccLAN3_3* VccSus1_05 / VccLAN1_05* Vcc3_3 Vcc1_05 Vcc1_05 Vss Vcc1_05 W EE_DIN INTVRMEN Y EE_SHCLK Vss RSMRST# INTRUDER# LDRQ1# / GPIO23 LAD1 Vss SATA1RXP / Reserved* SATA1RXN / Reserved* Vcc1_5_A LAD3 AA Vss RTCRST# PWROK LAD0 AB AC RTCX1 CLK14 LFRAME# LDRQ0# Vss LAD2 Vss Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss SATA3RXN / Reserved* SATA3RXP / Reserved* Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss Vss Vcc3_3 DD7 DD10 DD5 Vss DD11 AD Vss VccSATAPLL Vss Vss Vcc1_5_A Vss Vss Vcc1_5_A Vss DD6 Vcc3_3 DD4 AE SATA_CLKP Vss SATA0RXP Vss Vcc1_5_A SATA2RXP Vss Vcc1_5_A Vss DD8 Vss DD1 AF SATA_CLKN Vss SATA0RXN Vss SATA1TXN / Reserved* SATA1TXP / Reserved* 4 Vcc1_5_A SATA2RXN Vss SATA3TXN / Reserved* SATA3TXP / Reserved* 8 Vcc1_5_A Vss DD9 DD3 DD12 AG Vss SATA0TXN Vss Vcc1_5_A SATA2TXN Vss Vcc1_5_A SATARBIASP Vss Vcc3_3 DD2 Vss AH Vss SATA0TXP Vss Vcc1_5_A SATA2TXP Vss Vcc1_5_A SATARBIASN Vcc3_3 VSS DD13 DD14 1 2 3 5 6 7 9 10 11 12 13 14 774 Intel (R) ICH7 Family Datasheet Ballout Definition Figure 22-2. Desktop and Mobile Component Ballout (Topview-Right Side) 15 16 17 18 19 20 21 EL_RSVD / GPIO26 EL_STATE0 / GPIO27 TP0 / BATLOW#* Vss 22 23 24 25 26 27 28 AD8 AD2 AD7 AD5 SPKR GPIO10 SYS_RST# Vss SMBALERT# / GPIO11 PWRBTN# VccSus3_3 SMLINK1 LINKALERT# SUS_STAT# RI# A C/BE0# Vcc3_3 Vss PCIRST# PME# Vss SMBDATA SLP_S3# SMLINK0 Vss Vcc3_3 Vss B C/BE3# REQ1# REQ2# AD1 LAN_RST# SUSCLK SMBCLK VccSus3_3 DMI_ZCOMP PLTRST# Vss VccSus1_05 C Vcc3_3 GNT1# GNT2# Vss VccSus3_3 GPIO25 VccSus3_3 SLP_S4# EL_STATE1 / GPIO28 Vcc1_5_B Vss DMI_IRCOMP Vcc1_5_B Vcc1_5_B Vcc1_5_B D Vss AD4 AD6 AD0 GPIO13 GPIO9 GPIO8 GPIO15 Vcc1_5_B Vcc1_5_B Vcc1_5_B PETp1 PETn1 E STOP# FRAME# Vcc1_5_A AD3 GPIO12 WAKE# TP3 SLP_S5# Vcc1_5_B PERp1 PERn1 Vss Vss F AD14 Vcc3_3 Vcc1_5_A Vss VccSus3_3 VccSus1_05 Vss Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp2 PETn2 G Vcc1_5_B Vcc1_5_B Vss PERp2 PERn2 Vss Vss H Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp3 PETn3 J Vcc1_5_B Vcc1_5_B Vss PERp3 PERn3 Vss Vss K Vss Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp4 PETn4 L Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss PERp4 PERn4 Vss PETp5 / Reserved Vss PETp6 / Reserved Vcc1_5_B Vss PETn5 / Reserved Vss PETn6 / Reserved Vcc1_5_B M Vss Vss Vss Vss Vcc1_5_B Vcc1_5_B Vss Vss PERp5 / Reserved Vcc1_5_B PERn6 / Reserved Vss Vss PERn5 / Reserved Vcc1_5_B N Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss P Vss Vss Vss Vss Vcc1_5_B Vcc1_5_B Vcc1_5_B PERp6 / Reserved Vss R Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vcc1_5_B T Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss DMI0TXP DMI0TXN U Vss Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_5_B Vcc1_5_B Vss DMI0RXP DMI0RXN Vss Vss V Vcc1_5_B Vcc1_5_B Vss Vss Vss DMI1TXP DMI1TXN W Vcc1_5_B Vcc1_5_B Vss DMI1RXP DMI1RXN Vss Vss Y Vcc1_5_B GPIO0 / BM_BUSY#* GPIO7 Vcc1_5_B Vss Vss Vss DMI2TXP DMI2TXN AA DD0 Vss Vcc1_5_A Vss GPIO33 / AZ_DOCK_EN#* Vss GPIO37 / SATA3GP** GPIO21 / SATA0GP Vcc3_3 GPIO36 / SATA2GP 19 Vcc3_3 GPIO18 / STP_PCI#* GPIO38 Vss Vcc1_5_B GPIO16 / DPRSLPVR* Vcc1_5_B Vss DMI2RXP DMI2RXN Vss Vss AB DD15 Vcc3_3 Vcc1_5_A GPIO6 Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B DMI3TXP DMI3TXN AC Vss DCS3# V5REF Vcc3_3 GPIO35 / VRMPWRGD SATACLKREQ# Vss GPIO20 / STPCPU# INIT3_3V# A20GATE Vss DMI3RXP DMI3RXN Vcc1_5_B Vcc1_5_B Vcc1_5_B AD DDREQ DCS1# DA1 Vss GPIO39 V_CPU_IO Vss TP1 / DPRSTP#* GPIO49/ CPUPWRGD NMI Vss V_CPU_IO DMI_CLKP DMI_CLKN AE DIOR# DDACK# DA2 SATALED# GPIO32 / CLKRUN#* GPIO19 / SATA1GP** 18 THRM# INIT# SMI# INTR THERMTRIP# Vss Vss AF Vcc3_3 IORDY Vss Vss IGNNE# RCIN# Vss TP2 / DPSLP#* 25 FERR# CPUSLP#**/ VccDMIPLL NC* Vss A20M# AG DIOW# IDEIRQ DA0 MCH_SYNC# SERIRQ STPCLK# Vss V_CPU_IO AH 15 16 17 20 21 22 23 24 26 27 28 Intel (R) ICH7 Family Datasheet 775 Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name A20GATE A20M# ACZ_BIT_CLK ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 ACZ_SDOUT ACZ_SYNC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 Ball # AE22 AH28 U1 R5 T2 T3 T1 T4 R6 E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# CLK14 CLK48 CPUSLP#** / NC* DA0 DA1 DA2 DCS1# DCS3# DD0 DD1 DD10 DD11 DD12 DD13 DD14 DD15 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DDACK# DDREQ DEVSEL# DIOR# DIOW# DMI_CLKN DMI_CLKP Ball # B6 E6 D6 B15 C12 D12 C15 AC1 B2 AG27 AH17 AE17 AF17 AE16 AD16 AB15 AE14 AB13 AC14 AF14 AH13 AH14 AC15 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AF16 AE15 A12 AF15 AH15 AE28 AE27 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name DMI_IRCOMP DMI_ZCOMP DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP EE_CS EE_DIN EE_DOUT EE_SHCLK EL_RSVD / GPIO26 EL_STATE0 / GPIO27 EL_STATE1 / GPIO28 FERR# FRAME# GNT0# GNT1# GNT2# GNT3# GNT4# / GPIO48 GPIO0 / BM_BUSY#* GPIO1 / REQ5# GPIO10 GPIO12 Ball # D25 C25 V26 V25 U28 U27 Y26 Y25 W28 W27 AB26 AB25 AA28 AA27 AD25 AD24 AC28 AC27 W1 W3 Y2 Y1 A21 B21 E23 AG26 F16 E7 D16 D17 F13 A14 AB18 C8 A20 F19 776 Intel (R) ICH7 Family Datasheet Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name GPIO13 GPIO14 GPIO15 GPIO16 / DPRSLPVR* GPIO17 / GNT5# GPIO18 / STP_PCI#* GPIO19 / SATA1GP** GPIO2/ PIRQE# GPIO20 / STPCPU# GPIO21 / SATA0GP GPIO24 GPIO25 GPIO3 / PIRQF# GPIO32 / CLKRUN#* GPIO33 / AZ_DOCK_EN#* GPIO34 / AZ_DOCK_RST#* GPIO35 / SATACLKREQ# GPIO36 / SATA2GP GPIO37 / SATA3GP** GPIO38 GPIO39 GPIO4 / PIRQG# GPIO49 / CPUPWRGD GPIO5 / PIRQH# GPIO6 GPIO7 GPIO8 GPIO9 IDEIRQ IGNNE# INIT# INIT3_3V# Ball # E19 R4 E22 AC22 D8 AC20 AH18 G8 AF21 AF19 R3 D20 F7 AG18 AC19 U2 AD21 AH19 AE19 AD20 AE20 F8 AG24 G7 AC21 AC18 E21 E20 AH16 AG22 AF22 AG21 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name INTR INTRUDER# INTVRMEN IORDY IRDY# LAD0 LAD1 LAD2 LAD3 LAN_CLK LAN_RST# LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LDRQ0# LDRQ1# / GPIO23 LFRAME# LINKALERT# MCH_SYNC# NMI OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31 PAR PCICLK PCIRST# PERn1 PERn2 PERn3 Ball # AF25 Y5 W4 AG16 A7 AA6 AB5 AC4 Y6 V3 C19 U3 U5 V4 T5 U7 V6 V7 AC3 AA5 AB3 A26 AH20 AH24 D3 C4 D5 D4 E5 C3 A2 B3 E10 A9 B18 F26 H26 K26 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name PERn4 PERn5 / Reserved PERn6 / Reserved PERp1 PERp2 PERp3 PERp4 PERp5 / Reserved PERp6 / Reserved PERR# PETn1 PETn2 PETn3 PETn4 PETn5 / Reserved PETn6 / Reserved PETp1 PETp2 PETp3 PETp4 PETp5 / Reserved PETp6 / Reserved PIRQA# PIRQB# PIRQC# PIRQD# PLOCK# PLTRST# PME# PWRBTN# PWROK RCIN# REQ0# Ball # M26 P26 T25 F25 H25 K25 M25 P25 T24 C9 E28 G28 J28 L28 N28 R28 E27 G27 J27 L27 N27 R27 A3 B4 C5 B5 E11 C26 B19 C23 AA4 AG23 D7 Intel (R) ICH7 Family Datasheet 777 Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name REQ1# REQ2# REQ3# REQ4# / GPIO22 RI# RSMRST# RTCRST# RTCX1 RTCX2 SATA_CLKN SATA_CLKP SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN / Reserved* SATA1RXP / Reserved* SATA1TXN / Reserved* SATA1TXP / Reserved* SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN / Reserved* SATA3RXP / Reserved* SATA3TXN / Reserved* SATA3TXP / Reserved* SATALED# SATARBIAS# SATARBIAS SERIRQ SERR# SLP_S3# Ball # C16 C17 E13 A13 A28 Y4 AA3 AB1 AB2 AF1 AE1 AF3 AE3 AG2 AH2 AE5 AD5 AG4 AH4 AF7 AE7 AG6 AH6 AD9 AE9 AG8 AH8 AF18 AH10 AG10 AH21 B10 B24 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name SLP_S4# SLP_S5# SMBALERT# / GPIO11 SMBCLK SMBDATA SMI# SMLINK0 SMLINK1 SPI_ARB SPI_CLK SPI_CS# SPI_MISO SPI_MOSI SPKR STOP# STPCLK# SUS_STAT# SUSCLK SYS_RST# THERMTRIP# THRM# TP0 / BATLOW#* TP1 / DPRSTP#* TP2 / DPSLP#* TP3 TRDY# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P Ball # D23 F22 B23 C22 B22 AF23 B25 A25 P1 R2 P6 P2 P5 A19 F15 AH22 A27 C20 A22 AF26 AF20 C21 AF24 AH25 F21 F14 F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name USBP6N USBP6P USBP7N USBP7P USBRBIAS USBRBIAS# V_CPU_IO V_CPU_IO V_CPU_IO V5REF V5REF V5REF_Sus Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Ball # M1 M2 N4 N3 D1 D2 AE23 AE26 AH26 G10 AD17 F6 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 A1 F17 G17 H6 H7 J6 778 Intel (R) ICH7 Family Datasheet Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Ball # J7 T7 AB7 AB8 AB9 AB10 AB17 AC6 AC7 AC8 AC10 AC17 AD6 AD10 AE6 AE10 AF5 AF6 AF9 AF10 AG5 AG9 AH5 AH9 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Ball # K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23 AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vcc1_5_B Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 / VccHDA* VccDMIPLL VccRTC VccSATAPLL VccSus1_05 VccSus1_05 VccSus1_05 VccSus1_05 / VccLAN1_05* VccSus1_05 / VccLAN1_05* VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 Ball # AD28 A5 B7 B13 B16 B27 C10 D15 F9 G11 G12 G16 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19 AH11 U6 AG28 W5 AD2 C28 G20 K7 Y7 AA2 A24 C24 D19 D22 E3 G19 Intel (R) ICH7 Family Datasheet 779 Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 / VccLAN3_3* VccSus3_3 / VccLAN3_3* VccSus3_3 / VccLAN3_3* VccSus3_3 / VccLAN3_3* VccSus3_3 / VccSusHDA* VccUSBPLL VRMPWRGD Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7 P7 V1 V5 W2 W7 R7 C1 AD22 A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 780 Intel (R) ICH7 Family Datasheet Ballout Definition Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # P14 P15 P16 P17 P24 P27 P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Ball # V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 Table 22-1. Desktop and Mobile Component Ballout by Signal Name Signal Name Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss WAKE# Ball # AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27 F20 Intel (R) ICH7 Family Datasheet 781 Ballout Definition 22.2 Ultra Mobile Component Ballout Figure 22-3 and Figure 22-4 show the ICH7-U ballout from the top of the package view. Table 22-2 lists the ballout arranged by signal name. Figure 22-3. Intel(R) ICH7-U Ballout (top view, left side) 1 A VSS PIRQG#/ GPIO4 PIRQF#/ GPIO3 OC3# 2 VCC3_3 3 GNT5#/ GPIO17 AD29 4 AD22 5 PAR 6 AD15 7 REQ5#/ GPIO1 VCC3_3 8 PLOCK# 9 TRDY# 10 SERR# 11 AD20 A B AD23 VSS RSVD VSS VSS PERR# AD18 VSS B C RSVD RSVD AD31 AD30 OC7#/ GPIO31 VCCAUSBPLL OC5#/ GPIO29 V5REF_SUS USBP1N USBP3N USBP7N RSVD ACZ_SDIN0 VSS ACZ_SDOUT VCC3_3 RSVD RTCX1 RSVD RSVD RSVD DD6 DD8 5 RSVD PIRQE#/ GPIO2 VSS OC6#/ GPIO30 OC4# VSS USBP3P VSS VCCSUS3_3 RSVD VCC1_5A VCC3_3 VSS VCCRTC RTCX2 RSVD RSVD RSVD VSS DD3 6 AD24 IRDY# V5REF1 VSS VCC3_3 C D VSS VCCSUS1_05 OC0# AD21 PIRQH#/ GPIO5 OC1# OC2# AD28 AD25 VCC3_3 AD16 D E VSS VCCSUS3_3 CLK48 VSS VSS GNT3# AD26 PCICLK E F G H J K L M N P R T U V W Y AA AB USBP0P VSS USBP4P VSS USBP6P RSVD RSVD RSVD RSVD RSVD RSVD RSVD PWROK CLK14 LFRAME# LAD3 VSS 1 USBP0N USBP2P USBP4N USBP5P USBP6N RSVD ACZ_RST# ACZ_SDIN1 ACZ_SYNC RSVD RSVD RSVD RSMRST# VSS LAD1 RSVD RSVD 2 USBRBIAS# USBP2N VSS USBP5N VSS RSVD GPIO14 VSS RSVD RSVD RSVD RSVD LAD0 LAD2 RSVD RSVD RSVD 3 USBRBIAS VSS USBP1P VSS USBP7P RSVD VCCSUSHDA VCCHDA ACZ_BIT_CLK NC VSS INTRUDER# RSVD RSVD RSVD RSVD RSVD 4 RSVD AD27 AD17 VSS F G VCC1_5A VCC1_5A VCC1_5A VSS VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 RSVD RTEST# RSVD RSVD DD10 DD9 DD14 7 VSS RSVD VSS DD7 DD13 DD4 8 VCC1_5A VCC1_5A VSS VSS VSS VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VSS VSS VSS VSS VSS VSS VSS VSS VCC1_05 VCC1_05 VSS VSS VSS VSS VCC1_05 VCC1_05 H J K L M N P R T RSVD DD5 DD2 VCC3_3 VSS DD11 9 RSVD VSS DD1 DD12 DDREQ DIOR# 10 VSS VCC3_3 DD15 DIOW# IDEIRQ DD0 11 U V W Y AA AB 782 Intel (R) ICH7 Family Datasheet Ballout Definition Figure 22-4. Intel(R) ICH7-U Ballout (top view, right side) 12 A B C D E F G H J K L M N P R T U V W Y AA AB VCC1_5A VSS IORDY V5REF2 VSS DCS1# 12 VCC1_5A VCC3_3 DDACK# DA2 VCC3_3 DA1 13 VSS VSS DCS3# CLKRUN# VSS GPIO7 14 VCC3_3 DA0 RSVD RSVD THRM# RSVD 15 VSS VSS VSS VSS VSS VSS VSS VCC1_05 VCC1_5A VSS VSS VSS VSS VSS VCC1_05 VCC1_05 VCC1_5A VSS VCC1_05 VSS VCC1_05 VSS VSS VCC1_05 VCCSUS3_3 VSS VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VSS RSVD BMBUSY#/ GPIO0 SERIRQ RCIN# VSS RSVD 16 AD14 AD12 C/BE#_2 AD19 C/BE#_1 REQ#_3 13 VSS AD11 AD13 VSS AD10 AD9 14 REQ4#/ GPIO22 FRAME# STOP# DEVSEL# AD8 VSS 15 GNT4#/ GPIO48 VSS C/BE#_3 VCC3_3 AD7 AD3 16 C/BE#_0 AD6 AD5 VSS AD4 LAN_RST# PCIRST# 17 RSVD PME# RSVD AD2 RSVD SMBDATA RSVD RSVD PLTRST# VSS VCC1_5B VCC1_5B VCC1_5B VCC1_5B VCC1_5B VSS RSVD MCH_SYNC# VSS VCC3_3 A20GATE STPPCI#/ GPIO18 17 18 VCC3_3 VSS GPIO9 BATLOW# RSVD GPIO8 RSVD VSS VSS VSS VCC1_5B VSS VSS VSS VCC1_5B VSS VCCDMIPLL VSS V_CPU_IO VSS VSS RSVD 18 19 AD1 RSVD RSVD PWRBTN# VSS GPIO15 SLP_S5# RSVD RSVD VSS DMI_ZCOMP VSS DMI0RXP VSS DMI1RXP VSS VSS V_CPU_IO A20M# CPUSLP# V_CPU_IO GPIO6 19 20 AD0 GPIO12 VSS RSVD SMBCLK SMBALERT#/ GPIO11 VCCSUS1_05 VSS RSVD VSS DMI_IRCOMP VSS DMI0RXN VSS DMI1RXN VSS STPCLK# THERMTRIP# DPRSTP# SMI# NMI STPCPU#/ GPIO20 20 21 SPKR VSS SUSCLK SYS_RST# WAKE# SLP_S3# VSS VCC3_3 VSS RSVD VSS DMI0TXP VSS DMI1TXP VSS DMI_CLKP VSS FERR# DPSLP# CPUPWRGD/ GPIO49 VSS DPRSLPVR/ GPIO16 21 22 VSS GPIO10 RSVD GPIO13 VSS SLP_S4# SUS_STAT# VSS VSS RSVD VSS DMI0TXN VSS DMI1TXN VSS DMI_CLKN VSS INTR IGNNE# INIT# V_CPU_IO VRMPWRGD 22 A B C D E F G H J K L M N P R T U V W Y AA AB Intel (R) ICH7 Family Datasheet 783 Ballout Definition Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name A20GATE A20M# ACZ_BIT_CLK ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDOUT ACZ_SYNC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 Ball # AA17 W19 P4 M2 M5 N2 P5 P2 A20 A19 D17 F15 E16 C16 B16 E15 E14 F13 E13 B13 B12 C13 A12 A6 D11 F10 B10 D12 A11 D7 A4 B2 C7 D9 E10 F9 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name AD28 AD29 AD30 AD31 BATLOW# BMBUSY#/ GPIO0 C/BE#_0 C/BE#_1 C/BE#_2 C/BE#_3 CLK14 CLK48 CLKRUN# CPUPWRGD/ GPIO49 CPUSLP# DA0 DA1 DA2 DCS1# DCS3# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 Ball # D8 B3 C5 C4 D18 V16 A16 E12 C12 C15 W1 E3 Y14 Y21 Y19 V15 AB13 Y13 AB12 W14 AB11 W10 W9 AB6 AB8 V9 AA5 Y8 AB5 AA7 Y7 AB9 Y10 AA8 AB7 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name DD15 DDACK# DDREQ DEVSEL# DIOR# DIOW# DMI_CLKN DMI_CLKP DMI_IRCOMP DMI_ZCOMP DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DPRSLPVR/ GPIO16 DPRSTP# DPSLP# FERR# FRAME# GNT3# GNT4#/ GPIO48 GNT5#/ GPIO17 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 IDEIRQ Ball # W11 W13 AA10 D14 AB10 Y11 T22 T21 L20 L19 N20 N19 M22 M21 R20 R19 P22 P21 AB21 W20 W21 V21 B14 E9 A15 A3 AB19 AB14 F18 C18 B22 B20 D22 M3 F19 AA11 784 Intel (R) ICH7 Family Datasheet Ballout Definition Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name IGNNE# INIT# INTR INTRUDER# IORDY IRDY# LAD0 LAD1 LAD2 LAD3 LAN_RST# LFRAME# MCH_SYNC# NC NMI OC0# OC1# OC2# OC3# OC4# OC5#/ GPIO29 OC6#/ GPIO30 OC7#/ GPIO31 PAR PCICLK PCIRST# PERR# PIRQE#/ GPIO2 PIRQF#/ GPIO3 PIRQG#/ GPIO4 PIRQH#/ GPIO5 PLOCK# PLTRST# PME# PWRBTN# PWROK Ball # W22 Y22 V22 U4 W12 C8 V3 Y2 W3 AA1 F16 Y1 V17 R4 AA20 D4 F7 G7 D1 G6 F5 F6 D5 A5 E11 G16 B9 D6 C1 B1 E7 A8 J17 B17 D19 V1 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name RCIN# REQ#_3 REQ4#/ GPIO22 REQ5#/ GPIO1 RSMRST# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Ball # Y16 F12 A14 A7 V2 A17 AA2 AA3 AA4 AB15 AB16 AB18 AB2 AB3 AB4 B19 B5 C17 C19 C2 C22 C3 C6 D20 E17 E18 F8 G17 G18 H17 H19 J19 J20 K21 K22 L1 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Ball # L2 L3 L4 L5 M1 M6 N1 P1 P3 R1 R2 R3 T1 T2 T3 T5 T7 U1 U10 U16 U17 U2 U3 U9 V4 V5 V6 V7 V8 W15 W4 W5 W6 W7 Y15 Y3 Intel (R) ICH7 Family Datasheet 785 Ballout Definition Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name RSVD RSVD RSVD RTCX1 RTCX2 RTEST# SERIRQ SERR# SLP_S3# SLP_S4# SLP_S5# SMBALERT#/ GPIO11 SMBCLK SMBDATA SMI# SPKR STOP# STPCLK# STPCPU#/ GPIO20 STPPCI#/ GPIO18 SUS_STAT# SUSCLK SYS_RST# THERMTRIP# THRM# TRDY# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P Ball # Y4 Y5 Y6 U5 U6 U7 W16 A10 F21 F22 G19 F20 E20 F17 Y20 A21 C14 U20 AB20 AB17 G22 C21 D21 V20 AA15 A9 F2 F1 H5 H4 G3 G2 J5 J6 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS USBRBIAS# V_CPU_IO V_CPU_IO V_CPU_IO V_CPU_IO V5REF_SUS V5REF1 V5REF2 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_5A VCC1_5A VCC1_5A Ball # H2 H1 J3 J2 K2 K1 K5 K4 F4 F3 AA19 AA22 V19 W18 G5 C9 Y12 H11 J11 K14 K15 L15 M14 M15 N15 P11 P13 P15 R11 R12 R13 R14 R15 H13 H14 H8 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name VCC1_5A VCC1_5A VCC1_5A VCC1_5A VCC1_5A VCC1_5A VCC1_5A VCC1_5B VCC1_5B VCC1_5B VCC1_5B VCC1_5B VCC1_5B VCC1_5B VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCCAUSBPLL VCCDMIPLL VCCHDA VCCRTC VCCSUS1_05 VCCSUS1_05 VCCSUS3_3 Ball # H9 J8 J9 K8 N6 U12 U13 L17 L18 M17 N17 P17 R17 R18 A18 A2 AA13 B7 C11 D10 D15 H21 P6 R5 U15 V11 V13 Y17 Y9 E5 U18 N4 T6 D3 G20 E2 786 Intel (R) ICH7 Family Datasheet Ballout Definition Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUSHDA VRMPWRGD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # H15 L6 M8 N8 N9 P8 P9 R8 R9 M4 AB22 A1 A13 A22 AA12 AA14 AA16 AA18 AA21 AA6 AA9 AB1 B11 B15 B18 B21 B4 B6 B8 C10 C20 D13 D16 D2 E1 E19 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # E22 E4 E6 E8 F11 F14 G1 G21 G4 H10 H12 H18 H20 H22 H3 H6 J1 J10 J12 J13 J14 J15 J18 J21 J22 J4 K10 K11 K12 K13 K17 K18 K19 K20 K3 K6 Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # K9 L10 L11 L12 L13 L14 L21 L22 L8 L9 M10 M11 M12 M13 M18 M19 M20 M9 N10 N11 N12 N13 N14 N18 N21 N22 N3 N5 P10 P12 P14 P18 P19 P20 R10 R21 Intel (R) ICH7 Family Datasheet 787 Ballout Definition Table 22-2. Intel(R) ICH7-U Ballout by Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS WAKE# Ball # R22 R6 T16 T17 T18 T19 T20 T4 U11 U14 U19 U21 U22 U8 V10 V12 V14 V18 W17 W2 W8 Y18 E21 788 Intel (R) ICH7 Family Datasheet Electrical Characteristics 23 Electrical Characteristics This chapter contains the DC and AC characteristics for the ICH7. AC timing diagrams are included. 23.1 Thermal Specifications Refer to the Intel(R) I/O Controller Hub (ICH7) Thermal Design Guidelines for ICH7 thermal information. 23.2 Absolute Maximum Ratings Table 23-1. Intel(R) ICH7 Absolute Maximum Ratings Parameter Voltage on any 3.3 V Pin with respect to Ground Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF=5 V) 1.05 V Supply Voltage with respect to VSS 1.5 V Supply Voltage with respect to VSS 3.3 V Supply Voltage with respect to VSS 5.0 V Supply Voltage with respect to VSS V_CPU_IO Supply Voltage with respect to VSS Maximum Limits -0.5 to Vcc3_3 + 0.5 V -0.5 to V5REF + 0.5 V -0.5 to 2.1 V -0.5 to 2.1 V -0.5 to 4.6 V -0.5 to 5.5 V -0.5 to 2.1 V Intel (R) ICH7 Family Datasheet 789 Electrical Characteristics 23.3 DC Characteristics Table 23-2. DC Current Characteristics Power Plane Symbol Vcc1_05 VccSus1_05 Vcc1_5_A 1 1 Maximum Power Consumption S0 0.86 A See Note 1.01 A 0.77 A 0.33 A 1 S3COLD NA NA NA NA NA 30 mA NA NA 10 mA NA NA NA NA S4/S5 NA NA NA NA NA 30 mA NA NA 10 mA NA NA NA NA G3 NA NA NA NA NA NA 6 uA NA NA NA NA NA NA Vcc1_5_B Vcc3_3 VccSus3_3 VccRTC 1,2 52 mA NA 6 mA 10 mA 14 mA 10 mA 50 mA 50 mA 3 V5REF V5REF_Sus V_CPU_IO VccUSBPLL VccDMIPLL VccSATAPLL NOTES: 1. Due to the integrated 1.05 V voltage regulator on the ICH7, VccSus1_05 is included in the Vcc1_05 rail during the S0-S1 states and in the VccSus3_3 rail during the S3-S5 states. 2. VccSus3_3 assumes that the 8 high-speed USB 2.0 devices are connected to the ICH7's root ports. 3. Icc (RTC) data is estimated with VccRTC at 3.0 V while the system is in a mechanical off (G3) state at room temperature. Only the G3 state of this rail is shown to provide an estimate of battery life. 790 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-3. DC Current Characteristics (Mobile/Ultra Mobile Only) Power Plane Symbol Vcc1_05 1,2 3 3 Maximum Power Consumption S0 0.94 A 17 mA 30 mA 0.64 A 0.77 A 0.27 A 56 mA 92 mA 45 mA 10 mA 17 mA 40 mA NA 6 mA 10 mA 14 mA 10 mA 50 mA 50 mA S3COLD NA 17 mA 3 mA NA NA NA NA NA 21 mA 2 mA 2 mA 7 mA NA NA 10 mA NA NA NA NA S4/S5 NA 17 mA 3 mA NA NA NA NA NA 21 mA 2 mA 2 mA 7 mA NA NA 10 mA NA NA NA NA G3 NA NA NA NA NA NA NA NA NA NA NA NA 6 uA NA NA NA NA NA NA VccSus1_05 VccLAN1_05 Vcc1_5_A Vcc1_5_B Vcc3_3 VccHDA 4 VccHDA5 VccSus3_3 1,6 4 5 VccSusHDA VccSusHDA 7 VccLAN3_32 VccRTC V5REF V5REF_Sus V_CPU_IO VccUSBPLL VccDMIPLL VccSATAPLL NOTES: 1. When the internal VccSus1_05 voltage regulator on the ICH7-M/ICH7-U is enabled, VccSus1_05 is included in the Vcc1_05 rail during the S0 state and in the VccSus3_3 rail during the S3 - S5 states. There is a negligible change in Vcc1_05 and VccSus3_3 maximum power consumption when internal VccSus1_05 VR is disabled. 2. When the internal VccSus1_05 voltage regulator on the ICH7-M/ICH7-U is enabled, VccLAN1_05 is included in the Vcc1_05 rail during the S0 state and in the VccLAN3_3 rail during the S3 - S5 states. There is a negligible change in Vcc1_05 and VccLAN3_3 maximum power consumption when internal VccSus1_05 VR is disabled. 3. Integrated VccSus1_05 VR disabled. 4. VccHDA and VccSusHDA at 3.3 V. 5. VccHDA and VccSusHDA at 1.5 V. 6. VccSus3_3 assumes that the 8 high-speed USB 2.0 devices are connected to the ICH7's root ports. 7. Icc (RTC) data is estimated with VccRTC at 3.0 V while the system is in a mechanical off (G3) state at room temperature. Only the G3 state of this rail is shown to provide an estimate of battery life. Intel (R) ICH7 Family Datasheet 791 Electrical Characteristics Table 23-4. DC Characteristic Input Signal Association (Sheet 1 of 2) Symbol VIH1/VIL1 (5V Tolerant) VIH2/VIL2 (5V Tolerant) Clock Signals: CLK14, CLK48 Power Management Signals: MCH_SYNC#, THRM#, VRMPWRGD Associated Signals PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, REQ4#/GPIO22, REQ5#/GPIO1, SERR#, STOP#, TRDY# Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]#/GPIO[5:2] Interrupt Signals: IDEIRQ SATA Signals: Desktop Only: SATAGP[3:0]/GPIO[37,36,19,21], SATACLKREQ#/GPIO35 Mobile Only: SATAGP[2,0]/GPIO[36,21], SATACLKREQ#/GPIO35 VIH3/VIL3 AC '97/Intel(R) High Definition Audio Signals: Mobile Only: AZ_DOCK_EN#/GPIO33 GPIO Signals: Desktop Only: GPIO[39, 38, 33, 32, 20, 18, 16, 7, 6] Mobile/Ultra Mobile Only: GPIO[39:37, 19, 7, 6] Strap Signals: SPKR, SATALED# (Strap purposes only) Clock Signals: PCICLK LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LDRQ0#, LDRQ1#/ GPIO23 Power Management Signals: Desktop Only: LAN_RST# Mobile/Ultra Mobile Only: BM_BUSY#/GPIO0, CLKRUN#, LAN_RST# VIH4/VIL4 PCI Signals: PME# Interrupt Signals: SERIRQ CPU Signals: A20GATE, RCIN# USB Signals: OC[4:0]#, OC[7:5]#/GPIO[31:29] GPIO Signals: GNT4#/GPIO48, GNT5#/GPIO17, GPIO0 SPI Signals: Desktop and Mobile Only: SPI_CS#, SPI_MISO, SPI_ARB SMBus Signals: SMBCLK, SMBDATA VIH5/VIL5 System Management Signals: SMBALERT#/GPIO11 Desktop and Mobile Only: SMLINK[1:0] LAN Signals: LAN_CLK, LAN_RXD[2:0] VIH6/VIL6 EEPROM Signals: EE_DIN Strap Signals: EE_CS, EE_DOUT (Strap purposes only) VIH7/VIL7 VIMIN8/VIMAX8 VIH9/VIL9 VIMIN10/VIMAX10 Processor Signals: FERR#, THRMTRIP# GPIO Signals: GPIO49/CPUPWRGD PCI Express* Data RX Signals: PER[p,n][6:1] (Desktop and Mobile Only) Real Time Clock Signals: RTCX1 SATA Signals: Desktop Only: SATA[3:0]RX[P,N] Mobile Only: SATA[2,0]RX[P,N] 792 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-4. DC Characteristic Input Signal Association (Sheet 2 of 2) Symbol (R) Associated Signals AC '97/Intel High Definition Audio Signals: ACZ_SDIN[2:0], Mobile Only: AZ_DOCK_RST#/GPIO34 AC `97 Signals: ACZ_BIT_CLK Strap Signals: ACZ_SDOUT, ACZ_SYNC (Strap purposes only) GPIO Signals: GPIO34 (Desktop Only) NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode (Mobile/Ultra Mobile Only) VIH11/VIL11 VIH12/VIL12/ Vcross(abs) Clock Signals: DMI_CLKN, DMI_CLKP, SATA_CLKN, SATA_CLKP Power Management Signals: Desktop Only: PWRBTN#, RI#, SYS_RESET#, WAKE# Mobile/Ultra Mobile Only: BATLOW#, PWRBTN#, RI#, SYS_RESET#, WAKE# VIH13/VIL13 System Management Signal: LINKALERT# Intel(R) Quick Resume Technology Signals: EL_STATE[1:0]/GPIO[28:27], EL_RSVD/GPIO26 (ICH7DH Only) GPIO Signals: GPIO[28:26, 25:24, 15:12, 10:8] Other Signals: TP0 Power Management Signals: PWROK, RSMRST#, RTCRST# System Management Signals: INTRUDER# Other Signals: INTVRMEN (Desktop and Mobile Only) IDE Signals: DD[15:0], DDREQ, IORDY, For Ultra DMA Mode 4 and lower these signals follow the DC characteristics for VIH2/VIL2 USB Signals: USBP[7:0][P,N] (Low-speed and Full-speed) VIH14/VIL14 VIH15/VIL15 V+/V-/VHYS/ VTHRAVG/VRING (5V Tolerant) VDI / VCM / VSE (5V Tolerant) VHSSQ / VHSDSC / (5V Tolerant) VIH_HDA / VIL_HDA (Mobile/Ultra Mobile Only) VHSCM USB Signals: USBP[7:0][P,N] (in High-speed Mode) Intel(R) High Definition Audio Signals: ACZ_SDIN[2:0], AZ_DOCK_RST#/GPIO34 NOTE: Only applies when running in Low Voltage Mode (1.5 V) Intel (R) ICH7 Family Datasheet 793 Electrical Characteristics Table 23-5. DC Input Characteristics (Sheet 1 of 2) Symbol VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VIL4 VIH4 VIL5 VIH5 VIL6 VIH6 VIL7 VIH7 VIMIN8 VIMAX8 VIL9 VIH9 VIMIN10 VIMAX10 VIMIN10 VIMAX10 VIL11 VIH11 VIL12 VIH12 VIL13 VIH13 VIL14 VIH14 VIL15 VIH15 Vcross(abs) V+ Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Minimum Input Voltage Maximum Input Voltage Input Low Voltage Input High Voltage Minimum Input Voltage Maximum Input Voltage Minimum Input Voltage Maximum Input Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Absolute Crossing Point Low to high input threshold 275 750 Min -0.5 0.5(Vcc3_3) -0.5 2.0 -0.5 2.0 -0.5 0.5(Vcc3_3) -0.5 2.1 -0.5 0.6(Vcc3_3) Max 0.3(Vcc3_3) V5REF + 0.5 0.8 V5REF + 0.5 0.8 Vcc3_3 + 0.5 0.3(Vcc3_3) Vcc3_3 + 0.5 0.8 VccSus3_3 + 0.5 0.3(Vcc3_3) Vcc3_3 + 0.5 0.58(V_CPU_IO) V_CPU_IO + 0.5 Unit V V V V V V V V V V V V V V mVdiff p-p 1200 mVdiff p-p V V mVdiff p-p 600 mVdiff p-p mVdiff p-p mVdiff p-p V V V V V V V V V V V V 5 4 4 2 1 Notes -0.5 0.73(V_CPU_IO) 175 1 -0.5 0.40 325 0.10 1.2 2 3 3 -0.5 0.65(Vcc3_3) -0.150 0.660 0.35(Vcc3_3) Vcc3_3 + 0.5 0.150 0.850 0.8 VccSus3_3 + 0.5 0.78 VccRTC + 0.5 0.65 VccRTC + 0.5 0.550 2.0 -0.5 2.0 -0.5 2.0 -0.5 2.0 0.250 1.5 794 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-5. DC Input Characteristics (Sheet 2 of 2) Symbol V- Parameter High to low input threshold Difference between input thresholds: (V+current value) - (V- current value) Average of thresholds: VTHRAVG ((V+current value) + (V- current value))/2 AC Voltage at recipient connector Differential Input Sensitivity Differential Common Mode Range Single-Ended Receiver Threshold HS Squelch Detection Threshold HS Disconnect Detection Threshold HS Data Signaling Common Mode Voltage Range HS Squelch detection threshold HS disconnect detection threshold HS data signaling common mode voltage range 1.3 1.7 V Min 1.0 Max 1.5 Unit V Notes 5 VHYS 320 mV 5 5 VRING VDI VCM VSE VHSSQ VHSDSC VHSCM VHSSQ VHSDSC VHSCM VIL_HDA (Mobile/ Ultra Mobile Only) VIH_HDA (Mobile/ Ultra Mobile Only) NOTES: -1 0.2 0.8 0.8 100 525 6 V V 5,6 7,8 2.5 2.0 150 625 500 150 625 500 V V mV mV mV mV mV mV 8,9 8 8 8 -50 100 525 8 8 8 -50 8 Input Low Voltage 0.4(Vcc_HDA) V Input High Voltage 0.6(Vcc_HDA) V 1. PCI Express mVdiff p-p = |PETp[x] - PETn[x]| 2. Applicable only when SATA port signaling rate is 1.5 Gb/s: SATA Vdiff, tx (VIMAX/MIN10) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = |SATA[x]TXP/RXP - SATA[x]TXN/RXN| Intel (R) ICH7 Family Datasheet 795 Electrical Characteristics 3. Applicable only when SATA port signaling rate is 3 Gb/s: SATA Vdiff, tx (VIMAX/MIN10) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = |SATA[x]TXP/RXP - SATA[x]TXN/RXN| 4. VccRTC is the voltage applied to the VccRTC well of the ICH7. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. 5. Applies to Ultra DMA Modes greater than Ultra DMA Mode 4 6. This is an AC Characteristic that represents transient values for these signals 7. VDI = | USBPx[P] - USBPx[N] 8. Applies to High-speed USB 2.0 9. Includes VDI range Table 23-6. DC Characteristic Output Signal Association (Sheet 1 of 2) Symbol VOH1/VOL1 Associated Signals IDE Signals: DA[2:0], DCS[3,1]#, DDACK#, DD[15:0], DIOR#, DIOW# Processor Signals: Desktop Only: A20M#, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK#, CPUPWRGD/GPIO49 Mobile/Ultra Mobile Only: A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK#, CPUPWRGD/GPIO49 PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, SERR#, STOP#, TRDY# AC '97/Intel(R) High Definition Audio Signals: ACZ_RST#, ACZ_SDOUT, ACZ_SYNC Intel High Definition Audio Signals: ACZ_BIT_CLK NOTE: See VOH_HDA/VOL_HDA for High Definition Audio Low Voltage Mode (Mobile/Ultra Mobile Only) SMBus Signals: SMBCLK1, SMBDATA1 VOH4/VOL4 System Management Signals: SMLINK[1:0]1 GPIO Signals: GPIO11/SMBALERT1 Power Management Signals: Desktop Only: PLTRST#, SLP_S3#, SLP_S4#, SLP_S5#, SUSCLK#, SUS_STAT Mobile/Ultra Mobile Only: DPRSLPVR, PLTRST#, SLP_S3#, SLP_S4#, SLP_S5#, STP_CPU#, STP_PCI#, SUSCLK#, SUS_STAT GPIO Signals: Desktop Only: GPIO[39, 38, 33, 32, 20, 18, 16, 7, 6], GPIO[37,36,19,21]/ SATAGP[3:0]#, Mobile/Ultra Mobile Only: GPIO[39:37,19, 7, 6], GPIO[36,21]/ SATAGP[2,0]# Intel High Definition Audio Signals: AZ_DOCK_EN#/GPIO33 (Mobile Only) Other Signals: SPKR SATA Signal: SATALED#, SATACLKREQ#/GPIO35 EEPROM Signals: EE_CS, EE_DOUT, EE_SHCLK VOH6/VOL6 VOMIN7/VOMAX7 VOMIN8/VOMAX8 USB Signals: USBP[7:0][P,N] in Low-speed and Full-speed Modes PCI Express* Data TX Signals: PET[p,n][4:1] on ICH7 and PET[p,n][6:1] on ICH7R and ICH7DH and Mobile SATA Signals: Desktop Only: SATA[3:0]TX[P,N] Mobile Only: SATA[2,0]TX[P,N] VOH2/VOL2 VOH3/VOL3 VOH5/VOL5 796 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-6. DC Characteristic Output Signal Association (Sheet 2 of 2) Symbol Associated Signals LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4] PCI Signals: PCIRST#, GNT[3:0]#, GNT4/GPIO48, GNT5/GPIO17 GPIO Signals: Desktop Only: GPIO[34, 0], GPIO23/LDRQ1#, GPIO22/REQ4#, GPIO[5:2]/ PIRQ[H:E]#, GPIO1/REQ5# Mobile/Ultra Mobile Only: GPIO23/LDRQ1#, GPIO22/REQ4#, GPIO[5:2]/ PIRQ[H:E]#, GPIO1/REQ5#, GPIO0/BM_BUSY# Intel High Definition Audio Signals: AZ_DOCK_RST#/GPIO34 (Mobile Only) Interrupt Signals: SERIRQ SPI Signals: Desktop and Mobile Only: SPI_CS#, SPI_MOSI, SPI_CLK Processor Interface Signal: INIT3_3V# LAN Signals: LAN_RSTSYNC, LAN_TXD[2:0] GPIO Signals: GPIO[28:26, 25:24, 15:12, 10:8], GPIO[31:29]/OC[7:5]# VOH10/VOL10 VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK VOH_HDA/VOL_HDA (Mobile/Ultra Mobile Only) NOTES: Intel(R) High Definition Audio Signals: ACZ_RST#, ACZ_SDOUT, ACZ_SYNC NOTE: Only applies when running in Low Voltage Mode (1.5 V) USB Signals: USBP[7:0][P:N] in High-speed Mode Intel Quick Resume Technology Signals: EL_STATE[1:0]/GPIO[28:27], EL_RSVD/GPIO26 (ICH7DH Only) VOH9/VOL9 1. These signals are open drain. Intel (R) ICH7 Family Datasheet 797 Electrical Characteristics Table 23-7. DC Output Characteristics Symbol VOH1 VOL2 VOH2 VOH3 VOL4 VOH4 VOH5 VOH6 VOMIN7 VOMAX7 VOMIN8 VOMAX8 VOMIN8 VOMAX8 VOH9 VOL9 VOL6 VOL5 VOL3 VOL1 Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Minimum Output Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Voltage Minimum Output Voltage Maximum Output Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage HS Idle Level HS Data Signaling High HS Data Signaling Low Chirp J Level Chirp K Level VccSus3_3 0.5 0.9(Vcc3_3) 0.4 400 700 0.1(Vcc3_3) 400 600 Vcc3_3 Vcc3_3 VccSus3_3 0.5 0.9(Vcc3_3) 0.4 V_CPU_IO 0.3 Vcc3_3 Min Max 0.51 Unit V V 0.255 V V 0.1(Vcc3_3) V V V V 0.4 V V 0.4 V V mVdif fp-p 1200 mVdif fp-p mVdif fp-p mVdif fp-p mVdif fp-p mVdif fp-p V V V V 10.0 440 10.0 1100 mV mV mV mV mV 1.5 mA -0.5 mA 6 mA -0.5 mA 2 IOL / IOH 6 mA -6 mA 3 mA -3 mA 1.5 mA -0.5 mA 4 mA -2 mA 6 mA -2 mA 5 mA -2 mA Notes - 0.51 - 1 2 - 2 - 0.5 - 0.5 800 3 3 4 4 5 5 VOL10 VOH10 VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK VOL_HDA (Mobile/ Ultra Mobile Only) VOH_HDA (Mobile/ Ultra Mobile Only) NOTES: - -10.0 360 -10.0 700 -900 -500 0.1(VccHDA) Output Low Voltage V 1.5 mA Output High Voltage 0.9(Vcc_HDA) V -0.5 mA 1. Maximum Iol for CPUPWRGD is 12 mA for short durations (<500 mS per 1.5 s) and 9 mA for long durations. 2. The SERR#, PIRQ[H:A], GPIO11, SMBDATA, SMBCLK, LINKALERT#, and SMLINK[1:0] signal has an open drain driver and SATALED# has an open collector driver, and the VOH spec does not apply. This signal must have an external pull-up resistor. 3. PCI Express mVdiff p-p = |PETp[x] - PETn[x]| 798 Intel (R) ICH7 Family Datasheet Electrical Characteristics 4. Applicable only when SATA port signaling rate is 1.5 Gb/s: SATA Vdiff, TX (VOMAX/MIN8) is measured at the SATA connector on the transmit side closest to the ICH7 (generally, the motherboard connector), where SATA mV diff p-p = |SATAxTXP - SATAxTXN|. 5. Applicable only when SATA port signaling rate is 3 Gb/s: SATA Vdiff, TX (VOMAX/MIN8) is measured at the SATA connector on the transmit side closest to the ICH7 (generally, the motherboard connector), where SATA mV diff p-p = |SATAxTXP - SATAxTXN|. Table 23-8. Other DC Characteristics Symbol V5REF Vcc3_3 Vcc1_5_A, Vcc1_5_B, VccUSBPLL, VccSATAPLL, VccDMIPLL V_CPU_IO V5REF_Sus VccSus3_3 Vcc1_05 VccSus1_05 VccLAN3_3 (Mobile Only) VccLAN1_05 (Mobile Only) VccSusHDA (Mobile/Ultra Mobile Only) VccHDA (Mobile/Ultra Mobile Only) VccRTC VDI VCM VCRS VSE ILI1 ILI2 ILI3 ILI4 Parameter Intel(R) ICH7 Core Well Reference Voltage I/O Buffer Voltage Min 4.75 3.135 Max 5.25 3.465 Unit V V Notes 1 1 Internal Logic and I/O Buffer Voltage 1.425 1.575 V 1 Processor Interface Suspend Well Reference Voltage Suspend Well I/O Buffer Voltage Internal Logic Voltage Suspend Well Logic Voltage LAN Controller I/O Buffer Voltage LAN Controller Logic Voltage High Definition Audio Controller Low Voltage Mode Suspend Voltage High Definition Audio Controller Low Voltage Mode Core Voltage Battery Voltage Differential Input Sensitivity Differential Common Mode Range Output Signal Crossover Voltage Single Ended Rcvr Threshold ATA Input Leakage Current PCI_3V Hi-Z State Data Line Leakage PCI_5V Hi-Z State Data Line Leakage Input Leakage Current signals 0.945 4.75 3.135 0.998 0.998 3.135 0.998 1.25 5.25 3.465 1.102 1.102 3.465 1.102 V V V V V V V 1, 2 1 1 1 1 1.425 1.575 V Same as VccSus3_3 if not in low voltage mode Same as Vcc3_3 if not in low voltage mode 1 1.425 2.0 0.2 0.8 1.3 0.8 1.575 3.6 V V V |(USBPx+,USBPx)| Includes VDI 2.5 2.0 2.0 200 10 70 +100 V V V A A A A -200 -10 -70 -100 (0 V < VIN < 5 V) (0 V < VIN < 3.3 V) Max VIN = 2.7 V Min VIN = 0.5 V 3 - Clock Intel (R) ICH7 Family Datasheet 799 Electrical Characteristics Table 23-8. Other DC Characteristics Symbol CIN COUT CI/O CL CL NOTES: Parameter Input Capacitance Min Max 12 12 12 Typical Value XTAL1 XTAL2 6 6 pF pF Unit pF pF pF Notes FC = 1 MHz FC = 1 MHz FC = 1 MHz - All Other Output Capacitance I/O Capacitance 1. For all noise components 20 MHz, the sum of the DC voltage and the AC noise component must be within the specified DC min/max operating range on the ICH7 supply voltages. 2. The tolerances shown in Table 23-8 are inclusive of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a bandwidth limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz. 3. Includes CLK14, CLK48, LAN_CLK, and PCICLK. 800 Intel (R) ICH7 Family Datasheet Electrical Characteristics 23.4 1 AC Characteristics Table 23-9. Clock Timings (Sheet 1 of 2) Sym Parameter Min PCI Clock (PCICLK) t1 t2 t3 t4 t5 Period High Time Low Time Rise Time Fall Time 30 11 11 1 1 14 MHz Clock (CLK14) t6 t7 t8 t41 t42 Period High Time Low Time Rising Edge Rate Falling Edge Rate 67 20 20 1.0 1.0 48 MHz Clock (CLK48) fclk48 t9 t10 t11 t12 t13 Operating Frequency Frequency Tolerance High Time Low Time Rise Time Fall Time SMBus Clock (SMBCLK) fsmb t18 t19 t20 t21 Operating Frequency High time Low time Rise time Fall time 10 4.0 4.7 1000 300 16 50 KHz us us ns ns 3 Max Unit Notes Figur e 33.3 ns ns ns 23-1 23-1 23-1 23-1 23-1 4 4 V/ns V/ns 70 ns ns ns 1 1 23-1 23-1 23-1 4.0 4.0 V/ns V/ns 48.00 0 100 7 7 1.2 1.2 MHz ppm ns ns ns ns 2 23-1 23-1 23-1 23-1 23-16 23-16 23-16 23-16 Intel (R) ICH7 Family Datasheet 801 Electrical Characteristics Table 23-9. Clock Timings (Sheet 2 of 2) Sym Parameter Min Max Unit Notes Figur e AC '97 Clock (ACZ_BIT_CLK - AC `97 mode) (Desktop and Mobile Only) fac97 t26 t27 t28 t29 t30 Operating Frequency Input Jitter (refer to Clock Chip Specification) High time Low time Rise time Fall time -- 36 36 2.0 2.0 12.288 2 45 45 6.0 6.0 MHz ns ns ns ns ns 5 5 4 23-1 23-1 23-1 23-1 ACZ_BIT_CLK (Intel(R) High Definition Audio Mode) fHDA Operating Frequency Frequency Tolerance t26a t27a t28a Input Jitter (refer to Clock Chip Specification) High Time (Measured at 0.75Vcc) Low Time (Measured at 0.35Vcc) -- -- 18.75 18.75 24.0 100 300 22.91 22.91 MHz ppm ppm ns ns 23-1 23-1 SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN) (Desktop and Mobile Only) t36 t37 t38 Period Rise time Fall time 9.997 175 175 Suspend Clock (SUSCLK) fsuscl k t39 t39a 1. 2. 3. 4. 10.053 3 700 700 ns ps ps Operating Frequency High Time Low Time 10 10 32 -- -- kHz us us 6 6 6 CLK14 edge rates in a system as measured from 0.8 V to 2.0 V. The CLK48 expects a 40/60% duty cycle. The maximum high time (t18 Max) provides a simple method for devices to detect bus idle conditions. The ICH7 can tolerate a maximum of 2 ns of jitter from the input BITCLK. Note that clock jitter may impact system timing. Contact your Intel representative for further details and documentation. 5. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD. 6. SUSCLK duty cycle can range from 30% minimum to 70% maximum. NOTES: 802 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-10. PCI Interface Timing Sym t40 t41 t42 t43 Parameter AD[31:0] Valid Delay AD[31:0] Setup Time to PCICLK Rising AD[31:0] Hold Time from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCLKIN Rising PCIRST# Low Pulse Width GNT[5:0]# Valid Delay from PCICLK Rising t49 NOTE: GNT[2:0]# not on Ultra Mobile. REQ[5:0]# Setup Time to PCICLK Rising t50 NOTE: REQ[2:0]# not on Ultra Mobile. 1. Refer to note 3 of table 4-4 in Section 4.2.2.2 and note 2 of table 4-6 in Section 4.2.3.2 of the PCI Local Bus Specification, Revision 2.3 for measurement details. Min 2 7 0 2 Max 11 -- -- 11 Units ns ns ns ns Notes 1 Figure 23-2 23-3 23-3 1 23-2 t44 2 -- ns 23-6 t45 2 28 ns 23-4 t46 7 -- ns 23-3 t47 t48 0 1 2 -- -- 12 ns ms ns 23-3 23-5 12 -- ns NOTES: Intel (R) ICH7 Family Datasheet 803 Electrical Characteristics Table 23-11. IDE PIO Mode Timings Sym t60 t61 t62 t62i t63 t64 t65 t66 t66z t69 t60rd t60a t60b t60c Parameter Cycle Time (min) Addr setup to DIOW#/ DIOR# (min) DIRW#/DIOR# (min) DIOW#/DIOR# recovery time (min) DIOW# data setup (min) DIOW# data hold (min) DIOR# data setup (min) DIOR# data hold (min) DIOR# data tristate (max) DIOW#/DIOR# to address valid hold (min) Read data Valid to IORDY active (min) IORDY Setup IORDY Pulse Width (max) IORDY assertion to release (max) Mode 0 (nS) 600 70 165 -- 60 30 50 5 30 20 0 35 1250 5 Mode 1 (nS) 383 50 125 -- 45 20 35 5 30 15 0 35 1250 5 Mode 2 (nS) 240 30 100 -- 30 15 20 5 30 10 0 35 1250 5 Mode 3 (nS) 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 Mode 4 (nS) 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Figure 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 23-7 Table 23-12. IDE Multiword DMA Timings Sym t70 t70d t70e t70f t70g t70h t70i t70j t70kr t70kw t70lr t70lw t70m t70n t70z Parameter Cycle Time (min) DIOR#/DIOW# (min) DIOR# Data access (max) DIOR# Data hold (min) DIOR#/DIOW# Data setup (min) DIOW# Data hold (min) DDACK# to DIOR#/DIOW# setup (min) DIOR#/DIOW# to DDACK# hold (min) DIOR# negated pulse width (min) DIOW# negated pulse width (min) DIOR# to DDREQ delay (max) DIOW# to DDREQ delay (max) DCS1#/DCS3# valid to DIOR#/DIOW# (min) DCS1#/DCS3# hold (min) DDACK# to tristate (max) Mode 0 (nS) 480 215 150 5 100 20 0 20 50 215 120 40 50 15 20 Mode 1 (nS) 150 80 60 5 30 15 0 5 50 50 40 40 30 10 25 Mode 2 (nS) 120 70 50 5 20 10 0 5 25 25 35 35 25 10 25 Figure 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 23-8 804 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2) 1 Sym Parameter Mode 0 (ns) Min Max Mode 1 (ns) Min Max Mode 2 (ns) Min Max Measuring Location Sender Connector Figure t80 Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) 240 160 120 t81 112 -- 73 -- 54 -- End Recipient Connector Sender Connector Recipient Connector Intel(R) ICH7 ball Recipient Connector 23-10 t82 t83a Two Cycle Time (T2cyc) Data Setup Time (Tds) Recipient IC data setup time (from data valid until STROBE edge) (see Note 2) (Tdsic) Data Hold Time (Tdh) Recipient IC data hold time (from STROBE edge until data may become invalid) (see Note 2) (Tdhic) Data Valid Setup Time (Tdvs) Sender IC data valid setup time (from data valid until STROBE edge) (see Note 2) (Tdvsic) Data Valid Hold Time (Tdvh) Sender IC data valid hold time (from STROBE edge until data may become invalid) (see Note 2) (Tdvhic) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) CRC Word Setup Time at Host (Tcvs) 230 15 14. 7 5 -- -- 153 10 -- -- 115 7 -- -- 23-10 23-10 t83b -- 9.7 -- 6.8 -- t84a -- 5 -- 5 -- 23-10 t84b 4.8 -- 4.8 -- 4.8 -- ICH7 ball t85a 70 -- 48 -- 31 -- Sender Connector 23-10 t85b 72. 9 -- 50. 9 -- 33. 9 -- ICH7 ball t86a 6.2 -- 6.2 -- 6.2 -- Sender Connector 23-10 t86b 9 -- 9 -- 9 -- ICH7 ball t87 t88 t89 t90 t91 t92a 0 20 20 160 20 70 150 -- 70 -- -- -- 0 20 20 125 20 48 150 -- 70 -- -- -- 0 20 20 100 20 31 150 -- 70 -- -- -- See Note 2 Host Connector Host Connector Recipient Connector Host Connector Host Connector 23-12 23-12 23-9 23-11 23-9, 23-12 Intel (R) ICH7 Family Datasheet 805 Electrical Characteristics Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2) 1 Sym Parameter Mode 0 (ns) Min Max Mode 1 (ns) Min Max Mode 2 (ns) Min Max Measuring Location Figure t92b CRC word valid hold time at sender (from DMACK# negation until CRC may become invalid) (see Note 2) (Tcvh) STROBE output released-todriving to the first transition of critical timing (Tzfs) Data Output Released-toDriving Until the First Tunisian of Critical Timing (Tdzfs) Unlimited Interlock Time (Tui) Maximum time allowed for output drivers to release (from asserted or negated) (Taz) Minimum time for drivers to assert or negate (from released) (Tzad) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY#) (Trfs) Maximum time before releasing IORDY (Tiordyz) Minimum time before driving IORDY (see Note 2) (Tziordy) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) (Tss) 6.2 -- 6.2 -- 6.2 -- Host Connector t93 0 -- 0 -- 0 -- Device Connector Sender Connector Host Connector 23-12 t94 70 -- 48 -- 31 -- 23-9 t95 0 -- 0 -- 0 -- 23-9 t96a -- 10 -- 10 -- 10 See Note 2 t96b 0 -- 0 -- 0 -- Device Connector t97 -- 75 -- 70 -- 60 Sender Connector Device Connector Device Connector 23-9 t98a t98b -- 0 20 -- 0 20 -- 0 20 -- t99 50 -- 50 -- 50 -- Sender Connector 23-11 1. The specification symbols in parentheses correspond to the AT Attachment NOTES: (ATA/ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI measuring these timing parameters. - 6 with Packet Interface - 6) specification for further details on 806 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2) 1 Sym Parameter Mode 3 (ns) Min Max 90 Mode 4 (ns) Min Max 60 Mode 5 (ns) Min Max 40 16. 8 38 4.0 Measuring Location Sender Connector Figure t80 Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) 39 t81 -- 25 -- -- End Recipient Connector Sender Connector Recipient Connector 23-10 t82 t83 Two Cycle Time (T2cyc) Data Setup Time (Tds) Recipient IC data setup time (from data valid until STROBE edge) (see Note 2) (Tdsic) Data Hold Time (Tdh) Recipient IC data hold time (from STROBE edge until data may become invalid) (see Note 2) (Tdhic) Data Valid Setup Time (Tdvs) Sender IC data valid setup time (from data valid until STROBE edge) (see Note 2) (Tdvsic) Data Valid Hold Time (Tdvh) Sender IC data valid hold time (from STROBE edge until data may become invalid) (see Note 2) (Tdvhic) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) CRC Word Setup Time at Host (Tcvs) 86 7 -- -- 57 5 -- -- -- -- 23-10 23-10 t83b 6.8 -- 4.8 -- 2.3 -- ICH7 Balls t84 5 -- 5 -- 4.6 -- Recipient Connector 23-10 t84b 4.8 -- 4.8 -- 2.8 -- ICH7 Balls t85 20 -- 6.7 -- 4.8 -- Sender Connector 23-9 23-10 t85b 22. 6 -- 9.5 -- 6.0 -- ICH7 Balls t86 6.2 -- 6.2 -- 4.8 -- Sender Connector 23-9 23-10 t86b 9.0 -- 9.0 -- 6.0 -- ICH7 Balls t87 t88 t89 t90 t91 t92a 0 20 20 100 20 20 100 -- 55 -- -- -- 0 20 20 100 20 6.7 100 -- 55 -- -- -- 0 20 20 85 20 10 75 -- 50 -- -- -- See Note 2 Host Connector Host Connector Recipient Connector Host Connector Host Connector 23-12 23-12 23-10 23-11 23-12 Intel (R) ICH7 Family Datasheet 807 Electrical Characteristics Table 23-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 2 of 2) 1 Sym Parameter Mode 3 (ns) Min Max Mode 4 (ns) Min Max Mode 5 (ns) Min Max Measuring Location Figure CRC Word Hold Time at Sender t92b CRC word valid hold time at sender (from DMACK# negation until CRC may become invalid) (see Note 2) (Tcvh) STROBE output released-todriving to the first transition of critical timing (Tzfs) Data Output Released-toDriving Until the First Transition of Critical Timing (Tdzfs) Unlimited Interlock Time (Tui) Maximum time allowed for output drivers to release (from asserted or negated) (Taz) Drivers to assert or negate (from released) (Tzad) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY#) (Trfs) Maximum time before releasing IORDY (Tiordyz) Minimum time before driving IORDY (see Note 2) (Tziordy) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) (Tss) 6.2 -- 6.2 -- 10. 0 -- Host Connector t93 0 -- 0 -- 35 -- Device Connector 23-12 t94 20. 0 -- 6.7 -- 25 -- Sender Connector Host Connector t95 0 -- 0 -- 0 -- t96a -- 10 -- 10 -- 10 See Note 2 t96b 0 -- 0 -- 0 -- Device Connector Sender Connector Device Connector Device Connector t97 -- 60 -- 60 -- 50 t98a -- 20 -- 20 -- 20 t98b 0 -- 0 -- 0 -- t99 50 -- 50 -- 50 -- Sender Connector 23-11 1. The specification symbols in parentheses correspond to the AT Attachment NOTES: (ATA/ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI measuring these timing parameters. - 6 with Packet Interface - 6) specification for further details on 808 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-15. Universal Serial Bus Timing Sym Parameter Full-speed t100 t101 USBPx+, USBPx- Driver Rise Time USBPx+, USBPx- Driver Fall Time Source Differential Driver Jitter t102 t103 t104 To Next Transition For Paired Transitions Source SE0 interval of EOP Source Jitter for Differential Transition to SE0 Transition Receiver Data Jitter Tolerance t105 t106 t107 To Next Transition For Paired Transitions EOP Width: Must accept as EOP Width of SE0 interval during differential transition Min Max Units Notes Fig Source1 4 4 20 20 ns ns Note 2, CL = 50 pF Note 2, CL = 50 pF 3, 4 23-13 23-13 -3.5 -4 160 3.5 4 175 5 ns ns ns ns 23-14 23-15 5 6 -2 -18.5 -9 82 -- 18.5 9 -- 14 ns ns ns ns 4 23-14 23-15 5 Low-speed Source7 t108 USBPx+, USBPx - Driver Rise Time - Driver Fall Time 75 300 ns t109 USBPx+, USBPx 75 300 ns Note 2, 8, CL = 50 pF CL = 350 pF Note 2, 8, CL = 50 pF CL = 350 pF 3, 4 23-13 23-13 Source Differential Driver Jitter t110 t111 t112 t113 t114 t115 To Next Transition For Paired Transitions Source SE0 interval of EOP Source Jitter for Differential Transition to SE0 Transition Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width: Must accept as EOP Width of SE0 interval during differential transition -25 -14 1.25 25 14 1.50 100 152 200 -- 210 ns ns s ns ns ns ns ns 23-14 23-15 5 6 -40 -152 -200 670 -- 4 5 23-14 23-15 1. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s. 2. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. 3. Timing difference between the differential data signals. 4. Measured at crossover point of differential data signals. 5. Measured at 50% swing point of data signals. 6. Measured from last crossover point to 50% swing point of data line at leading edge of EOP. 7. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s. 8. Measured from 10% to 90% of the data signal. NOTES: Intel (R) ICH7 Family Datasheet 809 Electrical Characteristics Table 23-16. SATA Interface Timings (Desktop and Mobile Only) Sym UI UI-2 t120 t121 t122 t123 t124 t125 1. 2. 3. 4. Parameter Gen I Operating Data Period Gen II Operating Data Period (3Gb/s) Rise Time Fall Time TX differential skew COMRESET COMWAKE transmit spacing OOB Operating Data period Min 666.43 333.21 0.2 0.2 -- 310.4 103.5 646.67 Max 670.12 335.06 0.41 0.41 20 329.6 109.9 686.67 Units ps ps UI UI ps ns ns ns Notes Figure 1 2 3 3 4 NOTES: 20% - 80% at transmitter 80% - 20% at transmitter As measured from 100 mV differential crosspoints of last and first edges of burst. Operating data period during Out-Of-Band burst transmissions. Table 23-17. SMBus Timing Sym t130 Parameter Bus Tree Time Between Stop and Start Condition Hold Time after (repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Device Time Out Cumulative Clock Low Extend Time (slave device) Cumulative Clock Low Extend Time (master device) Min 4.7 Max -- Units s Notes Figure 23-16 t131 t132 t133 t134 t135 t136 t137 t138 4.0 4.7 4.0 0 250 25 -- -- -- -- -- -- -- 35 25 10 s s s ns ns ms ms ms 2 3 1 23-16 23-16 23-16 23-16 23-16 23-17 23-17 4 1. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns. 2. A device will timeout when any clock low exceeds this value. 3. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 4. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. NOTES: 810 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-18. AC '97 / Intel(R) High Definition Audio Timing Sym t140 t141 t142 t143 t144 t145 t146 Parameter ACZ_SDIN[2:0] Setup to Falling Edge of ACZ_BIT_CLK ACZ_SDIN[2:0] Hold from Falling Edge of ACZ_BIT_CLK ACZ_SYNC, ACZ_SDOUT valid delay from rising edge of ACZ_BIT_CLK Time duration for which ACZ_SDOUT is valid before ACZ_BIT_CLK edge. Time duration for which ACZ_SDOUT is valid after ACZ_BIT_CLK edge. Setup time for ACZ_SDIN[2:0] at rising edge of ACZ_BIT_CLK Hold time for ACZ_SDIN[2:0] at rising edge of ACZ_BIT_CLK Min 10 10 -- 7 7 15 0 Max -- -- 15 -- -- -- -- Units ns ns ns ns ns ns ns Notes 1 Figures 23-30 23-30 23-30 23-31 23-31 23-31 23-31 1 1 2 2 2 2 1. Audio link operating in AC `97 mode. (Desktop and Mobile Only) 2. Audio link operating in Intel High Definition Audio mode. NOTES: Table 23-19. LPC Timing Sym t150 t151 t152 t153 t154 t155 t156 t157 Parameter LAD[3:0] Valid Delay from PCICLK Rising LAD[3:0] Output Enable Delay from PCICLK Rising LAD[3:0] Float Delay from PCICLK Rising LAD[3:0] Setup Time to PCICLK Rising LAD[3:0] Hold Time from PCICLK Rising LDRQ[1:0]# Setup Time to PCICLK Rising LDRQ[1:0]# Hold Time from PCICLK Rising LFRAME# Valid Delay from PCICLK Rising Min 2 2 -- 7 0 12 0 2 Max 11 -- 28 -- -- -- -- 12 Units ns ns ns ns ns ns ns ns Notes Figures 23-2 23-6 23-4 23-3 23-3 23-3 23-3 23-2 Table 23-20. Miscellaneous Timings Sym t160 t161 t162 t163 t164 t165 1 Parameter SERIRQ Setup Time to PCICLK Rising SERIRQ Hold Time from PCICLK Rising RI#, EXTSMI#, GPIO, USB Resume Pulse Width SPKR Valid Delay from OSC Rising SERR# Active to NMI Active IGNNE# Inactive from FERR# Inactive Min 7 0 2 -- -- -- Max -- -- -- 200 200 230 Units ns ns RTCCLK ns ns ns Notes Figures 23-3 23-3 23-5 23-2 Intel (R) ICH7 Family Datasheet 811 Electrical Characteristics Table 23-21. SPI Timings (Desktop and Mobile Only) Sym t180 t182 t183 t184 t185 t186 t187 NOTES: Parameter Serial Clock Frequency Duty cycle at the host Tco of SPI_MOSI with respect to serial clock falling edge at the host Setup of SPI_MISO with respect to serial clock falling edge at the host Hold of SPI_MISO with respect to serial clock falling edge at the host Setup of SPI_CS# assertion with respect to serial clock rising at the host. Hold of SPI_CS# deassertion with respect to serial clock falling at the host. Min 17.3 40 -5 16 0 30 30 Max 18.4 60 13 -- -- -- -- Units MHz % ns ns ns ns ns Notes 1 Figures 23-32 23-32 23-32 23-32 23-32 23-32 1. The typical clock frequency driven by the ICH7 is 17.9 MHz. Table 23-22. (Power Sequencing and Reset Signal Timings (Sheet 1 of 2) Sym t200 t201 t202 t203 Parameter VccRTC active to RTCRST# inactive V5REF_Sus active to VccSus3_3 active VccSus3_3 active to VccSus1_05 active VccRTC supply active to VccSus supplies active VccSus supplies active to LAN_RST# inactive, RSMRST# inactive (Desktop Only) t205 VccSus supplies active to RSMRST# inactive (Mobile/Ultra Mobile Only) t206 VccLAN3_3 active to VccLAN1_05 active (Mobile Only) VccSus supplies active to VccLAN supplies active (Mobile Only) t208 VccLAN supplies active to LAN_RST# inactive (Mobile Only) t209 t211 V5REF active to Vcc3_3 active Vcc1_5 active to V_CPU_IO active 0 -- -- -- ms -- 1 Min 18 0 -- 0 Max -- -- -- -- Units ms ms -- ms Notes Fig 23-18 23-19 1 23-18 23-19 23-18 23-19 23-18 23-19 23-18 23-20 23-19 23-21 2 3 t204 10 -- ms 5 -- ms 4 -- -- -- 23-19 t207 0 -- ms 5 23-19 10 -- ms 23-19 23-18 23-19 23-18 23-19 6 812 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-22. (Power Sequencing and Reset Signal Timings (Sheet 2 of 2) Sym t212 Parameter VccLAN supplies active to Vcc supplies active (Mobile Only) VccSus supplies active to Vcc supplies active (Desktop Only) Vcc supplies active to PWROK t214 NOTE: PWROK assertion indicates that PCICLK has been stable for at least 1 ms. 99 -- ms 5, 7 Min 0 Max -- Units ms Notes 5 Fig 23-19 t213 0 -- ms 3 23-18 23-18 23-19 23-20 23-21 23-23 23-24 23-25 23-26 23-20 23-23 23-24 23-21 23-25 23-26 23-20 23-21 23-23 23-24 23-25 23-26 23-20 23-21 23-23 23-24 23-25 23-26 t215 V_CPU_IO active to STPCLK# and CPUSLP# inactive (Desktop Only) Vcc active to DPRSLPVR inactive and STPCLK#, STP_CPU#, STP_PCI#, DPSLP#, DPRSTP# inactive (Mobile/Ultra Mobile Only) PWROK and VRMPWRGD active and SYS_RESET# inactive to SUS_STAT# inactive and Processor I/F signals latched to strap value -- 50 ns t216 -- 50 ns t217 32 38 RTCCLK 8, 9 t218 SUS_STAT# inactive to PLTRST# inactive 2 3 RTCCLK 9 t228 t229 NOTES: ACZ_RST# active low pulse width ACZ_RST# inactive to ACZ_BIT_CLK startup delay 1 162.8 -- -- us ns 1. 5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. 2. The associated 3.3 V and 1.05 V supplies are assumed to power up or down `together'. If the integrated VccSus1_05 voltage regulator is not used: a) VccSus3_3 must power up before VccSus1_05 or after VccSus1_05 within 0.7 V, b) VccSus1_05 must power down before VccSus3_3 or after VccSus3_3 within 0.7 V. 3. The VccSus supplies must not be active while the VccRTC supply is inactive. 4. (Mobile Only) - a) VccLan3_3 must power up before VccLAN1_05 or after VccLAN1_05 within 0.7 V, b) VccLAN1_05 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7V. 5. (Mobile Only) - Vcc or VccLAN supplies must not be active while the VccSus supplies are inactive, and the Vcc supplies must not be active while the VccLAN supplies are inactive. 6. Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.7 V, b) V_CPU_IO must power down before Vcc1_5 or after Vcc1_5 within 0.7 V. 7. Vcc supplies refer to all "core well" supplies: Vcc3_3, Vcc1_05, Vcc1_5, V5REF, VccUSBPLL, VccDMIPLL, VccSATAPLL, V_CPU_IO and VccHDA (Mobile Only). It implies that all "suspend wells" and VccRTC are stable too. 8. INIT# value determined by value of the CPU BIST Enable bit (Chipset Configuration Register Offset 3414h: bit 2). 9. These transitions are clocked off the internal RTC. 1 RTC clock is approximately from 28.992 s to 32.044 s. Intel (R) ICH7 Family Datasheet 813 Electrical Characteristics Table 23-23. Power Management Timings (Sheet 1 of 3) Sym t230 t231 t232 t233 t234 t250 Parameter VccSus active to SLP_S5#, SLP_S4#, SLP_S3#, SUS_STAT#, PLTRST# and PCIRST#active RSMRST# inactive to SUSCLK running, SLP_S5# inactive SLP_S5# inactive to SLP_S4# inactive SLP_S4# inactive to SLP_S3# inactive Processor I/F signals latched prior to STPCLK# active (Mobile/Ultra Mobile Only) t253 t254 DPSLP#/Ultra Mobile active to STP_CPU# active (Mobile Only) STP_CPU# active to processor clock stopped (Mobile/Ultra Mobile Only) STP_CPU# active to DPRSTP#, DPRSLPVR active (Mobile/Ultra Mobile Only) t265 Break Event to DPRSTP#, DPRSLPVR inactive (C4 Exit) (Mobile/Ultra Mobile Only) DPRSLPVR, DPRSTP# inactive to STP_CPU# inactive and CPU Vcc ramped (Mobile/Ultra Mobile Only) Break Event to STP_CPU# inactive t267 (C3 Exit) (Mobile/Ultra Mobile Only) t268 STP_CPU# inactive to processor clock running (Mobile/Ultra Mobile Only) t269 t271 STP_CPU# inactive to DPSLP# inactive (Mobile/Ultra Mobile Only) S1 Wake Event to CPUSLP# inactive (Desktop Only) Break Event to STPCLK# inactive t273 (C2 Exit) (Mobile/Ultra Mobile Only) t274 STPCLK# inactive to processor I/F signals unlatched (Mobile/Ultra Mobile Only) 8 9 PCICLK 5, 6 Min Max 50 110 Units ns ms Notes Fig 23-20 23-21 1, 2 23-20 23-21 23-20 23-21 23-20 23-21 23-27 23-29 23-30 23-28 23-29 23-29 23-30 23-29 See Note Below 1 0 2 RTCCLK 3 4 5 1 0 1 - PCICLK PCICLK 6 6, 7 t255 0 1.5 1.8 s 8 23-29 t266 Programable. See D31:F0:AA, bits 3:2 6 Note 14 s 23-29 PCICLK 6, 9, 10 23-28 0 3 PCICLK 6, 7 23-29 23-30 23-28 23-29 23-22 1 1 1 25 PCICLK PCICLK 6, 11 6 0 ns 23-27 23-27 23-29 23-30 23-22 23-23 23-24 23-25 23-26 t280 STPCLK# active to DMI Message 0 PCICLK 12 814 Intel (R) ICH7 Family Datasheet Electrical Characteristics Table 23-23. Power Management Timings (Sheet 2 of 3) Sym t281 (Desktop Only) DMI Message to SUS_STAT# active SUS_STAT# active to PLTRST#, PCIRST# active (Desktop Only) SUS_STAT# active to STP_PCI# active (Mobile/Ultra Mobile Only) STP_PCI# active to PLTRST# and PCIRST# active (Mobile/Ultra Mobile Only) t287 PLTRST#, PCIRST# active to SLP_S3# active (S3COLD Configuration Only) SLP_S3# active to PWROK, VRMPWRGD inactive (Mobile/Ultra Mobile Only) t289 SLP_S3# active to PWROK, VRMPWRGD inactive (Desktop Only) t290 (S3COLD Configuration Only) PWROK, VRMPWRGD inactive to Vcc supplies inactive (Mobile/Ultra Mobile Only) t291 SLP_S3# active to SLP_S4# active (S3HOT Configuration Only) SLP_S4# active to VRMPWRGD and PWROK inactive (S3HOT Configuration Only) PWROK, VRMPWRGD inactive to Vcc supplies inactive PWROK, VRMPWRGD inactive to Vcc supplies inactive (Desktop Only) t295 SLP_S4# active to SLP_S5# active 1 2 RTCCLK 4, 16 Parameter DMI Message to CPUSLP# active Min 60 Max 63 Units PCICLK Notes 6 Fig 23-22 23-23 23-24 23-25 23-26 23-23 23-24 23-25 23-26 23-25 23-26 23-23 23-24 23-25 23-26 23-25 t283 2 RTCCLK 4 t284 t285 7 2 17 10 RTCCLK RTCCLK 4 4 t286 5 7 RTCCLK 4 1 2 RTCCLK 4 t288 0 ms 13 0 ms 13 23-23 20 ns 14, 15 23-25 23-23 23-24 23-25 23-26 23-24 23-26 23-24 23-26 23-23 23-23 23-24 23-25 23-26 23-23 23-24 23-25 23-26 23-23 23-24 23-25 23-26 1 2 RTCCLK 4 t292 t293 t294 0 20 20 ms ns ns 13 14, 15 14, 15 t296 Wake Event to SLP_S5# inactive 1 10 RTCCLK 4 t297 SLP_S5# inactive to SLP_S4# inactive See Note Below 3 Intel (R) ICH7 Family Datasheet 815 Electrical Characteristics Table 23-23. Power Management Timings (Sheet 3 of 3) Sym Parameter Min Max Units Notes 4 Fig 23-23 23-24 23-25 23-26 23-23 23-24 23-25 23-26 23-23 23-24 23-25 23-26 23-22 23-23 23-24 23-25 23-26 t298 SLP_S4# inactive to SLP_S3# inactive 1 2 RTCCLK t299 S4 Wake Event to SLP_S4# inactive (S4 Wake) See Note Below small as possi ble 3 t300 S3 Wake Event to SLP_S3# inactive (S3 Wake) CPUSLP# inactive to STPCLK# inactive (Desktop Only) SLP_S3# inactive to ICH7 check for PWROK active SLP_S3# active to Vcc supplies inactive Other Timings 0 RTCCLK 4 t301 8 PCICLK t302 t303 4 5 5 msec us 15, 17 t310 t311 t312 THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5# active RSMRST# rising edge transition from 20% to 80% RSMRST# falling edge transition 3 50 PCI CLK us 18 1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s. 2. If the AFTERG3_EN bit (GEN_PMCON_3 Configuration Register Bit 1) is set to a 1, SLP_S5# will not be deasserted until a wake event is detected. If the AFTERG3_EN bit is set to 0, SLP_S5# will deassert within the specification listed in the table. 3. The Min/Max times depend on the programming of the "SLP_S4# Minimum Assertion Width" and the "SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3). 4. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 28.992 s to 32.044 s. 5. Note that this does not apply for synchronous SMIs. 6. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns. 7. This is a clock generator specification. 8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for DPRSLPVR has been met, then this is permitted to be 0. 9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for STP_CPU# has been met, then this is permitted to be 0. 10.This value should be at most a few clocks greater than the minimum. 11.This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 s). 12.The ICH7 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing for this cycle getting to the ICH7 is dependant on the processor and the memory controller. 13.The ICH7 has no maximum timing requirement for this transition. It is up to the system designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes. 14.t290, t293, and t294 apply during S0 to G3 transitions only. In addition, the timings are not applied to V5REF. V5REF timings are bonded by power sequencing. 15.A Vcc supply is inactive when the voltage is below the min value specified in Table 23-8. 16.If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together similar to timing t287 (PCIRST# active to SLP_S3# active). 17.t303 applies during S0 to S3-S5 transitions. 18.RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V. NOTES: 816 Intel (R) ICH7 Family Datasheet Electrical Characteristics 23.5 Timing Diagrams Figure 23-1. Clock Timing Period High Time 2.0V 0.8V Low Time Fall Time Rise Time Figure 23-2. Valid Delay from Rising Clock Edge Clock 1.5V Valid Delay Output VT Figure 23-3. Setup and Hold Times Clock 1.5V Setup Time Hold Time Input VT VT Intel (R) ICH7 Family Datasheet 817 Electrical Characteristics Figure 23-4. Float Delay Input VT Float Delay Output Figure 23-5. Pulse Width Pulse Width VT VT Figure 23-6. Output Enable Delay Clock 1.5V Output Enable Delay Output VT 818 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-7. IDE PIO Mode t60 CS0#, CS1#, DA[2:0] t69 t62 DIOR#/DIOW# t62i t61 DD[15:0] Writes t63 DD[15:0] Reads t60a IORDY t60c IORDY t60c t60b t60rd t65 t66 t66z t64 Figure 23-8. IDE Multiword DMA CS0#/ CS1# t70m DDREQ t70i DDACK# t70j t70d DIOR#/DIOW# t70e t70g t70f t70z t70k t70l t70 t70n DD[15:0] Read t70g DD[15:0] Write t70h Intel (R) ICH7 Family Datasheet 819 Electrical Characteristics Figure 23-9. Ultra ATA Mode (Drive Initiating a Burst Read) DMARQ (drive) t96 t91 DMACK# (host) t89 STOP (host) t98 t89 DMARDY# (host) t99b t94 t97 DD[15:0] t95 STROBE (drive) t85 t86 DA[2:0], CS[1:0] Figure 23-10. Ultra ATA Mode (Sustained Burst) t82 t81 t85 t99f STROBE @ sender t86 t99g Data @ sender t86 t99g t86 t99g t81 t85 t99f t83 STROBE @ receiver t84 t99e Data @ receiver t99d t83 t99d t84 t99e t84 t99e 820 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-11. Ultra ATA Mode (Pausing a DMA Burst) t90 STOP (host) DMARDY# t99 STROBE DATA Figure 23-12. Ultra ATA Mode (Terminating a DMA Burst) DMARQ (drive) t87 DMACK# (host) t99c t99a t88 t91 STOP (host) DMARDY# (drive) t87 Strobe (host) t92 DATA (host) t93 t91 CRC Intel (R) ICH7 Family Datasheet 821 Electrical Characteristics Figure 23-13. USB Rise and Fall Times Rise Time CL Differential Data Lines 10% CL tR tF 10% 90% Fall Time 90% Low-speed: 75 ns at CL = 50 pF, 300 ns at C L = 350 pF Full-speed: 4 to 20 ns at C L = 50 pF High-speed: 0.8 to 1.2 ns at C L = 10 pF Figure 23-14. USB Jitter T period Crossover Points Differential Data Lines Jitter Consecutive Transitions Paired Transitions Figure 23-15. USB EOP Width Tperiod Data Crossover Level Differential Data Lines EOP Width 822 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-16. SMBus Transaction t19 t20 t21 SMBCLK t131 t134 t135 t132 t18 t133 SMBDATA t130 Figure 23-17. SMBus Timeout Start t137 CLK ack t138 SMBCLK t138 CLK ack Stop SMBDATA Intel (R) ICH7 Family Datasheet 823 Electrical Characteristics Figure 23-18. Power Sequencing and Reset Signal Timings (Desktop Only) PWROK t213 V_CPU_IO t211 Vcc1_5_A, Vcc1_5_B Vcc1_05 and other power 1 Vcc3_3 V5REF LAN_RST#, RSMRST# t203 VccSus1_05 t202 VccSus3_3 t201 V5REF_Sus t204 t209 t214 RTCRST# VccRTC t200 ICH7 P S D kt d NOTES: 1. Other power includes VccUSBPLL, VccDMIPLL, and VccSATAPLL. All of these power signals must independently meet the timings shown in the figure. There are no timing interdependencies between Vcc1_05 and these other power signals. There are also no timing interdependencies for these power signals, including Vcc1_05, to Vcc3_3 and Vcc1_5_A/Vcc1_5_B. However, If Vcc3_3 (core well buffer) is powered before Vcc1_05 (core well logic), core well signal states are indeterminate, undefined, and may glitch prior to PWROK assertion. Refer to Section 3.3 and Section 3.4 for a list of signals that will be determinate before PWROK. 2. PRWOK must not glitch, even if RSMRST# is low. 824 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-19. Power Sequencing and Reset Signal Timings (Mobile/Ultra Mobile Only) t214 PW ROK t212 V_CPU_IO Vcc1_5_A, Vcc1_5_B Vcc1_05 and other power 1 Vcc3_3 t209 t211 V5REF LAN_RST# t208 VccLAN1_05 t207 t206 VccLAN3_3 RSMRST# t203 t202 VccSus3_3 VccSus1_05 t205 V5REF_Sus t201 RTCRST# VccRTC t200 NOTES: 1. Other power includes VccUSBPLL, VccDMIPLL, and VccSATAPLL. All of these power signals must independently meet the timings shown in the figure. There are no timing interdependencies between Vcc1_05 and these other power signals. There are also no timing interdependencies for these power signals, including Vcc1_05, to Vcc3_3 and Vcc1_5_A/Vcc1_5_B. However, If Vcc3_3 (core well buffer) is powered before Vcc1_05 (core well logic), core well signal states are indeterminate, undefined, and may glitch prior to PWROK assertion. Refer to Section 3.3 and Section 3.4 for a list of signals that will be determinate before PWROK. Intel (R) ICH7 Family Datasheet 825 Electrical Characteristics Figure 23-20. G3 (Mechanical Off) to S0 Timings (Desktop Only) System State DMI message G3 G3 S5 S4 S3 S0 S0 state STPCLK#, CPUSLP# t215 (from V_CPU_IO) Processor I/F signals PLTRST# t218 SUS_STAT# t217 VRMPWRGD Strap Values NormalOperation PWROK t214 Vcc 1 SLP_S3# t230 SLP_S4# t232 t233 t234 SLP_S5# SUSCLK t231 RSMRST# LAN_RST# t204 VccSus1_05 t202 VccSus3_3 ICH7_G3_to_S0_DT .vsd Running NOTES: 1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. 826 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-21. G3 (Mechanical Off) to S0 Timings (Mobile/Ultra Mobile Only) System State DMI message STPCLK#, STP_CPU#, STP_PCI#, DPSLP#, DPRSTP# Main Battery Removed (G3) G3 S5 S4 S3 S0 S0 state t216 Strap Values Processor I/F Signals PLTRST# Normal Operation t218 SUS_STAT# VRMPWRGD t217 PWROK, LAN_RST# Vcc 1, VccLAN SLP_S3# t230 t233 t234 t214 t217 SLP_S4# SLP_S5# t232 SUSCLK t231 RSMRST# t205 VccSus1_05 VccSus3_3 t202 Running ICH7 G3 t S0 M bil d NOTES: 1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. Figure 23-22. S0 to S1 to S0 Timing (Desktop Only) STATE S0 S0 S1 S1 S1 S0 S0 STPCLK# t301 DMI Message t280 CPUSLP# t281 Wake Event t271 Intel (R) ICH7 Family Datasheet 827 Electrical Characteristics Figure 23-23. S0 to S5 to S0 Timings, S3COLD (Desktop Only) S0 S0 S3 S3 S4 S5 S4 S3 S3/S4/S5 S0 S0 STPCLK# t280 t215 (from V_CPU_IO) DMI Message SUS_STAT# t283 PLTRST# t284 SLP_S3# (S3COLD Config) t287 SLP_S4# t291 t217 t218 t300 t299 t298 SLP_S5# t297 t295 t296 Wake Event VRMPWRGD t289 PWROK Vcc1 t294 ICH7_S0_S5_S0_DT _S3COLD.vsd t214 NOTES: 1. Vcc includes Vcc1_5_A, Vcc 1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. 2. t294 is applicable when the system transitions from S0 to G3 only. 828 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-24. S0 to S5 to S0 Timings, S3HOT (Desktop Only) S0 S0 S3 S3 S4 S5 S4 S3 S3/S4/S5 S0 S0 STPCLK# t280 t215 (from V_CPU_IO) DMI Message SUS_STAT# t283 PLTRST# t284 SLP_S3# (S3HOT Config) t287 SLP_S4# t291 t217 t302 t300 t218 t299 t298 SLP_S5# t297 t295 t296 Wake Event VRMPWRGD t214 PWROK t292 t293 Vcc 1 ICH7_S0_S5_S0_DT _S3HOT .vsd NOTES: 1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. 2. t293 is applicable when the system transitions from S0 to G3 only. Intel (R) ICH7 Family Datasheet 829 Electrical Characteristics Figure 23-25. S0 to S5 to S0 Timings, S3COLD (Mobile/Ultra Mobile Only) S0 S0 S3 S3 S4 S5 S3/S4/S5 S0 S0 STPCLK# DMI Message STP_CPU#, DPSLP#, DPRSTP# t280 t216 DPRSLPVR SUS_STAT# t283 t217 t285 STP_PCI# t218 t286 PLTRST# PCIRST# SLP_S3# (S3COLD Board Config) SLP_S4# t291 t300 t287 t302 t299 t297 t295 Wake Event PWROK t288 Vcc t290 t298 SLP_S5# t296 t214 NOTES: 1. t290 is applicable when the system transitions from S0 to G3 only. 2. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. 830 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-26. S0 to S5 to S0 Timings, S3HOT (Mobile/Ultra Mobile Only) S0 S0 S3 S3 S4 S5 S3/S4/S5 S0 S0 STPCLK# DMI Message t216 STP_CPU#, DPSLP#, DPRSTP# t280 DPRSLPVR SUS_STAT# t283 t217 t285 STP_PCI# t218 t286 PLTRST# PCIRST# SLP_S3# (S3HOT Board Config) SLP_S4# t291 t300 t287 t302 t299 t297 t295 t298 SLP_S5# Wake Event VRMPWRGD t292 Vcc t293 t296 NOTES: 1. t293 is applicable when the system transitions from S0 to G3 only. 2. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL, VccSATAPLL, and V5REF. Figure 23-27. C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only) CPU I/F Unlatched Signals STPCLK# Break Event t250 Latched Unlatched t273 t274 Intel (R) ICH7 Family Datasheet 831 Electrical Characteristics Figure 23-28. C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only) CPU I/F Unlatched Signals STPCLK# t250 Latched t274 Unlatched Bus Master DPSLP# Active Idle t253 t267 t269 STP_CPU# CPU Clocks Break Event Running t254 Stopped Running t268 C0_C3_Timing Figure 23-29. C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only) CPU I/F Signals STPCLK# Bus Master Active Idle Unlatched t250 Latched t274 Unlatched DPSLP# t253 t269 STP_CPU# t254 t268 CPU Clocks DPRSTP# Running Stopped t265 Running DPRSLPVR CPU Vcc Break Event t255 t266 C0_C4_Timing 832 Intel (R) ICH7 Family Datasheet Electrical Characteristics Figure 23-30. AC '97 Data Input and Output Timings (Desktop and Mobile Only) t142 t140 ACZ_BIT_CLK VIH VIL ACZ_SDOUT ACZ_SDIN[2:0] ACZ_SYNC VOH VOL t141 Figure 23-31. Intel(R) High Definition Audio Input and Output Timings ACZ_BIT_CLK ACZ_SDOUT t143 t144 t143 t144 ACZ_SDIN[2:0] t145 t146 Intel (R) ICH7 Family Datasheet 833 Electrical Characteristics Figure 23-32. SPI Timings (Desktop and Mobile Only) t182 t182 SPI_CLK t183 SPI_MOSI t184 t185 SPI_MISO t186 t187 SPI_CS# 834 Intel (R) ICH7 Family Datasheet Package Information 24 24.1 Note: Package Information Desktop and Mobile Package Information The ICH7 package information is shown in Figure 24-1, Figure 24-2, and Figure 24-3. All dimensions, unless otherwise specified, are in millimeters Figure 24-1. Intel(R) ICH7 Package (Top View) -A// 0.127 A PIN #1 IDENTIFIER -B- 22.10 REF 0.127 A 4 PLACES TOP VIEW Intel (R) ICH7 Family Datasheet 835 Package Information Figure 24-2. Intel(R) ICH7 Package (Bottom View) PIN #1 CORNER 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG 2 0.70 0.50 1 . 0 6 6 8 J K L M N P R T U V W Y AA AB AC AD AE AF AG AH 28 27 26 25 24 23 22 21 20 1.10 REF 1 . 0 6 6 8 AH 0.78 REF 0.78 REF 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW Figure 24-3. Intel(R) ICH7 Package (Side View) // 0.15 0.20 C -C- 3 SEATING PLANE SIDE VIEW 836 Intel (R) ICH7 Family Datasheet Package Information 24.2 Ultra Mobile Package Information Figure 24-4 is the Intel ICH7-U package drawing. Figure 24-4. Intel ICH7-U Package Drawing Intel (R) ICH7 Family Datasheet 837 Package Information 838 Intel (R) ICH7 Family Datasheet Testability (Desktop and Mobile Only) 25 Testability (Desktop and Mobile Only) The ICH7 supports XOR Chain test mode. This non-functional test mode is a dedicated test mode when the chip is not operating in its normal manner. The XOR Chain Mode is entered as indicated in Figure 25-1. Figure 25-1. XOR Chain Test Mode Selection, Entry and Testing XOR Chain Test Mode Selection, Entry and Testing PCICLK RSMRST#/ LAN_RST# RTCRST# PWROK REQ[4:1]# ACZ_SDOUT/ EE_DOUT TP3 / GPIO25 DMI_CLK HeldLow 5ms 10ms Run 120 ms Run 2 ms Chain Select (1-5) DMI_CLKp = `0' DMI_CLKn = `1' Toggle XOR Output Enabled Notes: RSMRST#, PWROK, RTCRST#, LAN_RST# must be held high during test mode and output testing. PCICLK & DMI_CLK should be approximately 1 MHz while running/toggling For chains 4 and 5, all PETx[n] signals (of that chain) must be driv en during testing. REQ# Settings REQ[4:1]# = 0000 REQ[4:1]# = 0001 REQ[4:1]# = 0010 REQ[4:1]# = 0011 REQ[4:1]# = 0100 REQ[4:1]# = 0111 XOR Chain XOR 1 XOR 2 XOR 3 XOR 4 XOR 5 ALL-Z Intel (R) ICH7 Family Datasheet 839 Testability (Desktop and Mobile Only) Figure 25-2. Example XOR Chain Circuitry Vcc XOR Chain Output Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6 XOR Chain Testability Algorithm Example XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 25-1. Table 25-1. XOR Test Pattern Example Vector 1 2 3 4 5 6 7 Input Pin 1 0 1 1 1 1 1 1 Input Pin 2 0 0 1 1 1 1 1 Input Pin 3 0 0 0 1 1 1 1 Input Pin 4 0 0 0 0 1 1 1 Input Pin 5 0 0 0 0 0 1 1 Input Pin 6 0 0 0 0 0 0 1 XOR Output 1 0 1 0 1 0 1 In this example, Vector 1 applies all 0s to the chain inputs. The outputs being noninverting will consistently produce a 1 at the XOR output on a good board. One short to VCC (or open floating to VCC) will result in a 0 at the chain output, signaling a defect. Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even number of input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board. One short to VSS (or open floating to VSS) will result in a 0 at the chain output, signaling a defect. It is important to note that the number of inputs pulled to 1 will affect the expected chain output value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of chain inputs pulled to 1 is odd, expect 0 at the output. Continuing with the example in Table 25-1, as the input pins are driven to 1 across the chain in sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence (e.g., "1011") will identify the location of the short or open. 840 Intel (R) ICH7 Family Datasheet Testability (Desktop and Mobile Only) 25.1 XOR Chain Tables Table 25-2. XOR Chain 1 (REQ[4:1]# = 0000) Pin Name ACZ_SYNC ACZ_SDOUT ACZ_BIT_CLK GPIO0 (Desktop Only) / BM_BUSY# (Mobile Only) GPIO16 (Desktop Only) / DPRSLPVR (Mobile Only) AD0 AD3 AD1 AD5 REQ[2]# GNT[2]# AD6 AD2 REQ[1]# GNT[1]# C/BE0# AD4 GNT[4]#/GPIO48 FRAME# AD9 STOP# REQ[4]#/GPIO22 AD13 AD11 AD10 C/BE1# REQ3# AD20 SERR# Ball # R6 T4 U1 AB18 Notes Top of XOR Chain Pin Name AD16 GNT3# TRDY# AD18 Ball # E12 F13 F14 D11 30th XOR Notes signal in AC22 E18 F18 C18 A18 C17 D17 E17 A16 C16 D16 B15 E16 A14 F16 C14 F15 A13 C13 D14 E14 C12 E13 A10 B10 AD26 GPIO1/REQ5# AD24 AD15 PAR AD22 AD28 GPIO17/GNT5# PIRQD# GNT0# REQ[0]# PIRQB# GPIO4/PIRQG# PIRQC# PIRQA# GPIO2/PIRQE# AD30 GPIO3/PIRQF# GPIO5/PIRQH# ACZ_SDIN2 ACZ_SDIN0 ACZ_SDIN1 ACZ_RST# A8 C8 D9 G13 E10 F10 C7 D8 B5 E7 D7 B4 F8 C5 A3 G8 E6 F7 G7 T1 T2 T3 R5 TP0 (Desktop Only) / BATLOW# (Mobile Only) C21 XOR Chain 1 OUTPUT Intel (R) ICH7 Family Datasheet 841 Testability (Desktop and Mobile Only) Table 25-3. XOR Chain 2 (REQ[4:1]# = 0001) Pin Name AD7 AD8 C/BE3# DEVSEL# Ball # A17 A15 C15 A12 Notes Top of XOR Chain 2nd signal in XOR Pin Name SATA0RXP SATA0RXN SATA0TXN SATA0TXP SATA1RXP (Desktop Only) Reserved (Mobile Only) SATA1RXN (Desktop Only) Reserved (Mobile Only) SATA1TXN (Desktop Only) Reserved (Mobile Only) SATA1TXP (Desktop Only) Reserved (Mobile Only) SATARBIAS SATARBIAS# GPIO7 GPIO33/ AZ_DOCK_EN# (Mobile Only) GPIO32/ (Desktop Only) / CLKRUN# (Mobile Only) GPIO21/SATA0GP MCH_SYNC# THRM# GPIO39 GPIO38 GPIO6 GPIO35/ SATACLKREQ# PLTRST# RI# TP3 PWRBTN# Ball # AE3 AF3 AG2 AH2 Notes 27th signal in XOR AD14 G15 AD5 AD12 B12 AE5 AD19 A11 AG4 C/BE2# D12 AH4 PCICLK AD17 AD25 PLOCK# A9 C11 B9 E11 AG10 AH10 AC18 AC19 PERR# IRDY# AD21 AD27 AD23 AD29 AD31 GPIO34/ AZ_DOCK_RST# (Mobile Only) LFRAME# LAD3 LAD0 LAD1 C9 A7 F11 A6 E9 B6 D6 U2 AB3 Y6 AA6 AB5 AG18 AF19 AH20 AF20 AE20 AD20 AC21 AD21 C26 A28 F21 C23 842 Intel (R) ICH7 Family Datasheet Testability (Desktop and Mobile Only) Table 25-3. XOR Chain 2 (REQ[4:1]# = 0001) (Continued) Pin Name LAD2 LDRQ0# Ball # AC4 AC3 Notes Pin Name GPIO8 TP0/BATLOW# EL_RSVD (Digital Home Only) / GPIO26 GPIO2/PIRQE# Ball # E21 C21 A21 XOR Chain 2 OUTPUT Notes G8 Table 25-4. XOR Chain 3 (REQ[4:1]# = 0010) Pin Name INTVRMEN INTRUDER# DD6 DD10 DD8 DD7 Ball # W4 Y5 AD12 AB13 AE12 AC12 Notes Top of XOR Chain 2nd signal in XOR Pin Name DCS3# DA0 DA2 DA1 GPIO19/SATA1GP INIT3_3V# GPIO18 (Desktop Only) / STP_PCI# (Mobile Only) GPIO20 (Desktop Only) / STP_CPU# (Mobile Only) VRMPWRGD RCIN# A20GATE INIT# NMI GPIO49/ CPUPRWRGD TP1 (Desktop Only) / DPRSTP# (Mobile Only) TP2 (Desktop Only) / DPSLP# (Mobile Only) INTR THRMTRIP# Ball # AD16 AH17 AF17 AE17 AH18 AG21 Notes 26th signal in XOR DD9 AF12 AC20 DD3 AF13 AF21 DD2 DD5 DD13 DD14 DD4 DD11 AG13 AC13 AH13 AH14 AD14 AC14 AD22 AG23 AE22 AF22 AH24 AG24 DD1 AE14 AF24 DD12 AF14 AH25 DIOR# DDREQ AF15 AE15 AF25 AF26 Intel (R) ICH7 Family Datasheet 843 Testability (Desktop and Mobile Only) Table 25-4. XOR Chain 3 (REQ[4:1]# = 0010) (Continued) Pin Name DD15 DIOW# DD0 IDEIRQ IORDY DDACK# Ball # AC15 AH15 AB15 AH16 AG16 AF16 Notes Pin Name CPUSLP# STPCLK# A20M# SPKR OC4# SPI_MISO SPI_ARB SPI_MOSI SPI_CS# SPI_CLK DCS1# AE16 RI# Ball # AG27 AH22 AH28 A19 E5 P2 P1 P5 P6 R2 A28 XOR Chain 3 OUTPUT Notes Table 25-5. XOR Chain 4-1 (REQ[4:1]# = 0011) Pin Name DMI3RXP DMI3RXN Ball # AD24 AD25 Notes Top of XOR Chain 2nd signal in XOR Pin Name SMLINK0 SMLINK1 EL_STATE1 (Digital Home Only) / GPIO28 SLP_S3# SLP_S4# SLP_S5# GPIO15 SMBALERT#/ GPIO11 Must be driven for all skus including ICH7 Base Must be driven for all skus including ICH7 Base Must be driven for all skus including ICH7 Base Ball # B25 A25 Notes 23nd signal in XOR DMI3TXP AC27 E23 DMI3TXN DMI2RXP DMI2RXN DMI2TXP DMI2TXN PERp6 / Reserved (intel(R) ICH7 Base) PERn6 / Reserved (intel(R) ICH7 Base) PETp6 / Reserved (intel(R) ICH7 Base) AC28 AB25 AB26 AA27 AA28 B24 D23 F22 E22 B23 T24 SMBCLK C22 T25 GPIO25 D20 R27 WAKE# F20 844 Intel (R) ICH7 Family Datasheet Testability (Desktop and Mobile Only) Table 25-5. XOR Chain 4-1 (REQ[4:1]# = 0011) (Continued) Pin Name PETn6 / Reserved (intel(R) ICH7 Base) PERp4 PERn4 PETp4 PETn4 Ball # Notes Must be driven for all skus including ICH7 Base Pin Name Ball # Notes R28 GPIO9 E20 M25 M26 L27 L28 SMBDATA GPIO13 SYS_RST# SUSCLK EL_STATE0 (Digital Home Only) / GPIO27 GPIO12 GPIO10 PME# PCIRST# GPIO8 B22 E19 A22 C20 PERp3 K25 B21 PERn3 PETp3 PETn3 LINKALERT# SUS_STAT# 2 K26 J27 J28 A26 A27 F19 A20 B19 B18 E21 XOR Chain 4-1 OUTPUT Table 25-6. XOR Chain 4-2 (REQ[4:1]# = 0011) Pin Name OC6#/GPIO30 OC7#/GPIO31 OC2# OC1# OC3# OC0# OC5#/GPIO29 CLK48 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N Ball # A2 B3 D5 C4 D4 D3 C3 B2 F1 F2 G4 G3 H1 H2 J4 Notes Top of XOR Chain 2nd signal in XOR Pin Name LAN_CLK LAN_RXD0 LAN_TXD0 LAN_RXD1 EE_SHCLK EE_DIN LAN_TXD2 LAN_TXD1 EE_DOUT CLK14 LDRQ1#/GPIO23 SATA2RXP SATA2RXN SATA2TXN SATA2/TXP SATA3RXP (Desktop Only) Reserved (Mobile Only) Ball # V3 U5 U7 V4 Y1 W3 V7 V6 Y2 AC1 AA5 AE7 AF7 AG6 AH6 Notes 30th signal in XOR USBP3P J3 AE9 Intel (R) ICH7 Family Datasheet 845 Testability (Desktop and Mobile Only) Table 25-6. XOR Chain 4-2 (REQ[4:1]# = 0011) (Continued) Pin Name Ball # Notes Pin Name SATA3RXN (Desktop Only) Reserved (Mobile Only) SATA3TXN (Desktop Only) Reserved (Mobile Only) SATA3TXP (Desktop Only) Reserved (Mobile Only) SATALED# GPIO37/SATA3GP GPIO36/SATA2GP SERIRQ SMI# IGNNE# FERR# Ball # Notes USBP4N K1 AD9 USBP4P K2 AG8 USBP5N L4 AH8 USBP5P USBP6N USBP6P USBP7N USBP7P GPIO24 GPIO14 LAN_RSTSYNC LAN_RXD2 EE_CS 2 L5 M1 M2 N4 N3 R3 R4 U3 T5 W1 AF18 AE19 AH19 AH21 AF23 AG22 AG26 PLTRST# C26 XOR Chain 4-2 OUTPUT Table 25-7. XOR Chain 5 (REQ[4:1]# = 0100) Pin Name Ball # Notes Top of XOR Chain 2nd signal in XOR Pin Name PETn5 / Reserved (intel(R) ICH7 Base) PERp2 PERn2 PETp2 PETn2 PERp1 PERn1 PETp1 Ball # Notes Must be driven for all skus including ICH7 Base DMI1RXP Y25 N28 DMI1RXN DMI1TXP DMI1TXN DMI0RXP DMI0RXN DMI0TXP DMI0TXN Y26 W27 W28 V25 V26 U27 U28 H25 H26 G27 G28 F25 F26 E27 846 Intel (R) ICH7 Family Datasheet Testability (Desktop and Mobile Only) Table 25-7. XOR Chain 5 (REQ[4:1]# = 0100) (Continued) Pin Name PERp5 / Reserved (intel(R) ICH7 Base) PERn5 / Reserved (intel(R) ICH7 Base) PETp5 / Reserved (intel(R) ICH7 Base) Ball # Notes Must be driven for all skus including ICH7 Base Must be driven for all skus including ICH7 Base Must be driven for all skus including ICH7 Baes XOR Chain 5 OUTPUT Pin Name Ball # Notes P25 PETn1 E28 P26 N27 GPIO2/PIRQE# G8 Intel (R) ICH7 Family Datasheet 847 Testability (Desktop and Mobile Only) 848 Intel (R) ICH7 Family Datasheet |
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